JPH0440878B2 - - Google Patents

Info

Publication number
JPH0440878B2
JPH0440878B2 JP60138722A JP13872285A JPH0440878B2 JP H0440878 B2 JPH0440878 B2 JP H0440878B2 JP 60138722 A JP60138722 A JP 60138722A JP 13872285 A JP13872285 A JP 13872285A JP H0440878 B2 JPH0440878 B2 JP H0440878B2
Authority
JP
Japan
Prior art keywords
electrode
insulating layer
design change
connection pad
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60138722A
Other languages
English (en)
Other versions
JPS61296800A (ja
Inventor
Koji Kanehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP60138722A priority Critical patent/JPS61296800A/ja
Priority to US06/875,670 priority patent/US4710592A/en
Priority to DE8686108689T priority patent/DE3677417D1/de
Priority to EP86108689A priority patent/EP0206337B1/en
Publication of JPS61296800A publication Critical patent/JPS61296800A/ja
Publication of JPH0440878B2 publication Critical patent/JPH0440878B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5382—Adaptable interconnections, e.g. for engineering changes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0292—Programmable, customizable or modifiable circuits having a modifiable lay-out, i.e. adapted for engineering changes or repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4076—Through-connections; Vertical interconnect access [VIA] connections by thin-film techniques
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は配線基板上に形成される設計変更用電
極に関する。
〔従来の技術〕
従来の多層配線基板における設計変更用電極の
一例が、IBM J.RES.DEVELOP，VOL.26，No.
１，JAN.1982の第30頁〜第36頁に所載のA.J.
Blodgett等の“Termal Conduction Module：
Ａ High−Performance Maltilayer Ceramic
Package”と題する論文に開示されている。第３
図はこのような電極を示す。この電極は、集積回
路チツプまたはワイヤー（導電線）を接続する接
続部分３１と、設計変更時にパツド間を切り離す
切断部分３２とから構成され、各部分３１および
３２は層構成も導体材料も同じであり、構造上の
差異はない。基板上にこのような電極が形成され
たあと、この電極および他の必要部分を残して、
絶縁膜により基板上が覆われる。
〔発明が解決しようとする問題点〕
上述した従来の電極構造では、チツプやワイヤ
ーを半田づけするときには、基板上の配線パター
ンに半田が流れないよう設計変更電極上にソルダ
ーダムを設ける必要がある。すなわち、電極形成
後、さらにソルダーダム形成工程が必要となる。
ソルダーダム形成工程では、パターン化、硬化お
よび焼成等の処理が必要であるため、設計変更電
極の表面を酸化物等を生じない金属で形成しなけ
ればならず、この結果、半田ぬれ性や切断性を十
分に満足する材料だけで電極を形成することがで
きないという欠点がある。
〔問題点を解決するための手段〕
本発明の電極は、基板上に形成した電極部と、
該電極部を少なくとも２つの部分に切断できるよ
うに該電極部の一部を露出させて該電極部を覆う
絶縁層と、それぞれ前記２つの部分に対向する前
記絶縁層上の対応位置に形成した少なくとも２つ
の接続用パツドと、前記接続用パツドと前記電極
部とを接続するよう前記絶縁層を貫通するビアホ
ールとから構成される。
〔実施例〕
次に本発明について図面を参照して詳細に説明
する。
第１図を参照すると、本発明の一実施例は、内
部に各種の配線パターン（図示せず）を有する配
線層部（基板）１１と、配線層部１１上に形成さ
れ配線部分１２および切断部分１３からなる電極
部１９と、電極部１９を２つの部分に切断できる
ように電極部１９の切断部分１３を露出させて電
極部１９を覆う絶縁層１４と、配線部分１２に対
向する絶縁層１４上の対応位置に形成した２つの
接続用パツド１８と、接続用パツド１８と配線部
分１２とを電気的に接続するよう絶縁層１４を貫
通するビアホール１６と、前記各種の配線パター
ンの一部と配線部分１２とを電気的に接続するビ
アホール１７とから構成される。設計変更時に
は、電極部１９は、露出部１５を介して超音波カ
ツタやレーザー光線等により切断部分１３で切断
できる。電極部１９は、電気抵抗の低減および切
断の容易性を考慮して、スパツタリングにより形
成されたクロムおよびパラジウム膜上に金をめつ
きすることにより構成される。パツド１８は、半
田ぬれ性を考慮して、スパツタリングにより形成
されたクロム、パラジウムおよび銅膜上に半田ぬ
れ性のよい銅をめつきすることにより構成され
る。この方法では、銅層の形成が多層化の最終工
程となるため、銅の酸化等は全く発生しない。本
実施例では、絶縁層１４がソルダーダムとして働
き、半田が他の配線パターンに流れるのを阻止し
ている。
第２図を参照すると、本発明の第２の実施例の
断面図を第２図に示す。２１から２７は、接続用
パツド２８の構成以外は第１の実施例と全同じ構
成である。パツド２８は、クロム・パラジウム・
銅スパツタ膜の上に銅・ニツケル・金の多層めつ
きを行なうことにより形成され、接続用パツドを
酸化等から保護している。本実施例でも、電極の
形成が多層化の最終工程となるため、金の熱拡
散、熱膨張率の違いによる多層めつき間での剥れ
等は全く生じない。
〔発明の効果〕
以上、説明したように、本発明は設計変更電極
のチツプおよびワイヤー接続部を最上層に形成
し、配線部分やパターン切断部分をパツドの下に
絶縁層を介して形成することにより、接続性や切
断性に対してそれぞれすぐれた性質をもつた金属
を使つて設計変更電極を形成できるという効果が
ある。
【図面の簡単な説明】
第１図は本発明の第１の実施例の断面図、第２
図は本発明の第２の実施例の断面図および第３図
は従来例を示す斜視図である。 図において、１１……基板、１２……配線部
分、１３……切断部分、１４……絶縁層、１５…
…露出部、１６……ビアホール、１７……ビアホ
ール、１８……パツド、２８……パツド、３１…
…接続部、３２……切断部。

Claims (1)

  1. 【特許請求の範囲】 １ 配線基板上に形成される設計変更用電極にお
    いて、前記基板上に形成した電極部と、該電極部
    を少なくとも２つの部分に切断できるように該電
    極部の一部を露出させて該電極部を覆う絶縁層
    と、それぞれ前記２つの部分に対向する前記絶縁
    層上の対応位置に形成した少なくとも２つの接続
    用パツドと、前記接続用パツドと前記電極部とを
    接続するよう前記絶縁層を貫通するビアホールと
    から構成したことを特徴とする設計変更用電極。 ２ 前記接続用パツドと、前記切断部分とを異な
    る導電材料より形成したことを特徴とする特許請
    求の範囲第１項記載の設計変更用電極。 ３ 前記接続用パツドが銅を含むことを特徴とす
    る特許請求の範囲第１項記載の設計変更用電極。 ４ 前記接続用パツドの表面の材料が貴金属であ
    ることを特徴とする特許請求の範囲第３項記載の
    設計変更用電極。
JP60138722A 1985-06-25 1985-06-25 設計変更用電極 Granted JPS61296800A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60138722A JPS61296800A (ja) 1985-06-25 1985-06-25 設計変更用電極
US06/875,670 US4710592A (en) 1985-06-25 1986-06-18 Multilayer wiring substrate with engineering change pads
DE8686108689T DE3677417D1 (de) 1985-06-25 1986-06-25 Mehrschichtleitersubstrat mit kontaktflecken zum aendern von verbindungen.
EP86108689A EP0206337B1 (en) 1985-06-25 1986-06-25 Multilayer wiring substrate with engineering change pads

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60138722A JPS61296800A (ja) 1985-06-25 1985-06-25 設計変更用電極

Publications (2)

Publication Number Publication Date
JPS61296800A JPS61296800A (ja) 1986-12-27
JPH0440878B2 true JPH0440878B2 (ja) 1992-07-06

Family

ID=15228614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60138722A Granted JPS61296800A (ja) 1985-06-25 1985-06-25 設計変更用電極

Country Status (4)

Country Link
US (1) US4710592A (ja)
EP (1) EP0206337B1 (ja)
JP (1) JPS61296800A (ja)
DE (1) DE3677417D1 (ja)

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FR2404990A1 (fr) * 1977-10-03 1979-04-27 Cii Honeywell Bull Substrat d'interconnexion de composants electroniques a circuits integres, muni d'un dispositif de reparation
US4210885A (en) * 1978-06-30 1980-07-01 International Business Machines Corporation Thin film lossy line for preventing reflections in microcircuit chip package interconnections
US4245273A (en) * 1979-06-29 1981-01-13 International Business Machines Corporation Package for mounting and interconnecting a plurality of large scale integrated semiconductor devices
US4447857A (en) * 1981-12-09 1984-05-08 International Business Machines Corporation Substrate with multiple type connections
US4489364A (en) * 1981-12-31 1984-12-18 International Business Machines Corporation Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface
US4549200A (en) * 1982-07-08 1985-10-22 International Business Machines Corporation Repairable multi-level overlay system for semiconductor device

Also Published As

Publication number Publication date
EP0206337A3 (en) 1987-03-04
JPS61296800A (ja) 1986-12-27
EP0206337A2 (en) 1986-12-30
EP0206337B1 (en) 1991-02-06
US4710592A (en) 1987-12-01
DE3677417D1 (de) 1991-03-14

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