JPH0438039A - Signal interruption detection circuit - Google Patents
Signal interruption detection circuitInfo
- Publication number
- JPH0438039A JPH0438039A JP14575290A JP14575290A JPH0438039A JP H0438039 A JPH0438039 A JP H0438039A JP 14575290 A JP14575290 A JP 14575290A JP 14575290 A JP14575290 A JP 14575290A JP H0438039 A JPH0438039 A JP H0438039A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse
- output terminal
- output
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 21
- 239000003990 capacitor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003708 edge detection Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は信号断検出回路に関し、特にディジタルデータ
伝送用の信号断検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal disconnection detection circuit, and more particularly to a signal disconnection detection circuit for digital data transmission.
従来のこの種の信号断検出回路は、第３図のように、モ
ノステーブルマルチバイブレータ９に時定数設定用の抵
抗器Ｒおよび蓄電器Ｃを接続した構成を有しており、入
力端子１に与えられたディジタル入力信号は、モノステ
ーブルマルチバイブレータ４の入力端Ａに加えられ、信
号にパルス立上りが現れると出力をロー電圧” Ｌ ”
とし、蓄電器Ｃを瞬時に充電する。モノステーブルマル
チバイブレータ４の出力端Ｑでは抵抗器Ｒと蓄電器Ｃと
で得られる時定数の期間”Ｌ”が保持される。As shown in FIG. 3, this type of conventional signal disconnection detection circuit has a configuration in which a monostable multivibrator 9 is connected to a time constant setting resistor R and a capacitor C. The digital input signal is applied to the input terminal A of the monostable multivibrator 4, and when a pulse rise appears in the signal, the output is set to a low voltage "L".
and charges the capacitor C instantly. At the output terminal Q of the monostable multivibrator 4, "L" is maintained for a period of time constant obtained by the resistor R and the capacitor C.
“し”の圧力期間中に次のパルス立上がりが入力される
と、蓄電器Ｃは再び充電されその時点から再び抵抗器Ｒ
と蓄電器Ｃとで得られる時定数の期間、出力端Ｑは“Ｌ
”に保持される。時定数の期間を過ぎても入力信号の
パルス立上がりが無い場合は、出力端Ｑはハイ電圧°“
Ｈ′“どなる。この抵抗器Ｒおよび蓄電器Ｃで得られる
時定数の期間以上に入力端子１にパルス立上がりが現れ
ない場合に、信号断が生じたと見なしている。When the next pulse rise is input during the "resistance" pressure period, the capacitor C is charged again and from that point on, the resistor R is again
During the time constant period obtained by the capacitor C and the capacitor C, the output terminal Q is “L”.
”. If there is no pulse rise of the input signal even after the time constant period, the output terminal Q becomes a high voltage °“
If a pulse rise does not appear at input terminal 1 for a period longer than the time constant obtained by resistor R and capacitor C, it is considered that a signal disconnection has occurred.
この従来の信号断検出回路では、検出周期の精度が抵抗
器及び蓄電器の精度で決定され高精度を得られず、また
電源変動及び温度変動があると蓄電器の容量変化及びモ
ノステーブルマルチバイブレータに流れ込む電流の変化
により時定数の値が変わり検出周期も変動してしまうと
いう問題点がある。In this conventional signal disconnection detection circuit, the accuracy of the detection cycle is determined by the accuracy of the resistor and capacitor, and high accuracy cannot be obtained.Furthermore, when there is a power supply fluctuation or temperature fluctuation, the capacitance of the capacitor changes and the flow flows into the monostable multivibrator. There is a problem in that the value of the time constant changes due to changes in the current, and the detection period also changes.
本発明の信号断検出回路は、予め定めた周期をもつクロ
ック信号を分周して断検出周期のタイミングを示す第１
のパルス信号を発生する計数回路と、ディジタル入力信
号の各パルスの前縁および後縁を検出してそのタイミン
グを示す第２のパルス信号を発生するゲート回路と、前
記第１のパルス信号のタイミングごとにセットされ前記
第２のパルス信号ごとにセット中断される第１のフリッ
プフロップと、該第１のフリップフロップのセット状懸
を前記第１のパルス信号のタイミングごとに読取って出
力する第２のフリップフロップとを備えている。The signal disconnection detection circuit of the present invention divides a clock signal having a predetermined cycle to provide a first clock signal indicating the timing of the disconnection detection cycle.
a counting circuit that generates a pulse signal; a gate circuit that detects leading and trailing edges of each pulse of the digital input signal and generates a second pulse signal indicating the timing thereof; and a timing circuit of the first pulse signal. a first flip-flop whose setting is interrupted every time the second pulse signal is set; and a second flip-flop which reads and outputs the set state of the first flip-flop at every timing of the first pulse signal. It has flip-flops.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図であり、第２図は本
実施例の動作を例示する信号タイミング図である。入力
端子１に信号ａのような波形が入力されると、反転ゲー
ト３および排他的論理和ゲート４から成る前後縁検出回
路から信号すが出力される。一方、予め定めた周期のク
ロックパルスを発生する発振器２の出力を信号を計数回
路５で分周して、断検出周期Ｔ１パルスである信号Ｃを
得る。フリップフロップ６は信号すのパルス立上がりご
とに入力端りに与えである“Ｌ”を読み取って出力端Ｑ
を“Ｌ”とする。次に信号Ｃのパルス立上がりにてセッ
トされ出力端Ｑは“Ｈ”となる。フリップフロップ７は
、信号Ｃのパルス立上がりごとに入力端りに与えられる
フリップフロップ６の出力信号を読み取って、出力端Ｑ
から出力端子８へ出力する。FIG. 1 is a circuit diagram of one embodiment of the present invention, and FIG. 2 is a signal timing diagram illustrating the operation of this embodiment. When a waveform such as the signal a is input to the input terminal 1, a leading and trailing edge detection circuit comprising an inverting gate 3 and an exclusive OR gate 4 outputs a signal A. On the other hand, a signal output from an oscillator 2 that generates clock pulses with a predetermined cycle is frequency-divided by a counting circuit 5 to obtain a signal C that is a pulse with an interruption detection cycle T1. The flip-flop 6 reads "L" applied to the input terminal every time the pulse of the signal S rises, and outputs it to the output terminal Q.
is "L". Next, it is set at the rising edge of the signal C pulse, and the output terminal Q becomes "H". The flip-flop 7 reads the output signal of the flip-flop 6 applied to the input terminal every time the pulse of the signal C rises, and outputs the output signal to the output terminal Q.
The signal is output from the output terminal 8.
信号Ｃの断検出周期Ｔｌ内に信号すのパルス立上りが少
くとも１つ現われれば、出力端子８は“Ｌ”を保持する
が、信号すのパルス立上がりが現われない場合、フリッ
プフロップ７の入力が′″Ｈ”に変り、出力端子８はＨ
”を出力する。If at least one rising pulse of the signal C appears within the detection cycle Tl of the signal C, the output terminal 8 holds "L"; however, if no rising pulse of the signal C appears, the input of the flip-flop 7 changes to ``H'', and the output terminal 8 becomes H.
” is output.
この状態を信号断と判断することができる。この信号Ｃ
のパルス立上がり間の時間Ｔ１は、発振器５の周波数精
度を上げることにより高精度化できる。This state can be determined to be a signal disconnection. This signal C
The time T1 between pulse rises can be made more accurate by increasing the frequency accuracy of the oscillator 5.
以上説明したように本発明によれば、発振器のクロック
出力から計数回路によって断検出周期を作ることにより
、断検出周期の精度を上げると共に、電源変動および温
度変動に対する断検出周期の変動も発振器の周波数変動
範囲内に抑えることが出来る。As explained above, according to the present invention, by creating the disconnection detection period using the counting circuit from the clock output of the oscillator, the accuracy of the disconnection detection period is improved, and fluctuations in the disconnection detection period due to power supply fluctuations and temperature fluctuations are also prevented. It is possible to suppress the frequency fluctuation within the range.
第１図は本発明の一実施例の回路図、第２図は本発明の
実施例の信号タイミング図、第３図は従来の信号断検出
回路の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a signal timing diagram of the embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional signal disconnection detection circuit.
１・・・入力端子、２・・・発振器、３・・・反転ゲー
ト、４・・・排他的論理和ゲート、５・・・計数回路、
６．７・・・フリップフロップ、８・・・出力端子。DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Oscillator, 3... Inverting gate, 4... Exclusive OR gate, 5... Counting circuit,
6.7...Flip-flop, 8...Output terminal.
Claims (1)
周期のタイミングを示す第１のパルス信号を発生する計
数回路と、ディジタル入力信号の各パルスの前縁および
後縁を検出してそのタイミングを示す第２のパルス信号
を発生するゲート回路と、前記第１のパルス信号のタイ
ミングごとにセットされ前記第２のパルス信号ごとにセ
ット中断される第１のフリップフロップと、該第１のフ
リップフロップのセット状態を前記第１のパルス信号の
タイミングごとに読取って出力する第２のフリップフロ
ップとを備えていることを特徴とする信号断検出回路。A counting circuit that divides a clock signal with a predetermined period to generate a first pulse signal indicating the timing of the disconnection detection cycle, and a counting circuit that detects the leading and trailing edges of each pulse of the digital input signal and its timing. a gate circuit that generates a second pulse signal indicating the first pulse signal; a first flip-flop that is set at each timing of the first pulse signal and whose setting is interrupted at each of the second pulse signal; and a second flip-flop that reads and outputs the set state of the first pulse signal at each timing of the first pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14575290A JPH0438039A (en) | 1990-06-04 | 1990-06-04 | Signal interruption detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14575290A JPH0438039A (en) | 1990-06-04 | 1990-06-04 | Signal interruption detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438039A true JPH0438039A (en) | 1992-02-07 |
Family
ID=15392339
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14575290A Pending JPH0438039A (en) | 1990-06-04 | 1990-06-04 | Signal interruption detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438039A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994010801A1 (en) * | 1992-11-05 | 1994-05-11 | Ampex Systems Corporation | Input clock presence detector for a digital video input signal |
-
1990
- 1990-06-04 JP JP14575290A patent/JPH0438039A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994010801A1 (en) * | 1992-11-05 | 1994-05-11 | Ampex Systems Corporation | Input clock presence detector for a digital video input signal |
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