JPH04373151A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04373151A JPH04373151A JP17720391A JP17720391A JPH04373151A JP H04373151 A JPH04373151 A JP H04373151A JP 17720391 A JP17720391 A JP 17720391A JP 17720391 A JP17720391 A JP 17720391A JP H04373151 A JPH04373151 A JP H04373151A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- insulating film
- layer
- shield layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は微細化された配線層を有
する半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a finer wiring layer.
【０００２】0002
【従来の技術】半導体装置の配線構造の断面図を図５に
示す。下地の絶縁層２上に配線４が形成され、配線４上
には絶縁膜６が形成されている。配線４はメタル配線、
又はゲート電極につながる多結晶シリコン層にてなる配
線である。半導体装置の微細化にともなって配線間のピ
ッチ（図中ではｄ１＋ｄ２）も狭くなりつつある。現在
主流になりつつある０．８μｍのデザインルールでは、
その配線間ピッチは２．０〜２．３μｍ程度である。ま
た、配線４の厚さｈは配線間の間隔ｄ２に近づきつつあ
る。このような微細な構造では、これまでの粗いパター
ンでは問題にならなかった配線間のカップリング容量は
もちろんのこと、配線間の信号の重畳など、ＡＣ的なク
ロストークも問題になってくる。特に、高周波デバイス
やアナログ回路に用いられる高速デバイスなどでは、こ
れらのノイズの問題は今後重要視されるのは必至である
。2. Description of the Related Art A cross-sectional view of a wiring structure of a semiconductor device is shown in FIG. A wiring 4 is formed on the underlying insulating layer 2, and an insulating film 6 is formed on the wiring 4. Wiring 4 is metal wiring,
Alternatively, it is a wiring made of a polycrystalline silicon layer connected to the gate electrode. With the miniaturization of semiconductor devices, the pitch between interconnects (d1+d2 in the figure) is also becoming narrower. With the 0.8 μm design rule, which is currently becoming mainstream,
The pitch between the wirings is about 2.0 to 2.3 μm. Further, the thickness h of the wiring 4 is approaching the distance d2 between the wirings. In such a fine structure, not only coupling capacitance between wirings, which has not been a problem with conventional coarse patterns, but also AC crosstalk such as signal superimposition between wirings becomes a problem. Particularly in high-speed devices used in high-frequency devices and analog circuits, these noise problems will inevitably become more important in the future.
【０００３】0003
【発明が解決しようとする課題】しかしながら、配線間
のクロストークなどの問題に対する対策としては、配線
間の距離を長くする方法などが採られているだけであり
、それでは微細化や高集積化の流れに反するものとなる
。本発明は半導体装置の微細化や高集積化を達成しなが
ら、かつ上記のような配線間のカップリングやクロスト
ークなどの問題をなくした配線構造をもつ半導体装置を
提供することを目的とするものである。[Problem to be solved by the invention] However, as a countermeasure to problems such as crosstalk between wires, methods such as increasing the distance between wires are only taken, but this does not allow for miniaturization and high integration. It goes against the flow. An object of the present invention is to provide a semiconductor device having a wiring structure that eliminates problems such as coupling and crosstalk between wirings, while achieving miniaturization and high integration of the semiconductor device. It is something.
【０００４】0004
【課題を解決するための手段】本発明では、互いに接近
して配置された配線を有する少なくとも１つの配線層で
、配線とは絶縁されたシールド用導電体層（以下、シー
ルド層という）を設ける。そのようなシールド層は、隣
接する配線間から配線上にわたって設けてもよく、隣接
する配線間のみに設けてもよく、各配線の上部から側部
にわたって設けてもよい。[Means for Solving the Problems] In the present invention, a shielding conductor layer (hereinafter referred to as a shield layer) is provided in at least one wiring layer having wirings arranged close to each other and insulated from the wirings. . Such a shield layer may be provided between adjacent wires and over the wires, may be provided only between adjacent wires, or may be provided from the top to the side of each wire.
【０００５】[0005]
【実施例】図１は一実施例を表わす。下地絶縁膜２上に
配線４が形成されている。下地２は例えばＭＯＳトラン
ジスタなどの素子が形成されたシリコン基板上に形成さ
れた絶縁膜や、下層配線層との間の層間絶縁膜である。
配線４はアルミニウム配線や、ゲート電極につながる多
結晶シリコン配線などであり、その厚さは例えば６００
０〜１００００Åである。配線４上には下層の絶縁膜６
ａとして例えばＣＶＤ法によるシリコン酸化膜が例えば
５００〜１０００Åの厚さに形成されている。下層の絶
縁膜６ａ上にはシールド層として厚さが例えば５００〜
１０００Åのメタル膜、例えばアルミニウム膜８が形成
されている。アルミニウム膜８上には上層の絶縁膜６ｂ
として厚さが例えば３０００〜８０００ÅのＣＶＤ法に
よるシリコン酸化膜が形成されている。この２層の絶縁
膜６ａ，６ｂが配線４とその上層の配線との層間絶縁膜
や保護膜となる。Embodiment FIG. 1 shows an embodiment. A wiring 4 is formed on the base insulating film 2. The base 2 is, for example, an insulating film formed on a silicon substrate on which elements such as MOS transistors are formed, or an interlayer insulating film between it and a lower wiring layer. The wiring 4 is an aluminum wiring or a polycrystalline silicon wiring connected to the gate electrode, and its thickness is, for example, 600 mm.
It is 0 to 10000 Å. A lower insulating film 6 is placed on the wiring 4.
As a, a silicon oxide film is formed by, for example, a CVD method to a thickness of, for example, 500 to 1000 Å. A shield layer with a thickness of, for example, 500 mm or more is provided on the lower insulating film 6a.
A metal film, for example, an aluminum film 8, with a thickness of 1000 Å is formed. An upper insulating film 6b is formed on the aluminum film 8.
A silicon oxide film having a thickness of, for example, 3000 to 8000 Å is formed by CVD. These two layers of insulating films 6a and 6b serve as an interlayer insulating film and a protective film between the wiring 4 and the wiring in the upper layer.
【０００６】シールド層８が隣接する配線４，４間に存
在できるように、下層絶縁膜６ａは配線４とシールド層
８との絶縁の信頼性が確保できる範囲で薄くするのが好
ましい。配線４にこの２層の絶縁膜６ａ，６ｂを経てそ
の上層のメタル配線との間に接続がなされる場合は、そ
の接続用スルーホールを設ける部分のシールド層８には
予めスルーホール部にアルミニウム膜が存在しないよう
にパターン化を施しておく。[0006] In order to allow the shield layer 8 to exist between the adjacent wires 4, the lower insulating film 6a is preferably made as thin as possible to ensure the reliability of the insulation between the wires 4 and the shield layer 8. When a connection is made between the wiring 4 and the metal wiring in the upper layer through the two layers of insulating films 6a and 6b, the shield layer 8 in which the through hole for connection is provided is preliminarily coated with aluminum in the through hole. Patterning is applied so that no film exists.
【０００７】図２は第２の実施例を表わす。図２ではシ
ールド層１０は、下層の絶縁膜６ａと上層の絶縁膜６ｂ
の間のうち、隣接する配線４，４の間の領域にのみ埋め
込まれた状態で形成されている。このように配線間の部
分のみにシールド層１０を設けることにより、配線４の
寄生容量を抑え、また配線間部分での絶縁膜表面を平坦
化する効果も得られる。FIG. 2 shows a second embodiment. In FIG. 2, the shield layer 10 includes a lower insulating film 6a and an upper insulating film 6b.
It is formed so as to be buried only in the region between the adjacent wirings 4, 4. By providing the shield layer 10 only in the portions between the wires in this way, it is possible to suppress the parasitic capacitance of the wires 4 and to flatten the surface of the insulating film in the portions between the wires.
【０００８】図３は第３の実施例を表わす。図３ではシ
ールド層１２は各配線４の側面と上面を取り囲むように
形成されており、配線間の部分ではつながっていない。
図３では、シールド層１２をＡＣ的にグラウンド電位と
するか、その場合の容量が問題になる場合はオペアンプ
などのバッファ回路を介して配線４とシールド層１２を
同電位にすれば、低容量でシールド効果も実現すること
ができる。FIG. 3 shows a third embodiment. In FIG. 3, the shield layer 12 is formed so as to surround the side and top surfaces of each wiring 4, and is not connected at the portions between the wirings. In FIG. 3, the shield layer 12 can be set to AC ground potential, or if the capacitance is a problem in that case, the wiring 4 and the shield layer 12 can be set to the same potential via a buffer circuit such as an operational amplifier, thereby reducing the capacitance. A shielding effect can also be achieved.
【０００９】図４は図１の実施例の製造方法を表わす。
（Ａ）下地２上にメタル膜を堆積し、写真製版とエッチ
ングによりパターン化を施して配線４を形成する。
（Ｂ）ＣＶＤ法により全面に下層シリコン酸化膜６ａを
例えば５００〜１０００Åの厚さに堆積する。
シリコン酸化膜６ａ上に蒸着法やスパッタリング法によ
りシールド層としてアルミニウム膜８を例えば５００〜
１０００Åの厚さに堆積する。
（Ｃ）アルミニウム膜８上にＣＶＤ法により上層シリコ
ン酸化膜６ｂを例えば３０００〜８０００Åの厚さに堆
積する。
図２及び図３の実施例では、下層の絶縁膜６ａ上にシー
ルド層を堆積した後、配線間部分や、配線の側面と上面
部分にシールド層を残すように写真製版とエッチングに
よりパターン化を施した後、上層の絶縁膜６ｂを堆積す
る。図１や図３の実施例では、さらに上層に配線を形成
した場合に上下の配線層間でのクロストークを防ぐこと
もできる。FIG. 4 shows a method of manufacturing the embodiment of FIG. (A) A metal film is deposited on the base 2 and patterned by photolithography and etching to form the wiring 4. (B) A lower silicon oxide film 6a is deposited over the entire surface by CVD to a thickness of, for example, 500 to 1000 Å. For example, an aluminum film 8 is formed as a shield layer on the silicon oxide film 6a by vapor deposition or sputtering.
Deposit to a thickness of 1000 Å. (C) An upper silicon oxide film 6b is deposited on the aluminum film 8 by CVD to a thickness of, for example, 3000 to 8000 Å. In the embodiments shown in FIGS. 2 and 3, after a shield layer is deposited on the lower insulating film 6a, it is patterned by photolithography and etching so as to leave the shield layer between the wirings and on the side and top surfaces of the wirings. After this, an upper insulating film 6b is deposited. In the embodiments shown in FIGS. 1 and 3, crosstalk between upper and lower wiring layers can also be prevented when wiring is further formed in an upper layer.
【００１０】0010
【発明の効果】本発明では配線間にシールド層が存在す
るので、配線間のクロストークなどのＡＣ的ノイズを低
減することができる。また、図１や図３の実施例では、
さらに上層に配線を形成した場合に上下の配線層間での
クロストークなどを防ぐこともできる。Effects of the Invention In the present invention, since a shield layer exists between wiring lines, AC noise such as crosstalk between wiring lines can be reduced. Furthermore, in the embodiments shown in FIGS. 1 and 3,
Furthermore, when wiring is formed in the upper layer, it is also possible to prevent crosstalk between upper and lower wiring layers.
【図１】第１の実施例を示す要部断面図である。FIG. 1 is a sectional view of a main part showing a first embodiment.
【図２】第２の実施例を示す要部断面図である。FIG. 2 is a sectional view of a main part showing a second embodiment.
【図３】第３の実施例を示す要部断面図である。FIG. 3 is a sectional view of a main part showing a third embodiment.
【図４】第１の実施例の製造方法を示す工程断面図であ
る。FIG. 4 is a process cross-sectional view showing the manufacturing method of the first example.
【図５】従来の配線部分を示す断面図である。FIG. 5 is a sectional view showing a conventional wiring portion.
２ 下地絶縁膜 ４ 配線 ６ａ 下層絶縁膜 ６ｂ 上層絶縁膜 ８，１０，１２ シールド層 2 Base insulating film 4 Wiring 6a Lower layer insulation film 6b Upper layer insulation film 8, 10, 12 Shield layer
Claims (3)
る少なくとも１つの配線層で隣接する配線間から配線上
にわたって配線とは絶縁されたシールド用導電体層が設
けられている半導体装置。1. A semiconductor device in which at least one wiring layer having wirings arranged close to each other is provided with a shielding conductive layer insulated from the wirings from between adjacent wirings to over the wirings.
る少なくとも１つの配線層で隣接する配線間のみに配線
とは絶縁されたシールド用導電体層が設けられている半
導体装置。2. A semiconductor device in which a shielding conductor layer insulated from the wiring is provided only between adjacent wirings in at least one wiring layer having wirings arranged close to each other.
る少なくとも１つの配線層で各配線の上部から側部にわ
たって配線とは絶縁されたシールド用導電体層が設けら
れている半導体装置。3. A semiconductor device comprising at least one wiring layer having wirings arranged close to each other, and a shielding conductive layer insulated from the wirings extending from the top to the side of each wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17720391A JPH04373151A (en) | 1991-06-21 | 1991-06-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17720391A JPH04373151A (en) | 1991-06-21 | 1991-06-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04373151A true JPH04373151A (en) | 1992-12-25 |
Family
ID=16026980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17720391A Pending JPH04373151A (en) | 1991-06-21 | 1991-06-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04373151A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008021837A (en) * | 2006-07-13 | 2008-01-31 | Nec Electronics Corp | Semiconductor integrated circuit, and manufacturing method thereof |
| TWI779088B (en) * | 2017-09-07 | 2022-10-01 | 日商東京威力科創股份有限公司 | semiconductor device |
-
1991
- 1991-06-21 JP JP17720391A patent/JPH04373151A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008021837A (en) * | 2006-07-13 | 2008-01-31 | Nec Electronics Corp | Semiconductor integrated circuit, and manufacturing method thereof |
| TWI779088B (en) * | 2017-09-07 | 2022-10-01 | 日商東京威力科創股份有限公司 | semiconductor device |
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