JPH0436249U - - Google Patents

Info

Publication number
JPH0436249U
JPH0436249U JP7800390U JP7800390U JPH0436249U JP H0436249 U JPH0436249 U JP H0436249U JP 7800390 U JP7800390 U JP 7800390U JP 7800390 U JP7800390 U JP 7800390U JP H0436249 U JPH0436249 U JP H0436249U
Authority
JP
Japan
Prior art keywords
flatpack
pads
leads
relief
flat pack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7800390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7800390U priority Critical patent/JPH0436249U/ja
Publication of JPH0436249U publication Critical patent/JPH0436249U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す斜視図、第2
図は本考案におけるはんだ付け状態を示す断面図
、第3図は従来例を示す斜視図、第4図は従来例
におけるはんだ付け状態を示す断面図である。 1……リード、1a……リードに設けた逃げ、
2……クリームはんだ、3……プリント基板のパ
ツド、4……フラツトパツクIC。
Fig. 1 is a perspective view showing one embodiment of the present invention;
3 is a perspective view showing a conventional example, and FIG. 4 is a sectional view showing a soldering state in the conventional example. 1...Lead, 1a...Escape provided on the lead,
2...cream solder, 3...printed circuit board pad, 4...flat pack IC.

Claims (1)

【実用新案登録請求の範囲】 (1) リードを有するフラツトパツクICであつ
て、 リードは、プリント基板のパツドにはんだ付け
されるもので、プリント基板のパツドとの間に余
剰はんだを保持する逃げを有するものであること
を特徴とするフラツトパツクIC。 (2) 前記リードは、微細ピツチで複数設けられ
たものであることを特徴とする請求項第(1)項記
載のフラツトパツクIC。 (3) 前記リードの逃げは、逆テーパ形状に形成
したものであることを特徴とする請求項第(1)項
記載のフラツトパツクIC。
[Scope of Claim for Utility Model Registration] (1) A flatpack IC with leads, which are soldered to pads on a printed circuit board, and have a relief between them and the pads to hold excess solder. A flatpack IC characterized by having the following features: (2) The flat pack IC according to claim (1), wherein a plurality of the leads are provided with fine pitches. (3) The flat pack IC according to claim (1), wherein the lead relief is formed in an inverted tapered shape.
JP7800390U 1990-07-23 1990-07-23 Pending JPH0436249U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7800390U JPH0436249U (en) 1990-07-23 1990-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7800390U JPH0436249U (en) 1990-07-23 1990-07-23

Publications (1)

Publication Number Publication Date
JPH0436249U true JPH0436249U (en) 1992-03-26

Family

ID=31620897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7800390U Pending JPH0436249U (en) 1990-07-23 1990-07-23

Country Status (1)

Country Link
JP (1) JPH0436249U (en)

Similar Documents

Publication Publication Date Title
JPS62112179U (en)
JPH0436249U (en)
JPH0418474U (en)
JPS62196376U (en)
JPS62178572U (en)
JPS61157369U (en)
JPH0217854U (en)
JPS6333669U (en)
JPS645476U (en)
JPS60121601U (en) chip parts
JPH0158955U (en)
JPS62196375U (en)
JPS62190376U (en)
JPS62134274U (en)
JPS6146760U (en) LED holder
JPH01104071U (en)
JPS6219776U (en)
JPH0379451U (en)
JPH0459182U (en)
JPS62201941U (en)
JPS642471U (en)
JPH0215719U (en)
JPH0286174U (en)
JPH0167725U (en)
JPS6375068U (en)