JPH04357858A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04357858A JPH04357858A JP3132720A JP13272091A JPH04357858A JP H04357858 A JPH04357858 A JP H04357858A JP 3132720 A JP3132720 A JP 3132720A JP 13272091 A JP13272091 A JP 13272091A JP H04357858 A JPH04357858 A JP H04357858A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- pad
- bonding wire
- coating resin
- periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000011347 resin Substances 0.000 claims abstract description 57
- 229920005989 resin Polymers 0.000 claims abstract description 57
- 239000011248 coating agent Substances 0.000 claims abstract description 41
- 238000000576 coating method Methods 0.000 claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 24
- 239000007788 liquid Substances 0.000 abstract description 5
- 239000007787 solid Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 241000587161 Gomphocarpus Species 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、樹脂モ−ルド型、セラ
ディップ型、フラットパック型等のパッケ−ジを用いて
構成される半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device constructed using a resin mold type, Ceradip type, flat pack type, or other type of package.
【０００２】0002
【従来の技術】一般に、この種の半導体装置は、ＩＣ（
集積回路）、ＬＳＩ（大規模集積回路）などの半導体チ
ップがダイパッドの載置面上にダイボンドされ、半導体
チップのボンディング用パッドが適当なインナリ−ドボ
ンディング技術によりリ−ド部のインナリ−ドに電気的
接続された後、適当なパッケ−ジング技術を用いて封止
されて構成されている。かかるインナリ−ドボンディン
グ技術の一つとして、パッドとインナリ−ドとをワイヤ
で接続するワイヤボンディング技術があり、一般に普及
している。2. Description of the Related Art Generally, this type of semiconductor device is an IC (
Semiconductor chips such as integrated circuits) and LSIs (large-scale integrated circuits) are die-bonded onto the mounting surface of the die pad, and the bonding pads of the semiconductor chips are bonded to the inner leads of the lead portion using an appropriate inner lead bonding technique. After electrical connections are made, they are sealed and constructed using appropriate packaging techniques. As one of such inner lead bonding techniques, there is a wire bonding technique in which a pad and an inner lead are connected with a wire, and this technique is widely used.
【０００３】図３に、このようなワイヤボンディング技
術を用いた従来の半導体装置の一例の内部におけるワイ
ヤにより接続された部分の構造を示す。FIG. 3 shows the structure of a portion connected by wires inside an example of a conventional semiconductor device using such wire bonding technology.
【０００４】図３において、半導体チップ１１０ の表
面には、複数のボンディング用パッド１１１ がその周
囲に沿って配列されている。半導体チップ１１０ は、
ダイパッド１１２ 上にダイボンドされており、その周
りにはリ−ド部１１６ が距離を隔てて配列されている
。対応するパッド１１１ とリ−ド部１１６ のインナ
リ−ド１１６ａとは、ボンディングワイヤ１１５ によ
り夫々接続されている。この結果、リ−ド部１１６ の
図示しないアウタリ−ドに接続（アウタリ−ドボンディ
ング）することにより、当該半導体装置の外部の回路と
半導体チップ１１０ に形成された回路とを、リ−ド部
１１６ 及びボンディングワイヤ１１５ を介して電気
的接続することができる。In FIG. 3, a plurality of bonding pads 111 are arranged on the surface of a semiconductor chip 110 along its periphery. The semiconductor chip 110 is
It is die-bonded onto a die pad 112, and lead portions 116 are arranged around it at a distance. The corresponding pads 111 and inner leads 116a of the lead portions 116 are connected by bonding wires 115, respectively. As a result, by connecting (outer lead bonding) to the outer leads (not shown) of the lead portion 116, a circuit external to the semiconductor device and a circuit formed on the semiconductor chip 110 can be connected to the lead portion 116. An electrical connection can be made via a bonding wire 115 and a bonding wire 115 .
【０００５】[0005]
【発明が解決しようとする課題】一般にこのような半導
体装置においては、小型化及び高集積化の要請が強い。
このため、図３に示したパッド１１１ 及びボンディン
グワイヤ１１５ 等の間隔を狭くすることや、パッケ−
ジ内部の構造の厚みを減ずることが要求される。しかし
ながら、例えば樹脂モ−ルド型のパッケ−ジの場合には
、ボンディングワイヤ１１５の長さが例えば３．５ｍｍ
を越えると樹脂モ−ルドの際にボンディングワイヤ１
１５ が変形して、ショ−ト不良や、リ−ク不良が発生
する原因となる。即ち図３において、Ａ部のようにボン
ディングワイヤ１１５ と半導体チップ１１０ とが接
触したり、Ｂ部のように隣接するボンディングワイヤ１
１５ 同志が接触したり、Ｃ部のようにボンディングワ
イヤ１１５ とインナリ−ド１１６ａとが接触したりす
る事態が起こってしまう。SUMMARY OF THE INVENTION In general, there is a strong demand for such semiconductor devices to be smaller and more highly integrated. Therefore, the spacing between the pads 111 and the bonding wires 115 shown in FIG.
It is required to reduce the thickness of the internal structure. However, in the case of a resin molded package, for example, the length of the bonding wire 115 is, for example, 3.5 mm.
If the bonding wire 1 is exceeded during resin molding,
15 becomes deformed, causing short-circuit defects and leak defects. That is, in FIG. 3, the bonding wire 115 and the semiconductor chip 110 are in contact as shown in section A, or the bonding wire 1 is in contact with the semiconductor chip 110 as shown in section B.
15. A situation may occur where the wires come into contact with each other, or where the bonding wire 115 and the inner lead 116a come into contact as in the C section.
【０００６】このため特願平１−２０９，３０７ 号で
は、図４に示すように、ボンディングワイヤ１１５ の
パッド１１１ との接続部分を含めた半導体チップ１１
０ を表面側から液状又は固形のコ−ティング樹脂１２
１ で覆って熱硬化させた後に、リ−ド部１１６ のア
ウタリ−ド１１６ｂを残してモ−ルド樹脂１２２ によ
り樹脂封止するようにしている。この結果、コ−ティン
グ樹脂１２１ により、半導体装置内部において図３に
示したＡ部、Ｂ部、Ｃ部のような事態が発生するのをあ
る程度防いでいる。For this reason, in Japanese Patent Application No. 1-209,307, as shown in FIG.
0 from the surface side with liquid or solid coating resin 12
1 and heat cured, the outer leads 116b of the lead portions 116 are left and sealed with a mold resin 122. As a result, the coating resin 121 prevents, to some extent, the occurrence of situations such as those shown in portions A, B, and C shown in FIG. 3 inside the semiconductor device.
【０００７】しかしながら、この場合、図４に示したよ
うに、樹脂コ−ティングの際に、１２１ａの如くコ−テ
ィング樹脂１２１ がダイパッド１１２ から流れ落ち
、パッド１１１ との接続部の付近においてボンディン
グワイヤ１１５ が完全にコ−ティングできないことが
ある。更に、流れ落ちたコ−ティング樹脂１２１ａは、
樹脂封止作業等の妨げになり半導体装置の品質低下につ
ながる一方でこのように流れ落ちる分量は不特定であり
予測しがたいため、適度な分量のコ−ティング樹脂１２
１ を用いてパッド１１１ との接続部の付近において
ボンディングワイヤ１１５ を完全にコ−ティングして
前述のショ−ト不良やリ−ク不良を防ぐことは極めて困
難であった。However, in this case, as shown in FIG. 4, during the resin coating, the coating resin 121 flows down from the die pad 112 as shown at 121a, and the bonding wire 115 falls near the connection portion with the pad 111. may not be completely coated. Furthermore, the coating resin 121a that has flowed down is
The amount of coating resin 12 that flows down is unspecified and difficult to predict, while interfering with resin sealing work and causing a decline in the quality of semiconductor devices.
It was extremely difficult to completely coat the bonding wire 115 in the vicinity of the connection portion with the pad 111 using the bonding wire 115 to prevent the aforementioned short-circuit defects and leak defects.
【０００８】本発明は上述した従来の問題点に鑑み成さ
れたものであり、比較的簡単な構成によりショ−ト不良
やリ−ク不良の発生を防ぎつつ製造することができ、小
型化・高集積化に適している半導体装置を提供すること
を課題とする。The present invention has been made in view of the above-mentioned conventional problems, and has a relatively simple structure that allows manufacturing while preventing short-circuit defects and leak defects, and achieves miniaturization and An object of the present invention is to provide a semiconductor device suitable for high integration.
【０００９】[0009]
【課題を解決するための手段】本願第１発明の半導体装
置は上述の課題を達成すべく、表面にボンディング用パ
ッドを有する半導体チップと、該表面よりも一回り大き
な載置面を有しており該載置面に半導体チップがダイボ
ンドされるダイパッドと、半導体チップの周りに距離を
隔てて配置されたリ−ド部と、該リ−ド部のインナリ−
ドとパッドとを電気的接続するボンディングワイヤと、
該ボンディングワイヤの変形を防止すべく少なくともボ
ンディングワイヤのパッドに接続された部分を表面の側
から覆うコ−ティング樹脂と、半導体チップをダイパッ
ド、ボンディングワイヤ、インナリ−ド及びコ−ティン
グ樹脂と共にパッケ−ジする手段とを備えており、半導
体チップの周囲に沿って露出した載置面の部分に該周囲
に沿って伸びる溝を設けたことを特徴とする。[Means for Solving the Problems] In order to achieve the above-mentioned problems, the semiconductor device of the first invention of the present application has a semiconductor chip having a bonding pad on its surface, and a mounting surface that is slightly larger than the surface. A die pad to which a semiconductor chip is die-bonded to the mounting surface, a lead part arranged at a distance around the semiconductor chip, and an inner part of the lead part.
a bonding wire that electrically connects the pad and the pad;
A coating resin is applied to cover at least the portion of the bonding wire connected to the pad from the surface side in order to prevent deformation of the bonding wire, and the semiconductor chip is packaged together with the die pad, bonding wire, inner leads, and coating resin. The device is characterized in that a groove extending along the periphery of the semiconductor chip is provided in a portion of the mounting surface exposed along the periphery of the semiconductor chip.
【００１０】本願第２発明の半導体装置は上述の課題を
達成すべく、表面にボンディング用パッドを有する半導
体チップと、該表面よりも一回り大きな載置面を有して
おり該載置面に半導体チップがダイボンドされるダイパ
ッドと、半導体チップの周りに距離を隔てて配置された
リ−ド部と、該リ−ド部のインナリ−ドとパッドとを電
気的接続するボンディングワイヤと、該ボンディングワ
イヤの変形を防止すべく少なくともボンディングワイヤ
のパッドに接続された部分を表面の側から覆うコ−ティ
ング樹脂と、半導体チップをダイパッド、ボンディング
ワイヤ、インナリ−ド及びコ−ティング樹脂と共にパッ
ケ−ジする手段とを備えており、半導体チップの周囲に
沿って露出した載置面の部分に該周囲に沿って伸びる凸
部を設けたことを特徴とする。In order to achieve the above-mentioned problems, the semiconductor device of the second invention of the present application has a semiconductor chip having a bonding pad on its surface, and a mounting surface that is slightly larger than the surface. A die pad to which a semiconductor chip is die-bonded, a lead part arranged at a distance around the semiconductor chip, a bonding wire that electrically connects the inner lead of the lead part and the pad, and the bonding wire. A coating resin is applied to cover at least the portion of the bonding wire connected to the pad from the surface side to prevent deformation of the wire, and the semiconductor chip is packaged together with the die pad, bonding wire, inner leads, and coating resin. The device is characterized in that a convex portion extending along the periphery of the semiconductor chip is provided on a portion of the mounting surface exposed along the periphery of the semiconductor chip.
【００１１】[0011]
【作用】本願第１発明の半導体装置においては、半導体
チップは、その表面よりも一回り大きなダイパッドの載
置面にダイボンドされる。ボンディングワイヤは、リ−
ド部のインナリ−ドとパッドとを電気的接続する。コ−
ティング樹脂は、ボンディングワイヤの変形を防止すべ
く、少なくともボンディングワイヤのパッドに接続され
た部分を表面の側から覆っている。かかるコ−ティング
樹脂は、その製造工程では、液状又は固形のコ−ティン
グ樹脂を半導体チップ上にコ−ティングして熱硬化、紫
外線硬化等して形成されるので、コ−ティングの際には
重力の作用によりダイパッドから流れ落ちようとする。
ここで、半導体チップの周囲に沿って露出した載置面の
部分に該周囲に沿って伸びる溝が設けられているので、
かかるコ−ティング樹脂はコ−ティングされた際に、こ
の溝のところまで流れてくるとこれに流れを阻止され、
即ちかかる溝を越えてダイパッドから流れ落ち難くなる
。このため、当該半導体装置は、かかるダイパッドに形
成された溝といった比較的簡単な構成により、所定量の
コ−ティング樹脂により確実にパッドとの接続部の付近
においてボンディングワイヤを完全にコ−ティングして
、前述のショ−ト不良やリ−ク不良の発生を有効に防ぐ
ことができる。この結果、当該半導体装置においては、
ショ−ト不良やリ−ク不良を発生させることなく、パッ
ドやボンディングワイヤの間隔を狭めることができ、装
置の小型化・高集積化が可能となる。In the semiconductor device of the first aspect of the present invention, the semiconductor chip is die-bonded to the mounting surface of the die pad, which is slightly larger than the surface of the semiconductor chip. The bonding wire is
The inner lead of the pad portion is electrically connected to the pad. Cor
The bonding resin covers at least the portion of the bonding wire connected to the pad from the surface side in order to prevent deformation of the bonding wire. In the manufacturing process, such a coating resin is formed by coating a semiconductor chip with a liquid or solid coating resin and curing it with heat or ultraviolet light. It tends to flow down from the die pad due to the action of gravity. Here, since a groove extending along the periphery of the semiconductor chip is provided in a portion of the mounting surface exposed along the periphery of the semiconductor chip,
When the coating resin is coated, when it flows to this groove, the flow is blocked by this.
In other words, it becomes difficult for the liquid to flow down from the die pad over the groove. Therefore, the semiconductor device uses a relatively simple structure such as a groove formed in the die pad to ensure that the bonding wire is completely coated in the vicinity of the connection part with the pad with a predetermined amount of coating resin. Therefore, the occurrence of the aforementioned short-circuit defects and leak defects can be effectively prevented. As a result, in the semiconductor device,
The spacing between pads and bonding wires can be narrowed without causing short-circuit defects or leakage defects, making it possible to miniaturize and highly integrate devices.
【００１２】また、本願第２発明の半導体装置において
は、半導体チップの周囲に沿って露出した載置面の部分
に該周囲に沿って伸びる凸部が設けられているので、か
かるコ−ティング樹脂はコ−ティングされた際に、この
凸部のところまで流れてくるとこれに流れを阻止され、
即ちかかる凸部を越えてダイパッドから流れ落ち難くな
る。このため、当該半導体装置は、ダイパッドに形成さ
れた、例えばその載置面に張り付けたポリイミドテ−プ
からなる凸部といった比較的簡単な構成により、所定量
のコ−ティング樹脂により確実にパッドとの接続部の付
近においてボンディングワイヤを完全にコ−ティングし
て、前述のショ−ト不良やリ−ク不良の発生を有効に防
ぐことができる。Further, in the semiconductor device of the second invention of the present application, since the portion of the mounting surface exposed along the periphery of the semiconductor chip is provided with a convex portion extending along the periphery, such coating resin When coated, when it flows to this convex part, the flow is blocked by this,
In other words, it becomes difficult for the resin to flow down from the die pad over the convex portion. For this reason, the semiconductor device has a relatively simple structure, such as a convex portion formed on the die pad, made of polyimide tape attached to the mounting surface, and is reliably attached to the pad using a predetermined amount of coating resin. By completely coating the bonding wire in the vicinity of the connecting portion, it is possible to effectively prevent the aforementioned short-circuit defects and leak defects.
【００１３】次に示す本発明の実施例から、本発明のこ
のような作用がより明らかにされ、更に本発明の他の作
用が明らかにされよう。[0013] From the following examples of the present invention, these effects of the present invention will become clearer, and other effects of the present invention will become clearer.
【００１４】[0014]
【実施例】以下図面を用いて本発明の実施例を詳細に説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described in detail below with reference to the drawings.
【００１５】図１は本願発明の第１実施例である半導体
装置の構造を示す断面図である。FIG. 1 is a sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention.
【００１６】同図において、半導体装置は、半導体チッ
プ１０と、ダイパッド１２と、ボンディングワイヤ１５
と、リ−ド部１６と、コ−ティング樹脂２１と、パッケ
−ジ本体を構成するモ−ルド樹脂２２とを備えている。In the figure, the semiconductor device includes a semiconductor chip 10, a die pad 12, and bonding wires 15.
, a lead portion 16, a coating resin 21, and a mold resin 22 constituting the package body.
【００１７】半導体チップ１０は、ダイパッド１２の載
置面上にダイボンドされている。半導体チップ１０の表
面には、ボンディング用パッド１１がその周囲に沿って
複数配列されており、夫々のパッド１１には、例えば金
線であるボンディングワイヤ１５の一端が、熱圧着ボン
ディング、超音波ボンディング、ネイルヘッドボンディ
ング等により接続されている。ボンディングワイヤ１５
の他端は、リ−ド部１６のインナリ−ド１６ａ に接続
されている。尚、本実施例では、比較的長いとされる３
．５ｍｍ 以上の長さを持つボンディングワイヤ１５を
用いるものとする。The semiconductor chip 10 is die-bonded onto the mounting surface of the die pad 12. A plurality of bonding pads 11 are arranged on the surface of the semiconductor chip 10 along its periphery, and one end of a bonding wire 15 made of, for example, a gold wire is attached to each pad 11 by thermocompression bonding or ultrasonic bonding. , connected by nail head bonding, etc. Bonding wire 15
The other end is connected to the inner lead 16a of the lead portion 16. In addition, in this example, 3
．． A bonding wire 15 having a length of 5 mm or more is used.
【００１８】リ−ド部１６のアウタリ−ド１６ｂ は、
モ−ルド樹脂２２から構成されたパッケ−ジ本体の外部
に突出しており、当該半導体装置を配線基板等に実装す
る際に、適当なアウタリ−ドボンディング技術により所
定の配線に接続される。The outer lead 16b of the lead portion 16 is
It protrudes from the package body made of molded resin 22, and is connected to a predetermined wiring by an appropriate outer bonding technique when the semiconductor device is mounted on a wiring board or the like.
【００１９】コ−ティング樹脂２１は、ボンディングワ
イヤ１５の変形を防止するためのものであり、ボンディ
ングワイヤ１５をパッド１１に接続した後に、かかるボ
ンディングワイヤ１５の接続部分を含めた半導体チップ
１０の表面上に、液状又は固形のコ−ティング樹脂を落
として加熱することで、コ−ティング樹脂を溶融し熱硬
化させて形成したものである。モ−ルド樹脂２２は、こ
のようにしてコ−ティング樹脂２１を形成した後の半導
体チップ１０、ダイパッド１２、ボンディングワイヤ１
５及びリ−ド部１６からなる構造体を、アウタリ−ド１
６ｂ を残して樹脂封止している。このように本実施例
では、モ−ルド樹脂２２からパッケ−ジする手段の一例
が構成されており、樹脂モ−ルド・フラットパック型の
半導体装置が実現されている。The coating resin 21 is for preventing deformation of the bonding wire 15, and after the bonding wire 15 is connected to the pad 11, the surface of the semiconductor chip 10 including the connecting portion of the bonding wire 15 is coated. It is formed by dropping liquid or solid coating resin on top and heating it to melt and thermoset the coating resin. The mold resin 22 includes the semiconductor chip 10, die pad 12, and bonding wire 1 after forming the coating resin 21 in this way.
5 and the lead part 16, the outer lead 1
All but 6b are sealed with resin. In this way, in this embodiment, an example of means for packaging from the mold resin 22 is constructed, and a resin mold flat pack type semiconductor device is realized.
【００２０】ここで、ダイパッド１２は、半導体チップ
１０の表面よりも一回り大きな載置面を有しており、か
かる載置面において半導体チップ１０の周囲に沿って露
出した部分には、該周囲に沿って伸びる溝３０が設けら
れている。この溝により、コ−ティング樹脂２１を形成
すべく樹脂をコ−ティングする際に、かかる樹脂がダイ
パッド１２から流れ落ちるのを有効に防ぐことができ、
このように熱硬化して得られるコ−ティング樹脂２１に
より、確実にパッド１１との接続部の付近におけるボン
ディングワイヤ１５の部分を完全に覆うことができる。
この結果、ボンディングワイヤ１５が３．５ｍｍ 以上
と長いにも拘らず、前述した従来例の如きショ−ト不良
やリ−ク不良の発生を有効に防ぐことができる。Here, the die pad 12 has a mounting surface that is slightly larger than the surface of the semiconductor chip 10, and a portion exposed along the periphery of the semiconductor chip 10 on the mounting surface has a surface that is slightly larger than that of the semiconductor chip 10. A groove 30 is provided extending along. This groove can effectively prevent the resin from flowing down from the die pad 12 when coating the resin to form the coating resin 21.
The coating resin 21 obtained by thermosetting in this manner can reliably completely cover the portion of the bonding wire 15 in the vicinity of the connection portion with the pad 11. As a result, even though the bonding wire 15 is as long as 3.5 mm or more, it is possible to effectively prevent the occurrence of short circuit defects and leak defects as in the conventional example described above.
【００２１】尚、リ−ド部１６とダイパッド１２とは、
一つの金属性リ−ドフレ−ムから形成することができる
ので、リ−ドフレ−ムの段階で、該リ−ドフレ−ムの半
導体チップ１０の周囲に沿って露出することになる部分
にこのような溝３０を形成しておくだけで上述の如き効
果が得られるので極めて有利である。Note that the lead portion 16 and die pad 12 are as follows:
Since the lead frame can be formed from a single metal lead frame, such a structure is applied to the portion of the lead frame that will be exposed along the periphery of the semiconductor chip 10 at the lead frame stage. This is extremely advantageous because the above-mentioned effects can be obtained simply by forming the grooves 30.
【００２２】次に、本願発明の第２実施例について図２
を用いて説明する。尚、図２において図１と同一の構成
要素については同一の参照符号を付しその説明は省略す
る。Next, FIG. 2 shows a second embodiment of the present invention.
Explain using. In FIG. 2, the same components as in FIG. 1 are designated by the same reference numerals, and the explanation thereof will be omitted.
【００２３】図２において、半導体装置は、ダイパッド
４２を備えている。ダイパッド４２は、半導体チップ１
０の表面よりも一回り大きな載置面を有しており、かか
る載置面において半導体チップ１０の周囲に沿って露出
した部分には、該周囲に沿って、凸部の一例を構成する
ポリイミドテ−プ６０が張り付けられている。このポリ
イミドテ−プ６０により、コ−ティング樹脂２１を形成
すべく樹脂をコ−ティングする際に、かかる樹脂がダイ
パッド４２から流れ落ちるのを有効に防ぐことができ、
このように熱硬化して得られるコ−ティング樹脂２１に
より、確実にパッド１１との接続部の付近におけるボン
ディングワイヤ１５の部分を完全に覆うことができる。
この結果、ボンディングワイヤ１５が３．５ｍｍ 以上
と長いにも拘らず、前述した従来例の如きショ−ト不良
やリ−ク不良の発生を有効に防ぐことができる。In FIG. 2, the semiconductor device includes a die pad 42. As shown in FIG. The die pad 42 is the semiconductor chip 1
The semiconductor chip 10 has a mounting surface that is one size larger than the surface of the semiconductor chip 10, and a polyimide film constituting an example of a convex portion is placed along the periphery of the exposed portion of the mounting surface along the periphery of the semiconductor chip 10. A tape 60 is applied. This polyimide tape 60 can effectively prevent the resin from flowing down from the die pad 42 when coating the resin to form the coating resin 21.
The coating resin 21 obtained by thermosetting in this manner can reliably completely cover the portion of the bonding wire 15 in the vicinity of the connection portion with the pad 11. As a result, even though the bonding wire 15 is as long as 3.5 mm or more, it is possible to effectively prevent the occurrence of short circuit defects and leak defects as in the conventional example described above.
【００２４】尚、リ−ド部１６とダイパッド４２とは、
一つの金属性リ−ドフレ−ムから形成することができる
ので、リ−ドフレ−ムの段階で、該リ−ドフレ−ムの半
導体チップ１０の周囲に沿って露出することになる部分
にこのようなポリイミドテ−プ６０を張り付けておくだ
けで上述の如き効果が得られるので極めて有利である。Note that the lead portion 16 and die pad 42 are
Since the lead frame can be formed from a single metal lead frame, such a structure is applied to the portion of the lead frame that will be exposed along the periphery of the semiconductor chip 10 at the lead frame stage. This is extremely advantageous because the above-mentioned effects can be obtained simply by applying the polyimide tape 60.
【００２５】尚、本実施例では、ポリイミドテ−プ６０
から凸部の一例を構成したが、他の材料からなるテ−プ
や他の部材を張り付けても良く、又ダイパッド４２の周
囲に縁を設けるように構成しても良い。In this embodiment, the polyimide tape 60
Although an example of a convex portion is constructed from the die pad 42, tape or other members made of other materials may be attached thereto, or an edge may be provided around the die pad 42.
【００２６】以上の実施例では樹脂モ−ルド・フラット
パック型のパッケ−ジを用いて当該半導体装置を構成し
たが、インナリ−ドボンディングにワイヤボンディング
を用いるタイプのパッケ−ジである、樹脂モ−ルド・デ
ィプ型、中空樹脂モ−ルド型、セラディップ型等のパッ
ケ−ジを用いて半導体装置を構成する場合にも同様にコ
−ティング樹脂が流れ落ちるのを有効に防止することが
でき、ショ−ト不良やリ−ク不良の発生を防ぐことがで
きるのは容易に理解されよう。In the above embodiments, the semiconductor device was constructed using a resin mold flat pack type package. Even when a semiconductor device is constructed using a package such as a cold dip type, hollow resin mold type, or Ceradip type, it is possible to effectively prevent the coating resin from flowing down in the same way. It is easily understood that the occurrence of short circuit defects and leak defects can be prevented.
【００２７】[0027]
【発明の効果】以上詳細に説明したように本願発明によ
れば、半導体チップは、その表面よりも一回り大きなダ
イパッドの載置面にダイボンドされており、コ−ティン
グ樹脂は、ボンディングワイヤの変形を防止すべく、少
なくともボンディングワイヤのパッドに接続された部分
を表面の側から覆っている。ここで、第１発明では、半
導体チップの周囲に沿って露出した載置面の部分に該周
囲に沿って伸びる溝が設けられており、また、第２発明
では、溝の代わりに該周囲に沿って伸びる凸部が設けら
れているので、比較的簡単な構成により、コ−ティング
樹脂により確実にパッドとの接続部の付近においてボン
ディングワイヤを完全にコ−ティングして、ショ−ト不
良やリ−ク不良の発生を有効に防ぐことができる。この
結果、当該半導体装置においては、ショ−ト不良やリ−
ク不良を発生させることなく、パッドやボンディングワ
イヤの間隔を狭めることができ、装置の小型化・高集積
化が可能となる。従って、本発明により、比較的低コス
トで、信頼性が多く小型で集積度の高い半導体装置を実
現することができる。As explained in detail above, according to the present invention, the semiconductor chip is die-bonded to the mounting surface of the die pad, which is slightly larger than the surface of the semiconductor chip, and the coating resin is In order to prevent this, at least the portion of the bonding wire connected to the pad is covered from the surface side. Here, in the first invention, a groove extending along the periphery is provided in a portion of the mounting surface exposed along the periphery of the semiconductor chip, and in the second invention, instead of the groove, a groove is provided in the periphery. Since a protrusion is provided that extends along the bonding wire, a relatively simple structure ensures that the bonding wire is completely coated with the coating resin near the connection area with the pad, thereby preventing short-circuit defects. The occurrence of leak defects can be effectively prevented. As a result, the semiconductor device suffers from short-circuit defects and leakage.
The spacing between pads and bonding wires can be narrowed without causing any bonding defects, and devices can be made smaller and more highly integrated. Therefore, according to the present invention, it is possible to realize a highly reliable, compact, and highly integrated semiconductor device at relatively low cost.
【図１】図１は、本発明の一実施例の構成を示す断面図
である。FIG. 1 is a sectional view showing the configuration of an embodiment of the present invention.
【図２】図２は、本発明の他の実施例の構成を示す断面
図である。FIG. 2 is a sectional view showing the configuration of another embodiment of the present invention.
【図３】図３は、従来の半導体装置の内部構造を示す部
分斜視図である。FIG. 3 is a partial perspective view showing the internal structure of a conventional semiconductor device.
【図４】図４は、図３の半導体装置の構成を示す断面図
である。FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device of FIG. 3;
１０ 半導体チップ １１ ボンディング用パッド １２、４２ ダイパッド １５ ボンディングワイヤ １６ リ−ド部 １６ａ インナリ−ド １６ｂ アウタリ−ド ２１ コ−ティング樹脂 ２２ モ−ルド樹脂 ３０ 溝 ６０ ポリイミドテ−プ 10 Semiconductor chip 11 Bonding pad 12, 42 Die pad 15 Bonding wire 16 Lead part 16a Inner lead 16b Outer lead 21 Coating resin 22 Mold resin 30 groove 60 Polyimide tape
Claims (2)
半導体チップと、該表面よりも一回り大きな載置面を有
しており該載置面に前記半導体チップがダイボンドされ
るダイパッドと、前記半導体チップの周りに距離を隔て
て配置されたリ−ド部と、該リ−ド部のインナリ−ドと
前記パッドとを電気的接続するボンディングワイヤと、
該ボンディングワイヤの変形を防止すべく少なくとも前
記ボンディングワイヤの前記パッドに接続された部分を
前記表面の側から覆うコ−ティング樹脂と、前記半導体
チップを前記ダイパッド、前記ボンディングワイヤ、前
記インナリ−ド及び前記コ−ティング樹脂と共にパッケ
−ジする手段とを備えており、前記半導体チップの周囲
に沿って露出した前記載置面の部分に該周囲に沿って伸
びる溝を設けたことを特徴とする半導体装置。1. A semiconductor chip having a bonding pad on its surface, a die pad having a mounting surface one size larger than the surface and to which the semiconductor chip is die-bonded, a lead part arranged at a distance around the lead part; a bonding wire electrically connecting the inner lead of the lead part and the pad;
A coating resin that covers at least a portion of the bonding wire connected to the pad from the surface side to prevent deformation of the bonding wire, and a coating resin that covers the semiconductor chip with the die pad, the bonding wire, the inner lead, and the bonding wire. a means for packaging together with the coating resin, and a groove extending along the periphery of the semiconductor chip is provided in a portion of the mounting surface exposed along the periphery of the semiconductor chip. Device.
半導体チップと、該表面よりも一回り大きな載置面を有
しており該載置面に前記半導体チップがダイボンドされ
るダイパッドと、前記半導体チップの周りに距離を隔て
て配置されたリ−ド部と、該リ−ド部のインナリ−ドと
前記パッドとを電気的接続するボンディングワイヤと、
該ボンディングワイヤの変形を防止すべく少なくとも前
記ボンディングワイヤの前記パッドに接続された部分を
前記表面の側から覆うコ−ティング樹脂と、前記半導体
チップを前記ダイパッド、前記ボンディングワイヤ、前
記インナリ−ド及び前記コ−ティング樹脂と共にパッケ
−ジする手段とを備えており、前記半導体チップの周囲
に沿って露出した前記載置面の部分に該周囲に沿って伸
びる凸部を設けたことを特徴とする半導体装置。2. A semiconductor chip having a bonding pad on its surface, a die pad having a mounting surface one size larger than the surface and to which the semiconductor chip is die-bonded, a lead part arranged at a distance around the lead part; a bonding wire electrically connecting the inner lead of the lead part and the pad;
A coating resin that covers at least a portion of the bonding wire connected to the pad from the surface side to prevent deformation of the bonding wire, and a coating resin that covers the semiconductor chip with the die pad, the bonding wire, the inner lead, and the bonding wire. means for packaging together with the coating resin, and a convex portion extending along the periphery of the semiconductor chip is provided on a portion of the mounting surface exposed along the periphery of the semiconductor chip. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3132720A JPH04357858A (en) | 1991-06-04 | 1991-06-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3132720A JPH04357858A (en) | 1991-06-04 | 1991-06-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04357858A true JPH04357858A (en) | 1992-12-10 |
Family
ID=15088005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3132720A Pending JPH04357858A (en) | 1991-06-04 | 1991-06-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04357858A (en) |
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| US11444209B2 (en) | 2012-03-20 | 2022-09-13 | Allegro Microsystems, Llc | Magnetic field sensor integrated circuit with an integrated coil enclosed with a semiconductor die by a mold material |
| US10725100B2 (en) | 2013-03-15 | 2020-07-28 | Allegro Microsystems, Llc | Methods and apparatus for magnetic sensor having an externally accessible coil |
| US9411025B2 (en) | 2013-04-26 | 2016-08-09 | Allegro Microsystems, Llc | Integrated circuit package having a split lead frame and a magnet |
| US10921391B2 (en) | 2018-08-06 | 2021-02-16 | Allegro Microsystems, Llc | Magnetic field sensor with spacer |
| US10991644B2 (en) | 2019-08-22 | 2021-04-27 | Allegro Microsystems, Llc | Integrated circuit package having a low profile |
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