JPH04356834A - Synchronizing circuit using crc check - Google Patents
Synchronizing circuit using crc checkInfo
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- JPH04356834A JPH04356834A JP3024075A JP2407591A JPH04356834A JP H04356834 A JPH04356834 A JP H04356834A JP 3024075 A JP3024075 A JP 3024075A JP 2407591 A JP2407591 A JP 2407591A JP H04356834 A JPH04356834 A JP H04356834A
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- crc
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- parallelly
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- 238000001514 detection method Methods 0.000 claims abstract description 39
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 1
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明はディジタル通信装置に
おいて受信信号の同期をとる同期回路、特に受信信号を
並列展開した信号より、ＣＲＣチェックを用いて同期を
とる同期回路に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization circuit that synchronizes received signals in a digital communication device, and more particularly to a synchronization circuit that synchronizes received signals using a CRC check from parallel expanded signals.
【０００２】0002
【従来の技術】従来、この種の装置として、図３に示す
ようなものがあった。この図は信学技報ＳＡＴ８９−４
１（豊島、鑑、龍野秀雄著：ヘッダ誤りによるセル同期
回路構成法の検討）に示されたもので、図において、１
は直並列変換回路、２は分周回路、３〜５はフリップフ
ロップ、６〜８はＣＲＣ演算・比較回路、１０，１４，
１５は一致検出回路、１１，１６，１７は保護回路、１
８はＡＮＤ回路、１２はインヒビット回路、１３はフレ
ームカウンタである。2. Description of the Related Art Conventionally, there has been a device of this type as shown in FIG. This figure is from IEICE Technical Report SAT89-4
1 (written by Toyoshima, Kan, and Hideo Tatsuno: Study of cell synchronization circuit configuration method due to header error), and in the figure, 1
is a serial/parallel conversion circuit, 2 is a frequency divider circuit, 3 to 5 are flip-flops, 6 to 8 are CRC calculation/comparison circuits, 10, 14,
15 is a coincidence detection circuit, 11, 16, 17 are protection circuits, 1
8 is an AND circuit, 12 is an inhibit circuit, and 13 is a frame counter.
【０００３】次に動作について説明する。直並列変換回
路Ｌは、入力した信号をｎ並列展開し、分周回路２は、
入力したクロックをｎ分周する。Ｌ個のフリップフロッ
プ３〜５は、並列展開されたｎ個の信号を遅延させ、総
数｛ｎ×（Ｌ＋１）｝個の並列の信号を生成する。ｎ個
のＣＲＣ演算・比較回路６〜８は、それぞれ｛ｎ×（Ｌ
＋１）｝個に並列展開された信号の中から１ビットづつ
づれた特定のｍ個の信号よりＣＲＣの演算を行いその演
算結果とＣＲＣビットを比較し一致検出を行う。検出信
号はｎ個の一致検出回路１０，１４，１５に別々に加え
られて、フレームカウンタ１３から出力される検出タイ
ミング信号と照合される。Next, the operation will be explained. The serial-to-parallel conversion circuit L expands the input signal into n parallels, and the frequency division circuit 2
Divide the frequency of the input clock by n. The L flip-flops 3 to 5 delay the n signals developed in parallel to generate a total of {n×(L+1)} parallel signals. The n CRC computation/comparison circuits 6 to 8 each have {n×(L
+1)} signals expanded in parallel, a CRC calculation is performed on specific m signals each containing one bit, and a match is detected by comparing the calculation result with the CRC bit. The detection signal is separately applied to n coincidence detection circuits 10, 14, and 15, and compared with the detection timing signal output from the frame counter 13.
【０００４】ＣＲＣ演算・比較回路６〜８からの検出信
号と検出タイミング信号が一致すれば、一致検出回路１
０，１４，１５は同期信号を検出したものと判断して、
ｎ個の保護回路１１，１６，１７は同期確立状態の時は
そのままの状態を維持し、同期確立前状態の時は、連続
して一致検出が例えば６回得られたときに同期が確立さ
れたと判断する。If the detection signals from the CRC calculation/comparison circuits 6 to 8 match the detection timing signals, the match detection circuit 1
0, 14, and 15 are determined to have detected a synchronization signal,
The n protection circuits 11, 16, and 17 maintain the same state when the synchronization is established, and when the synchronization is not established, the synchronization is established when a coincidence is detected six times in a row. I judge that.
【０００５】又上記タイミングが一致しない場合には、
同期信号が全く検出されないか、あるいは正常と異なる
タイミングで同期信号を検出した場合であり、ｎ個の保
護回路１１，１６，１７は同期確立状態で連続して例え
ば７回不一致検出が行われたとき、インヒビット回路１
２にインヒビット信号を出力して、フレームカウンタ１
３に入力するクロックを禁止する。[0005] Also, if the above timings do not match,
This is a case where a synchronization signal is not detected at all, or a synchronization signal is detected at a timing different from normal, and the n protection circuits 11, 16, and 17 detect a discrepancy, for example, seven times in a row while the synchronization is established. When, inhibit circuit 1
Output an inhibit signal to frame counter 1
Disable the clock input to 3.
【０００６】従って、本同期回路は、入力した信号をｎ
並列展開し、その信号に対してｎ個並列にＣＲＣチェッ
クを行い、各ｎ個の一致検出信号に対して保護を掛ける
ことによって同期をとっている。Therefore, this synchronous circuit converts the input signal into n
Synchronization is achieved by expanding the signals in parallel, performing n CRC checks on the signals in parallel, and applying protection to each of the n coincidence detection signals.
【０００７】[0007]
【発明が解決しようとする課題】従来のＣＲＣチェック
を用いた同期回路は上記のように構成されているので、
受信した信号を並列展開し同期を取る場合、同期位置付
近でＣＲＣ用ビットを一部含むビット列による擬似パタ
ーン一致確率が非常に高いため、保護回路出力を用いて
誤同期確率を低減する必要があった。そのため、保護回
路が、並列展開数分だけ必要になり、回路規模が増大す
るという問題点があった。[Problem to be Solved by the Invention] Since the conventional synchronous circuit using the CRC check is configured as described above,
When synchronizing received signals by expanding them in parallel, the probability of false pattern matching due to a bit string that partially includes CRC bits near the synchronization position is very high, so it is necessary to reduce the probability of false synchronization using the protection circuit output. Ta. Therefore, a protection circuit corresponding to the number of parallel expansions is required, resulting in a problem that the circuit scale increases.
【０００８】この発明は上記のような問題点を解決する
ためになされたもので、入力した信号を並列展開し同期
を取る場合にも、保護回路を並列展開数分必要とせず、
回路規模を縮小することのできるＣＲＣチェックを用い
た同期回路を得ることを目的とする。The present invention was made to solve the above-mentioned problems, and even when input signals are expanded in parallel and synchronized, protection circuits for the number of parallel expansions are not required.
The object of the present invention is to obtain a synchronous circuit using a CRC check that can reduce the circuit scale.
【０００９】[0009]
【課題を解決するための手段】この発明に係るＣＲＣチ
ェックを用いた同期は、並列展開された複数個の並列信
号を複数個並列にＣＲＣチェックを行い同期をとる同期
回路において、上記並列信号の個数に応じて複数個並列
配置し、それぞれ複数個の並列信号のＣＲＣ演算を行い
、演算結果とＣＲＣビットを比較し一致検出を行うＣＲ
Ｃ演算・比較回路と、該各ＣＲＣ演算・比較回路から出
力される一致信号に対して予め優先度を設定し、優先度
順に１つの一致検出信号を選択出力する選択回路とを備
えたことを特徴とするＣＲＣチェックを用いて構成した
ものである。[Means for Solving the Problems] Synchronization using a CRC check according to the present invention is performed in a synchronization circuit that synchronizes a plurality of parallel signals expanded in parallel by performing CRC checks on the plurality of parallel signals. Multiple CRs are arranged in parallel depending on the number of CRs, each performs CRC calculations on multiple parallel signals, and a match is detected by comparing the calculation results and CRC bits.
The present invention is equipped with a C calculation/comparison circuit and a selection circuit that sets priorities in advance for the coincidence signals output from each of the CRC calculation/comparison circuits and selects and outputs one coincidence detection signal in order of priority. It is constructed using a characteristic CRC check.
【００１０】0010
【作用】この発明においては、並列展開された信号に対
して、複数個並列に配置されたＣＲＣ演算・比較回路は
、ＣＲＣの演算を行いその演算結果とＣＲＣビットを比
較して一致検出信号を出力し、選択回路は、各上記ＣＲ
Ｃ演算・比較回路が出力する一致検出信号に対して予め
優先度を設定し、同時に２つ以上の上記ＣＲＣ演算・比
較回路から一致検出信号が出力された場合、予め設定さ
れた優先度順に１つの上記一致検出信号を選択出力する
。[Operation] In the present invention, a plurality of CRC calculation/comparison circuits arranged in parallel perform CRC calculations on signals developed in parallel, compare the calculation results with CRC bits, and generate a coincidence detection signal. output, and the selection circuit selects each of the above CRs.
Priorities are set in advance for the coincidence detection signals output by the C calculation/comparison circuits, and if two or more of the above-mentioned CRC calculation/comparison circuits output coincidence detection signals at the same time, 1 The two coincidence detection signals are selected and output.
【００１１】[0011]
【実施例】図１はこの発明の一実施例を示すブロック図
であり、１〜８，１０〜１３は図３に示した従来装置と
同一のものである。図において、１は直並列変換回路、
２は分周回路、３〜５はフリップフロップ、６〜８はＣ
ＲＣ演算・比較回路、９は選択回路、１０は一致検出回
路、１１は保護回路、１２はインヒビット回路、１３は
フレームカウンタである。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which numerals 1 to 8 and 10 to 13 are the same as the conventional device shown in FIG. In the figure, 1 is a serial-to-parallel conversion circuit;
2 is a frequency divider circuit, 3 to 5 are flip-flops, and 6 to 8 are C
RC calculation/comparison circuit, 9 a selection circuit, 10 a coincidence detection circuit, 11 a protection circuit, 12 an inhibit circuit, and 13 a frame counter.
【００１２】次に動作について説明する。直並列変換回
路１は、入力した信号をｎ並列展開し、分周回路２は、
入力したクロックをｎ分周する。Ｌ個のフリップフロッ
プ３〜５は、並列展開されたｎ個の信号を遅延させ、総
数｛ｎ×（Ｌ＋１）｝個の並列の信号を生成する。ｎ個
のＣＲＣ演算・比較回路６〜８は、それぞれ｛ｎ×（Ｌ
＋１）｝個に並列展開された信号の中から１ビットづつ
づれた特定のｍ個の信号よりＣＲＣの演算を行いその演
算結果とＣＲＣビットを比較し一致検出を行う。Next, the operation will be explained. The serial-to-parallel converter circuit 1 expands the input signal into n parallels, and the frequency divider circuit 2
Divide the frequency of the input clock by n. The L flip-flops 3 to 5 delay the n signals developed in parallel to generate a total of {n×(L+1)} parallel signals. The n CRC computation/comparison circuits 6 to 8 each have {n×(L
+1)} signals expanded in parallel, a CRC calculation is performed on specific m signals each containing one bit, and a match is detected by comparing the calculation result with the CRC bit.
【００１３】選択回路９は、ｎ個のＣＲＣ演算・比較回
路６〜８から出力されるｎ個の一致検出信号に予め優先
度を付けておき、同期引き込み動作中は、２個以上の一
致検出信号が同時に検出された時その優先度にしたがっ
て検出信号を１つ選択し、同期確立前状態あるいは、同
期確立状態の時は、同期引き込み動作中に選択したｎ個
のＣＲＣ演算・比較回路６〜８の中の１つのＣＲＣ演算
・比較回路からの一致検出信号のみを出力する。The selection circuit 9 assigns priorities in advance to the n coincidence detection signals outputted from the n CRC calculation/comparison circuits 6 to 8, and during the synchronization pull-in operation, selects two or more coincidence detection signals. When signals are detected at the same time, one detection signal is selected according to its priority, and in the state before synchronization establishment or in the synchronization establishment state, n CRC calculation/comparison circuits 6 to 6 selected during the synchronization pull-in operation are selected. Only the coincidence detection signal from one of the 8 CRC calculation/comparison circuits is output.
【００１４】選択回路９により選択された検出信号は一
致検出回路１０に加えられ、フレームカウンタ１３から
出力される検出タイミング信号と照合される。選択回路
９からの検出信号と検出タイミング信号が一致すれば、
一致検出回路１０は同期信号を検出したものと判断して
、保護回路１１は同期確立状態の時はそのままの状態を
維持し、同期引き込み動作中あるいは、同期確立前状態
の時は、連続して一致検出が例えば６回得られたときに
同期が確立されたと判断する。The detection signal selected by the selection circuit 9 is applied to a coincidence detection circuit 10 and compared with a detection timing signal output from a frame counter 13. If the detection signal from the selection circuit 9 and the detection timing signal match,
The coincidence detection circuit 10 determines that a synchronization signal has been detected, and the protection circuit 11 maintains the same state when synchronization is established, and continuously performs synchronization during synchronization pull-in operation or before synchronization is established. It is determined that synchronization has been established when a match is detected, for example, six times.
【００１５】又上記タイミングが一致しない場合には、
同期信号が全く検出されないか、あるいは正常と異なる
タイミングで同期信号を検出した場合であり、保護回路
１１は同期確立状態で連続して例えば７回不一致検出が
行われたとき、インヒビット回路１２にインヒビット信
号を出力して、フレームカウンタ１３に入力するクロッ
クを禁止する。[0015] Also, if the above timings do not match,
This is the case when the synchronization signal is not detected at all, or when the synchronization signal is detected at a timing different from normal, and the protection circuit 11 sends an inhibit signal to the inhibit circuit 12 when a mismatch is detected seven times in a row in the synchronization established state. A signal is output to inhibit the clock input to the frame counter 13.
【００１６】従って、本同期回路は、入力した信号をｎ
並列展開し、その信号に対してｎ個並列にＣＲＣチェッ
クを行い、各ｎ個の一致検出信号から優先度順に１つの
一致検出信号を選択し保護を掛けることによって同期を
とっている。図２は、選択回路９が、ｎ個のＣＲＣ演算
・比較回路６〜８から出力される一致検出信号を選択し
ている場合の一致検出回路１０、保護回路１１における
動作を示すタイミング図である。Therefore, this synchronous circuit converts the input signal into n
Synchronization is achieved by expanding the signals in parallel, performing CRC checks on n signals in parallel, selecting one coincidence detection signal from each of the n coincidence detection signals in order of priority, and applying protection. FIG. 2 is a timing diagram showing operations in the coincidence detection circuit 10 and the protection circuit 11 when the selection circuit 9 selects coincidence detection signals output from n CRC calculation/comparison circuits 6 to 8. .
【００１７】[0017]
【発明の効果】以上のようにこの発明によれば、複数個
並列に配置されたＣＲＣ演算・比較回路は、ＣＲＣの演
算を行いその演算結果とＣＲＣビットを比較して一致検
出信号を出力し、選択回路は、各上記ＣＲＣ演算・比較
回路が出力する一致検出信号に対して予め優先度を設定
し、同時に２つ以上の上記ＣＲＣ演算・比較回路から一
致検出信号が出力された場合、予め設定された優先度順
に１つの上記一致検出信号を選択出力するので、入力し
た信号を並列展開し同期を取る場合にも、保護回路を並
列展開数分必要とせず、回路規模を縮小することのでき
るＣＲＣチェックを用いた同期回路を得られるという効
果がある。[Effects of the Invention] As described above, according to the present invention, a plurality of CRC calculation/comparison circuits arranged in parallel perform CRC calculations, compare the calculation results with CRC bits, and output a coincidence detection signal. , the selection circuit sets a priority in advance for the coincidence detection signals output from each of the above-mentioned CRC calculation/comparison circuits, and when coincidence detection signals are outputted from two or more of the above-mentioned CRC calculation/comparison circuits at the same time, Since one of the coincidence detection signals is selected and output in the order of the set priority, even when input signals are expanded in parallel and synchronized, protection circuits for the number of parallel expansions are not required, making it possible to reduce the circuit scale. This has the effect that a synchronous circuit using a CRC check can be obtained.
【図１】この発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】上記実施例の特徴的な動作を示すタイミング図
である。FIG. 2 is a timing diagram showing the characteristic operation of the above embodiment.
【図３】従来の装置を示すブロック図である。FIG. 3 is a block diagram showing a conventional device.
１ 直並列変換回路 ２ 分周回路 ３ フリップフロップ ４ フリップフロップ ５ フリップフロップ ６ ＣＲＣ演算・比較回路 ７ ＣＲＣ演算・比較回路 ８ ＣＲＣ演算・比較回路 ９ 選択回路 １０ 一致検出回路 １４ 一致検出回路 １５ 一致検出回路 1 Serial to parallel conversion circuit 2 Frequency divider circuit 3 Flip-flop 4 Flip-flop 5 Flip-flop 6 CRC calculation/comparison circuit 7 CRC calculation/comparison circuit 8 CRC calculation/comparison circuit 9 Selection circuit 10 Coincidence detection circuit 14 Coincidence detection circuit 15 Coincidence detection circuit
Claims (1)
数個並列にＣＲＣチェックを行い同期をとる同期回路に
おいて、上記並列信号の個数に応じて複数個並列配置し
、それぞれ複数個の並列信号のＣＲＣ演算を行い、演算
結果とＣＲＣビットを比較し一致検出を行うＣＲＣ演算
・比較回路と、該各ＣＲＣ演算・比較回路から出力され
る一致信号に対して予め優先度を設定し、優先度順に１
つの一致検出信号を選択出力する選択回路とを備えたこ
とを特徴とするＣＲＣチェックを用いた同期回路。Claim 1: In a synchronizing circuit that synchronizes a plurality of parallel signals developed in parallel by performing CRC checks in parallel, a plurality of parallel signals are arranged in parallel according to the number of parallel signals, and each of the plurality of parallel signals is A CRC calculation/comparison circuit that performs a CRC calculation and compares the calculation result with the CRC bits to detect a match, and a priority is set in advance for the match signal output from each CRC calculation/comparison circuit. 1 in order
A synchronous circuit using a CRC check, comprising: a selection circuit that selectively outputs two coincidence detection signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3024075A JPH04356834A (en) | 1991-01-24 | 1991-01-24 | Synchronizing circuit using crc check |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3024075A JPH04356834A (en) | 1991-01-24 | 1991-01-24 | Synchronizing circuit using crc check |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04356834A true JPH04356834A (en) | 1992-12-10 |
Family
ID=12128305
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3024075A Pending JPH04356834A (en) | 1991-01-24 | 1991-01-24 | Synchronizing circuit using crc check |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04356834A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007195185A (en) * | 2006-01-18 | 2007-08-02 | Samsung Electronics Co Ltd | Apparatus and method for processing bursts in wireless communication system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217737A (en) * | 1988-07-05 | 1990-01-22 | Fujitsu Ltd | N:1 selector with precedence function |
-
1991
- 1991-01-24 JP JP3024075A patent/JPH04356834A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217737A (en) * | 1988-07-05 | 1990-01-22 | Fujitsu Ltd | N:1 selector with precedence function |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007195185A (en) * | 2006-01-18 | 2007-08-02 | Samsung Electronics Co Ltd | Apparatus and method for processing bursts in wireless communication system |
| US7844884B2 (en) | 2006-01-18 | 2010-11-30 | Samsung Electronics Co., Ltd | Apparatus and method for processing bursts in a wireless communication system |
| JP4675913B2 (en) * | 2006-01-18 | 2011-04-27 | 三星電子株式会社 | Burst processing apparatus and method in wireless communication system |
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