JPH04334020A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04334020A JPH04334020A JP10529091A JP10529091A JPH04334020A JP H04334020 A JPH04334020 A JP H04334020A JP 10529091 A JP10529091 A JP 10529091A JP 10529091 A JP10529091 A JP 10529091A JP H04334020 A JPH04334020 A JP H04334020A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- high melting
- point metal
- atmosphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 238000002844 melting Methods 0.000 claims abstract description 26
- 230000008018 melting Effects 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 13
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000012300 argon atmosphere Substances 0.000 claims 2
- 239000012298 atmosphere Substances 0.000 abstract description 9
- 238000001039 wet etching Methods 0.000 abstract description 6
- 239000010936 titanium Substances 0.000 description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 13
- 238000004544 sputter deposition Methods 0.000 description 12
- 229910021341 titanium silicide Inorganic materials 0.000 description 11
- 239000007789 gas Substances 0.000 description 10
- 235000012239 silicon dioxide Nutrition 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 5
- 229910000838 Al alloy Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910009871 Ti5Si3 Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000003746 solid phase reaction Methods 0.000 description 1
- 229910021352 titanium disilicide Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は，半導体装置の電極配線
構造，特に，メタルとシリコンのコンタクト構造の形成
方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode wiring structure for a semiconductor device, and more particularly to a method for forming a contact structure between metal and silicon.
【０００２】ＬＳＩなどの半導体装置の微細化は急速に
進展しつつあり，それに伴って，コンタクト部分の低抵
抗化，即ち，コンタクト抵抗や拡散層の低抵抗化，また
，浅い不純物拡散層の形成，更にまた，セルフアライメ
ント方式の有効な利用などが重要な問題となっており，
そのような問題に対処できる技術が必要とされている。[0002] The miniaturization of semiconductor devices such as LSI is progressing rapidly, and along with this, the resistance of the contact portion, that is, the contact resistance and the resistance of the diffusion layer, is reduced, and the formation of a shallow impurity diffusion layer is required. , Furthermore, the effective use of self-alignment methods has become an important issue.
There is a need for technology that can deal with such problems.
【０００３】0003
【従来の技術】図４は従来例の説明図である。図におい
て，３１はＳｉ基板， ３２はＳｉＯ２膜， ３３はコ
ンタクトホール， ３４はＴｉ膜， ３５はＴｉ５Ｓｉ
３膜， ３６は ＴｉＳｉ２膜である。2. Description of the Related Art FIG. 4 is an explanatory diagram of a conventional example. In the figure, 31 is a Si substrate, 32 is a SiO2 film, 33 is a contact hole, 34 is a Ti film, and 35 is a Ti5Si film.
3 and 36 are TiSi2 films.
【０００４】従来の半導体装置においては，メタルとシ
リコン（Ｓｉ）のコンタクト部分においては， 金属配
線材料， 或いは， 高融点金属がＳｉ基板と直接に接
している場合が多い。In conventional semiconductor devices, in the contact portion between metal and silicon (Si), the metal wiring material or the high melting point metal is often in direct contact with the Si substrate.
【０００５】ところが， 半導体素子の微細化に伴い，
従来よりも浅い不純物拡散層の形成が行われると，
コンタクト抵抗の増加， 接合破壊などが問題となる。However, with the miniaturization of semiconductor devices,
When an impurity diffusion layer is formed shallower than before,
Problems include increased contact resistance and junction breakdown.
【０００６】[0006]
【発明が解決しようとする課題】そこで，セルフアライ
メント方式によるメタルとメタルシリサイドのコンタク
ト構造，特に，チタンシリサイド（ＴｉＳｉ２） とＳ
ｉのコンタクト構造の形成については，図４に示すよう
に，次のようなプロセスが提案されている。[Problem to be solved by the invention] Therefore, a contact structure between metal and metal silicide using a self-alignment method, especially titanium silicide (TiSi2) and S
Regarding the formation of the contact structure of i, as shown in FIG. 4, the following process has been proposed.
【０００７】即ち，図４（ａ）に示すように，二酸化シ
リコン（ＳｉＯ２）膜３２で被覆され， コンタクトホ
ール３３が形成されたＳｉ基板３１上にチタン（Ｔｉ）
膜３４をスパッタにより被覆形成する。That is, as shown in FIG. 4(a), titanium (Ti) is deposited on a Si substrate 31 covered with a silicon dioxide (SiO2) film 32 and in which a contact hole 33 is formed.
A film 34 is formed by sputtering.
【０００８】図４（ｂ）に示すように，ラピッド・サー
マル・アニール（ＲＴＡ） 等のランプ加熱処理により
ＴｉとＳｉの固相反応を利用して， コンタクトホール
３３内のＴｉとＳｉのコンタクト部分にのみ， チタン
リッチなシリサイド（Ｔｉ５Ｓｉ３ ， ＴｉＳｉ）膜
３５を形成する。As shown in FIG. 4(b), the contact portion between Ti and Si in the contact hole 33 is formed by utilizing the solid phase reaction between Ti and Si through lamp heat treatment such as rapid thermal annealing (RTA). A titanium-rich silicide (Ti5Si3, TiSi) film 35 is formed only in this region.
【０００９】次に， 図４（ｃ）に示すように，ＳｉＯ
２膜３２上の未反応のＴｉ膜３４を過酸化水素とアンモ
ニア水により， ウエットエッチングで除去する。再び
， 図４（ｄ）に示すように，ＲＴＡ 等のランプ加熱
処理を行い， チタンリッチなシリサイド膜３５から，
チタンダイシリサイド（ＴｉＳｉ２） 膜３６を形成
する。Next, as shown in FIG. 4(c), SiO
The unreacted Ti film 34 on the second film 32 is removed by wet etching using hydrogen peroxide and aqueous ammonia. Again, as shown in FIG. 4(d), a lamp heat treatment such as RTA is performed to remove the titanium-rich silicide film 35.
A titanium disilicide (TiSi2) film 36 is formed.
【００１０】しかし， Ｔｉ膜３４形成後の熱処理や，
ウエットエッチング処理等， 工程数の増加や， Ｓ
ｉ基板のハンドリングの煩わしさ， プロセス条件の複
雑化等の幾つかの問題点が生じ， このことにより，
生産効率及び半導体装置の信頼性が低下する。However, the heat treatment after forming the Ti film 34,
Increasing the number of processes such as wet etching treatment, etc.
Several problems have arisen, such as the hassle of handling the i-board and the complexity of process conditions.
Production efficiency and reliability of semiconductor devices decrease.
【００１１】本発明は， 上記の問題点に鑑み， 熱処
理やウエットエッチング処理等のない簡単な工程で低抵
抗化を実現する手段を得ることを目的として提供される
ものである。[0011] In view of the above-mentioned problems, the present invention is provided for the purpose of providing a means for realizing low resistance through a simple process that does not require heat treatment, wet etching, or the like.
【００１２】0012
【課題を解決するための手段】図１は本発明の原理説明
図である。図において，１はＳｉ基板，２は絶縁膜，３
はコンタクトホール，４は高融点金属， ５は高融点金
属窒化膜，６は高融点金属シリサイド膜，７は電極配線
膜である。[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 1 is a Si substrate, 2 is an insulating film, and 3 is a Si substrate.
4 is a contact hole, 4 is a high melting point metal, 5 is a high melting point metal nitride film, 6 is a high melting point metal silicide film, and 7 is an electrode wiring film.
【００１３】上記の問題点を解決するためには， Ｔｉ
のような高融点金属をアルゴン（Ａｒ）雰囲気中にてス
パッタさせて， Ｓｉ基板上に堆積させ， 次に， 反
応ガスをＡｒから， 窒素（Ｎ２）に切替え， Ｎ２を
主体とする雰囲気中で， 上層に窒化チタン（ＴｉＮ）
を堆積させて， Ｔｉ／ＴｉＮ 構造を形成し， 次
に， 真空を破ることなく連続的に熱処理して， 選択
的にメタル／Ｓｉのコンタクト部分に高融点金属のシリ
サイドを形成すれば良い。[0013] In order to solve the above problems, Ti
A high-melting point metal such as is deposited on a Si substrate by sputtering in an argon (Ar) atmosphere, and then the reaction gas is switched from Ar to nitrogen (N2) and deposited in an atmosphere mainly composed of N2. , Titanium nitride (TiN) on the upper layer
is deposited to form a Ti/TiN structure, and then heat-treated continuously without breaking the vacuum to selectively form refractory metal silicide at the metal/Si contact area.
【００１４】即ち，本発明の目的は，図１（ａ）に示す
ような，コンタクトホール３を有する絶縁膜２が表面に
形成されたシリコン基板１と電極金属膜とのコンタクト
をとる半導体装置の製造法において，図１（ｂ）に示す
ように，Ａｒ雰囲気中で， 少なくとも該Ｓｉ基板１上
に高融点金属膜４を堆積する工程と，次に， 図１（ｃ
）に示すように，該Ａｒ雰囲気をＮ２雰囲気に切替え，
該Ｎ２雰囲気気中で該高融点金属膜４上に高融点金属
窒化膜５を積層する工程と，続いて， 図１（ｄ）に示
すように，真空を破ることなく， 該Ｓｉ基板１を熱処
理し， 選択的に該コンタクトホール３内の該Ｓｉ基板
１と高融点金属窒化膜５のコンタクト部分に高融点金属
シリサイド膜６を形成する工程と，しかる後に， 図１
（ｅ）に示すように，該高融点金属シリサイド膜６上に
電極配線膜７を形成する工程とを含むことにより達成さ
れる。That is, an object of the present invention is to provide a semiconductor device as shown in FIG. 1(a) in which a silicon substrate 1 on which an insulating film 2 having a contact hole 3 is formed makes contact with an electrode metal film. The manufacturing method includes a step of depositing a high melting point metal film 4 on at least the Si substrate 1 in an Ar atmosphere, as shown in FIG.
), the Ar atmosphere was switched to N2 atmosphere,
A process of laminating a high melting point metal nitride film 5 on the high melting point metal film 4 in the N2 atmosphere, and then, as shown in FIG. 1(d), the Si substrate 1 is laminated without breaking the vacuum. A heat treatment step is performed to selectively form a high melting point metal silicide film 6 on the contact portion between the Si substrate 1 and the high melting point metal nitride film 5 in the contact hole 3, and then, as shown in FIG.
As shown in (e), this is achieved by including the step of forming an electrode wiring film 7 on the high melting point metal silicide film 6.
【００１５】[0015]
【作用】本発明による工程によって，Ｔｉ膜上に形成さ
れた ＴｉＮ膜は， スパッタガスとしてＮ２ガスのみ
を使用し， プロセス中の圧力を比較的高くし， Ｓｉ
基板の加熱を行わずに形成しているために， ＴｉＮ
膜中に過飽和のＮ２が多く含まれている。[Operation] The TiN film formed on the Ti film by the process according to the present invention uses only N2 gas as the sputtering gas and relatively high pressure during the process.
Because it is formed without heating the substrate, TiN
The film contains a large amount of supersaturated N2.
【００１６】従って， その後の熱処理で， Ｔｉと基
板Ｓｉの直接接している部分で起こるシリサイド反応は
， 上層にあるＮ２リッチな ＴｉＮ膜中に含まれる過
飽和のＮ２が， 下層のＴｉ膜中に拡散するので， 基
板中のＳｉを過度に消失することなく， コンタクト部
分に選択的に ＴｉＳｉ２を形成することができる。[0016] Therefore, during the subsequent heat treatment, the silicide reaction that occurs in the area where Ti and the substrate Si are in direct contact is caused by the supersaturated N2 contained in the upper N2-rich TiN film diffusing into the lower Ti film. Therefore, TiSi2 can be selectively formed in the contact area without excessive loss of Si in the substrate.
【００１７】本発明によれば， 上述の従来例の工程で
示した ＴｉＳｉ２とＳｉのコンタクト構造の形成時に
生ずる問題をクリアでき， 熱処理やウエットエッチン
グ処理等のプロセスを省略することができる。According to the present invention, it is possible to overcome the problems that occur during the formation of the TiSi2 and Si contact structure shown in the conventional process described above, and processes such as heat treatment and wet etching can be omitted.
【００１８】[0018]
【実施例】図２は本発明の一実施例の工程順模式断面図
，図３は本発明の実施例に用いた装置の模式構造図であ
る。Embodiment FIG. 2 is a schematic cross-sectional view of the steps of an embodiment of the present invention, and FIG. 3 is a schematic structural diagram of an apparatus used in the embodiment of the present invention.
【００１９】図において，８はＳｉ基板，９はＳｉＯ２
膜，１０はコンタクトホール，１１はＴｉ膜， １２は
ＴｉＮ膜， １３は ＴｉＳｉ２膜， １４はＡｌ合
金膜， １５はチャンバ， １６はランプヒータ， １
７はＴｉターゲット， １８はＡｒガス導入口， １９
はＮ２ガス導入口， ２０はＤＣ電源， ２１は排気口
， ２２は基板搬出入用チャンバ， ２３はロードロッ
ク， ２４はハンドラー室， ２５はロボットハンドラ
ー， ２６はチャンバＡ， ２７はチャンバＢ ２８
はチャンバＣ， ２９はチャンバＤ，３０はチャンバＥ
である。In the figure, 8 is a Si substrate, 9 is a SiO2
10 is a contact hole, 11 is a Ti film, 12 is a TiN film, 13 is a TiSi2 film, 14 is an Al alloy film, 15 is a chamber, 16 is a lamp heater, 1
7 is a Ti target, 18 is an Ar gas inlet, 19
is a N2 gas inlet, 20 is a DC power supply, 21 is an exhaust port, 22 is a chamber for loading and unloading substrates, 23 is a load lock, 24 is a handler room, 25 is a robot handler, 26 is a chamber A, 27 is a chamber B 28
is chamber C, 29 is chamber D, and 30 is chamber E.
It is.
【００２０】図２は本発明をＡｌ合金膜の電極配線層と
Ｓｉ基板とのコンタクト部にバリアメタルとして，低抵
抗の ＴｉＳｉ２膜を用いた例である。本発明のプロセ
スは，図３（ａ）に示す装置を使用した。FIG. 2 shows an example of the present invention in which a low-resistance TiSi2 film is used as a barrier metal in the contact portion between the electrode wiring layer of the Al alloy film and the Si substrate. The process of the present invention used the apparatus shown in FIG. 3(a).
【００２１】図２（ａ）に示すように，コンタクト領域
にコンタクト用の高濃度拡散を行ったＳｉ基板８上に１
μｍの厚さにＳｉＯ２膜９を形成する。このＳｉＯ２膜
９を，図示しないレジスト膜をマスクとしてドライエッ
チングによりパターニングして，コンタクトホール１０
を形成する。As shown in FIG. 2(a), a silicon substrate 8 is formed on a Si substrate 8 in which high concentration diffusion for contacting is performed in the contact region.
A SiO2 film 9 is formed to a thickness of μm. This SiO2 film 9 is patterned by dry etching using a resist film (not shown) as a mask to form contact holes 10.
form.
【００２２】このＳｉ基板８のコンタクトホール１０内
の自然酸化膜を希弗酸系の水溶液でウエットエッチング
して除去した後， Ｓｉ基板８を図３（ａ）に示す装置
にセットする。After removing the natural oxide film in the contact hole 10 of the Si substrate 8 by wet etching with a dilute hydrofluoric acid-based aqueous solution, the Si substrate 8 is set in the apparatus shown in FIG. 3(a).
【００２３】図２（ｂ）に示すように，Ｓｉ基板８上に
Ｔｉ膜１１をスパッタにより ５００Åの厚さに被覆す
る。Ｔｉ膜１１のスパッタ条件はＤＣ出力が ５００Ｗ
，Ａｒガス流量３０ｓｃｃｍ，チャンバ内ガス圧力２．
０ｍＴｏｒｒで行った。As shown in FIG. 2(b), a Ti film 11 is coated on the Si substrate 8 to a thickness of 500 Å by sputtering. The sputtering conditions for the Ti film 11 are a DC output of 500W.
, Ar gas flow rate 30 sccm, chamber gas pressure 2.
The test was conducted at 0 mTorr.
【００２４】次に，図２（ｃ）に示すように，反応ガス
をＡｒからＮ２に切替え， Ｎ２を主体とする雰囲気に
て， Ｓｉ基板８上に ＴｉＮ膜１２を １，０００Å
の厚さに堆積して， Ｔｉ／ＴｉＮ 構造を形成する。Next, as shown in FIG. 2(c), the reaction gas was switched from Ar to N2, and a TiN film 12 with a thickness of 1,000 Å was deposited on the Si substrate 8 in an atmosphere mainly composed of N2.
to form a Ti/TiN structure.
【００２５】ＴｉＮ 膜１２のスパッタ条件はＤＣ出力
が ５００Ｗ，Ｎ２ガス流量１５０ｓｃｃｍ， チャ
ンバ内ガス圧力１０ｍＴｏｒｒで行った。次に，図２（
ｄ）に示すように，ＲＴＡ により，７００℃の熱処理
を３０秒行うと， Ｓｉ基板８にコンタクトする部分の
ＴｉＮ膜１２にＳｉ基板８よりＳｉが拡散して，Ｔｉ
Ｓｉ２ 膜１３が形成される。The sputtering conditions for the TiN film 12 were a DC output of 500 W, a N2 gas flow rate of 150 sccm, and a chamber gas pressure of 10 mTorr. Next, Figure 2 (
As shown in d), when heat treatment is performed at 700°C for 30 seconds by RTA, Si diffuses from the Si substrate 8 into the TiN film 12 in the portion that contacts the Si substrate 8, and the Ti
A Si2 film 13 is formed.
【００２６】また，同時にＳｉＯ２膜９上の薄いＴｉ膜
１１にも， 上層の ＴｉＮ膜１２から窒素原子（Ｎ）
が拡散して， 全体が ＴｉＮ膜１２になる。最後に，
図２（ｅ）に示すように別のスパッタ装置を用いて，
Ｓｉ基板８上に銅（Ｃｕ）及びＳｉを各１％含んだア
ルミニウム（Ａｌ）合金膜１４を１μｍの厚さに被覆し
，パタニングして，電極配線層を形成する。At the same time, nitrogen atoms (N) are also deposited on the thin Ti film 11 on the SiO2 film 9 from the upper TiN film 12.
is diffused, and the whole becomes a TiN film 12. lastly,
As shown in Figure 2(e), using another sputtering device,
An aluminum (Al) alloy film 14 containing 1% each of copper (Cu) and Si is coated on the Si substrate 8 to a thickness of 1 μm and patterned to form an electrode wiring layer.
【００２７】以上，Ｔｉ膜のスパッタから， チタンシ
リサイド膜の形成までを同一チャンバ内で行ったが，
他の実施例として， 図３（ｂ）に示すように，配線工
程を真空搬送の連続処理装置で行うもできる。As described above, the steps from sputtering the Ti film to forming the titanium silicide film were performed in the same chamber.
As another embodiment, as shown in FIG. 3(b), the wiring process can be performed using a vacuum conveyance continuous processing apparatus.
【００２８】即ち，図３（ｂ）の装置の基板搬出入用チ
ャンバ２２内にＳｉ基板８をセットし，真空にした後，
ロードロック２３を開いて， Ｓｉ基板８をハンドラー
室２４に搬送する。そして， ロボットハンドラー２５
によりＳｉ基板８を先ずチャンバＡ２６にセットする。That is, after setting the Si substrate 8 in the substrate loading/unloading chamber 22 of the apparatus shown in FIG. 3(b) and evacuating it,
The load lock 23 is opened and the Si substrate 8 is transported to the handler chamber 24. And robot handler 25
First, the Si substrate 8 is set in the chamber A26.
【００２９】ここで， ＡｒスパッタによりＳｉ基板８
のコンタクトホール１０内の自然酸化膜を除去する。そ
の後， 前述の搬送方法により， Ｓｉ基板８をチャン
バＢ２７内にセットし， 図２（ｂ）に示すＴｉ膜１１
のスパッタを行う。Here, the Si substrate 8 is sputtered by Ar sputtering.
The natural oxide film inside the contact hole 10 is removed. Thereafter, the Si substrate 8 is set in the chamber B27 by the above-mentioned transport method, and the Ti film 11 shown in FIG. 2(b) is placed.
Perform sputtering.
【００３０】同様にして， チャンバＣ２８内で Ｔｉ
Ｎ膜１２のスパッタ， チャンバＤ２９内でランプ加熱
による ＴｉＳｉ２膜１３の形成， チャンバＥ３０内
でＡｌ合金膜１４のスパッタを連続的に行う。Similarly, in chamber C28, Ti
Sputtering of the N film 12, formation of the TiSi2 film 13 by lamp heating in the chamber D29, and sputtering of the Al alloy film 14 in the chamber E30 are successively performed.
【００３１】このようにして， 真空を破ることなく，
不活性ガス中で， Ｓｉと配線金属のコンタクト部分
の低抵抗化， ならびに熱的に安定な電極配線構造を形
成することができる。[0031] In this way, without breaking the vacuum,
In an inert gas, it is possible to reduce the resistance of the contact area between Si and wiring metal, and to form a thermally stable electrode wiring structure.
【００３２】[0032]
【発明の効果】以上説明したように， 本発明によれば
， 低抵抗，かつ，熱的に安定で，信頼性の高い金属と
Ｓｉのコンタクト構造を形成することが出来，素子の微
細化，高集積化にも寄与するところが大きい。[Effects of the Invention] As explained above, according to the present invention, it is possible to form a contact structure between metal and Si that is low in resistance, thermally stable, and highly reliable. It also greatly contributes to higher integration.
【図１】 本発明の原理説明図[Figure 1] Diagram explaining the principle of the present invention
【図２】 本発明の一実施例の工程順模式断面図[Fig. 2] Schematic sectional view of the process order of one embodiment of the present invention
【図
３】 本発明の実施例に用いた装置の模式構造図[Figure 3] Schematic structural diagram of the device used in the examples of the present invention
【図
４】 従来例の説明図[Figure 4] Explanatory diagram of conventional example
１ Ｓｉ基板 ２ 絶縁膜 ３ コンタクトホール ４ 高融点金属 ５ 高融点金属窒化膜 ６ 高融点金属シリサイド膜 ７ 電極配線膜 ８ Ｓｉ基板 ９ ＳｉＯ２膜 １０ コンタクトホール １１ Ｔｉ膜 １２ ＴｉＮ膜 １３ ＴｉＳｉ２膜 １４ Ａｌ合金膜 １５ チャンバ １６ ランプヒータ １７ Ｔｉターゲット １８ Ａｒガス導入口 １９ Ｎ２ガス導入口 ２０ ＤＣ電源 ２１ 排気口 ２２ 基板搬出入用チャンバ ２３ ロードロック ２４ ハンドラー室 ２５ ロボットハンドラー ２６ チャンバＡ ２７ チャンバＢ ２８ チャンバＣ ２９ チャンバＤ ３０ チャンバＥである。 1 Si substrate 2 Insulating film 3 Contact hole 4 High melting point metal 5 High melting point metal nitride film 6 High melting point metal silicide film 7 Electrode wiring film 8 Si substrate 9 SiO2 film 10 Contact hole 11 Ti film 12 TiN film 13 TiSi2 film 14 Al alloy film 15 Chamber 16 Lamp heater 17 Ti target 18 Ar gas inlet 19 N2 gas inlet 20 DC power supply 21 Exhaust port 22 Chamber for loading and unloading substrates 23 Load lock 24 Handler room 25 Robot handler 26 Chamber A 27 Chamber B 28 Chamber C 29 Chamber D 30 Chamber E.
Claims (1)
縁膜（２） が表面に形成されたシリコン基板（１）
と電極金属膜とのコンタクトをとる半導体装置の製造法
において，アルゴン雰囲気中で， 少なくとも該シリコ
ン基板（１） 上に高融点金属膜（４） を堆積する工
程と，次に， 該アルゴン雰囲気を窒素雰囲気に切替え
， 該窒素雰囲気中で該高融点金属膜（４） 上に高融
点金属窒化膜（５） を積層する工程と，続いて， 真
空を破ることなく， 該シリコン基板（１） を熱処理
し， 選択的に該コンタクトホール（３） 内の該シリ
コン基板（１） と高融点金属窒化膜（５） のコンタ
クト部分に高融点金属シリサイド膜（６） を形成する
工程と，しかる後に， 該高融点金属シリサイド膜（６
） 上に電極配線膜（７） を形成する工程とを含むこ
とを特徴とする半導体装置の製造方法。[Claim 1] A silicon substrate (1) on which an insulating film (2) having a contact hole (3) is formed.
A method for manufacturing a semiconductor device that makes contact with an electrode metal film includes a step of depositing a high melting point metal film (4) on at least the silicon substrate (1) in an argon atmosphere, and then removing the argon atmosphere. Switching to a nitrogen atmosphere, stacking a high melting point metal nitride film (5) on the high melting point metal film (4) in the nitrogen atmosphere, and then depositing the silicon substrate (1) on the high melting point metal film (4) without breaking the vacuum. a step of heat treatment and selectively forming a high melting point metal silicide film (6) at the contact portion between the silicon substrate (1) and the high melting point metal nitride film (5) in the contact hole (3); The high melting point metal silicide film (6
) Forming an electrode wiring film (7) thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10529091A JPH04334020A (en) | 1991-05-10 | 1991-05-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10529091A JPH04334020A (en) | 1991-05-10 | 1991-05-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04334020A true JPH04334020A (en) | 1992-11-20 |
Family
ID=14403557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10529091A Withdrawn JPH04334020A (en) | 1991-05-10 | 1991-05-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04334020A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09186105A (en) * | 1995-10-28 | 1997-07-15 | Nec Corp | Semiconductor device manufacturing method |
-
1991
- 1991-05-10 JP JP10529091A patent/JPH04334020A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09186105A (en) * | 1995-10-28 | 1997-07-15 | Nec Corp | Semiconductor device manufacturing method |
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