JPH04324632A - Manufacture of insulating film of semiconductor device - Google Patents
Manufacture of insulating film of semiconductor deviceInfo
- Publication number
- JPH04324632A JPH04324632A JP9435291A JP9435291A JPH04324632A JP H04324632 A JPH04324632 A JP H04324632A JP 9435291 A JP9435291 A JP 9435291A JP 9435291 A JP9435291 A JP 9435291A JP H04324632 A JPH04324632 A JP H04324632A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio2
- substrate
- insulating film
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 32
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 32
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 32
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 32
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 32
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 8
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 5
- 239000007789 gas Substances 0.000 claims description 13
- 239000011261 inert gas Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 3
- 230000007547 defect Effects 0.000 description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000007864 aqueous solution Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 102000004190 Enzymes Human genes 0.000 description 1
- 108090000790 Enzymes Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013068 control sample Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】この発明は、半導体装置の絶縁膜
の製造方法に関する。より詳しくは半導体基板上におけ
るゲート絶縁膜、キャパシター絶縁膜の製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an insulating film for a semiconductor device. More specifically, the present invention relates to a method of manufacturing a gate insulating film and a capacitor insulating film on a semiconductor substrate.
【０００２】0002
【従来の技術と課題】半導体装置において、薄いゲート
絶縁膜として、従来からＳｉ基板を熱酸化することによ
って形成されるＳｉＯ２ の熱酸化膜が広く用いられて
いる。これはＳｉＯ２ 膜／Ｓｉ基板の界面特性が安定
なことと、この絶縁膜が絶縁破壊耐圧が高く（９〜１０
ＭＶ／ｃｍ）かつ高電界（約７ＭＶ／ｃｍ）での電流リ
ークが低いことから半導体装置に利用した場合に長時間
の信頼性が高いなど、他の絶縁膜にない優れた特定をも
っているからである。2. Description of the Related Art In semiconductor devices, a thermal oxide film of SiO2, which is formed by thermally oxidizing a Si substrate, has been widely used as a thin gate insulating film. This is because the interface characteristics of the SiO2 film/Si substrate are stable, and this insulating film has a high dielectric breakdown voltage (9 to 10
MV/cm) and high electric field (approximately 7 MV/cm), so it has excellent long-term reliability when used in semiconductor devices, and has excellent properties that other insulating films do not have. be.
【０００３】ところが、集積回路素子の微細化がますま
す要望されているために、ＳｉＯ２ 膜の薄膜化が進み
、特に６４Ｍ以上のＤＲＡＭでは厚みが１０ｍｍ以下の
薄いＳｉＯ２ 膜が要求されている。そのためトンネル
成分が直接現れてくる７０Å以下の厚みの場合にはその
リーク電流が大きくなるという問題が発生し、前記のよ
うな長期の信頼性を得ることが困難である。その上に、
素子の微細化にもかかわらず、集積回路の容量が大きく
なってきている。そのためチップ面積が増大するととも
にゲート領域の総面積が増大するので、ピンホールなど
によるＳｉＯ２ 膜の欠陥密度を低減する要求がますま
す高まっている。特にデバイス機構の中には、ゲート面
積がチップ面積の３０％以上にも及ぶ占有率をもってい
るものがあり、歩留り向上のためにもＳｉＯ２ 膜の欠
陥密度を大幅に低下させる必要が生じている。However, as integrated circuit elements are increasingly required to be miniaturized, SiO2 films are becoming thinner, and in particular, DRAMs of 64M or more are required to have a thin SiO2 film with a thickness of 10 mm or less. Therefore, in the case of a thickness of 70 Å or less where the tunnel component directly appears, a problem arises in that the leakage current becomes large, making it difficult to obtain the above-mentioned long-term reliability. in addition,
Despite miniaturization of devices, the capacity of integrated circuits is increasing. Therefore, as the chip area increases, the total area of the gate region also increases, so there is an increasing demand for reducing the defect density of the SiO2 film due to pinholes and the like. In particular, some device mechanisms have a gate area that accounts for 30% or more of the chip area, making it necessary to significantly reduce the defect density of the SiO2 film in order to improve yield.
【０００４】ゲートＳｉＯ２ 膜の絶縁破壊耐圧特性に
ついては、山部ら（ＶＬＳＩ Ｒｅｓｅａｒｃｈ Ｃｅ
ｎｔｅｒ， Ｔｏｓｈｉｂａ Ｃｏｒｐｏｒａｔｉｏｎ
） 、” Ｐｒｏｃｅｅｄｉｎｇｓ ｏｆ ｔｈｅｓ
ｉｘｔｈ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｓｙｍｐｏｓ
ｉｕｍ ｏｎ Ｓｉｌｉｃｏｎ Ｍａｔｅｒｉａｌｓ
Ｓｃｉｅｎｃｅ ａｎｄ Ｔｅｃｈｎｏｌｏｇｙ ”
ｐ３４９（１９９０）において分類がなされている。す
なわち、電界強度が １）０〜１ＭＶ／ｃｍ、２）１
〜８ＭＶ／ｃｍおよび ３）８ＭＶ／ｃｍ以上のそれ
ぞれの場合に絶縁破壊をおこすモードをそれぞれＡ，Ｂ
およびＣのモード不良と呼んでいる。Ａモード不良は、
Ｓｉ基板のダスト、汚染などが原因で起こるゲートＳｉ
Ｏ２膜のピンホールによるものであり、Ｂモード不良は
、Ｓｉ基板表面のＳｉ結晶の結晶欠陥が原因で生ずるゲ
ートＳｉＯ２ 膜の欠陥や微小ＳｉＯ２結晶などの電気
的ウィークスポットなどによるものであり、Ｃモード不
良はＳｉＯ２固有の絶縁破壊耐圧特性によるものである
。Regarding the breakdown voltage characteristics of the gate SiO2 film, Yamabe et al.
Toshiba Corporation
), “Proceedings of these
ixth International Sympos
ium on Silicon Materials
Science and Technology”
Classification is made in p.349 (1990). That is, the electric field strength is 1) 0 to 1 MV/cm, 2) 1
~8MV/cm and 3) Modes that cause dielectric breakdown in each case of 8MV/cm or more are A and B, respectively.
and C mode failure. A mode failure is
Gate Si caused by dust, contamination, etc. on the Si substrate
B-mode defects are caused by pinholes in the O2 film, and B-mode defects are caused by defects in the gate SiO2 film caused by crystal defects in the Si crystal on the Si substrate surface and electrical weak spots such as minute SiO2 crystals. The mode failure is due to the dielectric breakdown voltage characteristics inherent to SiO2.
【０００５】これらのモード不良のうちＡモード不良は
、ゲートＳｉＯ２ 膜形成前のＳｉ基板表面の清浄度に
大きく依存しているので、この不良を克服するには、ま
ずＳｉ基板の清浄法を検討する必要がある。しかし洗浄
方法を改善しても防止できないピンホールがゲートＳｉ
Ｏ２ 膜に発生することがある。したがってこのような
ピンホールの欠陥を解消するには、洗浄方法以外の方法
が必要である。[0005] Among these mode failures, the A-mode failure is highly dependent on the cleanliness of the Si substrate surface before forming the gate SiO2 film, so in order to overcome this failure, it is first necessary to consider a cleaning method for the Si substrate. There is a need to. However, pinholes that cannot be prevented even with improved cleaning methods occur on the gate Si.
It may occur in the O2 film. Therefore, methods other than cleaning methods are required to eliminate such pinhole defects.
【０００６】[0006]
【課題を解決するための手段】この発明は、上記の特に
Ａモード不良を解消する方法として、Ｓｉ基板上に熱酸
化法でＳｉＯ２ の熱酸化膜を形成し、前記熱酸化膜の
上にＣＶＤ法でＳｉＯ２ 膜を積層し、酸素ガスを含む
雰囲気下で熱処理することからなる、半導体装置の絶縁
膜の製造方法を提供するものである。この発明による絶
縁膜は、Ｓｉ基板に形成されたＳｉＯ２ の熱酸化膜に
おけるピンホールが生じていても、その上にＣＶＤ法で
形成されたＳｉＯ２ 膜が補償し、さらにＳｉ基板に対
する酸素欠損が酸素雰囲気下での熱処理により補償され
ているため、ゲート電極やキャパシター電極の基板に対
する優れた絶縁膜となる。[Means for Solving the Problems] The present invention is a method for solving the above-mentioned A-mode defects, in which a thermal oxide film of SiO2 is formed on a Si substrate by a thermal oxidation method, and then a CVD film is deposited on the thermal oxide film. The present invention provides a method for manufacturing an insulating film for a semiconductor device, which comprises stacking SiO2 films by a method and heat-treating them in an atmosphere containing oxygen gas. In the insulating film according to the present invention, even if pinholes occur in the SiO2 thermal oxide film formed on the Si substrate, the SiO2 film formed thereon by the CVD method compensates for them, and furthermore, oxygen vacancies in the Si substrate are Since it is compensated by heat treatment in an atmosphere, it becomes an excellent insulating film for the substrate of gate electrodes and capacitor electrodes.
【０００７】この発明の方法によるＳｉ基板上における
絶縁膜は次のようにして形成される。Ｓｉ基板としては
、Ｓｉの単結晶からなる基板が用いられる。Ｓｉ基板は
、表面にＦｅなどの重金属や微小欠陥を有することがあ
るので、通常希フッ化水素酸水溶液（例えば約１％ＨＦ
水溶液）で洗浄し、１０００℃以上の高温下で一旦熱酸
化膜を形成し、この熱酸化膜を希フッ化水素酸水溶液で
除去して使用するのが望ましい。An insulating film on a Si substrate according to the method of the present invention is formed as follows. As the Si substrate, a substrate made of single crystal Si is used. Si substrates may have heavy metals such as Fe or micro defects on their surfaces, so they are usually treated with a dilute hydrofluoric acid aqueous solution (for example, about 1% HF).
It is desirable to use the substrate by cleaning with aqueous solution), forming a thermal oxide film once at a high temperature of 1000° C. or higher, and removing this thermal oxide film with a dilute hydrofluoric acid aqueous solution.
【０００８】このように予め洗浄したＳｉ基板上に、Ｓ
ｉＯ２ の熱酸化膜が形成される。この熱酸化膜の形成
は、それ自体公知の方法で行うことができる。例えば、
Ｓｉ基板をＨＣｌ／Ｏ２ 雰囲気下で約９００℃に保持
することによって熱酸化膜を形成することができる。熱
酸化膜の膜厚は、約１００Åが好ましい。[0008] On the Si substrate that has been cleaned in advance in this way, S
A thermal oxide film of iO2 is formed. This thermal oxide film can be formed by a method known per se. for example,
A thermal oxide film can be formed by maintaining the Si substrate at about 900° C. in an HCl/O2 atmosphere. The thickness of the thermal oxide film is preferably about 100 Å.
【０００９】次に、熱酸化膜（ＳｉＯ２ ）上に、ＣＶ
Ｄ法によってＳｉＯ２ 膜が積層される。ＣＶＤ法の条
件は、高温で（例えば８００℃〜９００℃、好ましくは
８２０℃〜８６０℃）、減圧（１０−４Ｔｏｒｒ以下）
下が好ましい。蒸発材料としては、ケイ素化合物（例え
ばＳｉＨ４ ）が用いられる。雰囲気ガスとしては、Ｏ
２ ，Ｎ２Ｏなどが用いられる。このＣＶＤ法によって
形成するＳｉＯ２ 膜の膜厚は、約３０〜８０Å、好ま
しくは４０〜６０Åである。このＳｉＯ２ 膜は、いわ
ゆる高温酸化膜〔ＨＴＯ（Ｈｉｇｈ Ｔｅｍｐｅｒａｔ
ｕｒｅ Ｏｘｉｄｅ）膜〕で、上記工程で形成されたＳ
ｉＯ２ 熱酸化膜中にピンホールが存在しても、それを
充分に埋め込みピンホールの補償をすることになる。Next, on the thermal oxide film (SiO2), CV
SiO2 films are laminated by method D. The conditions for the CVD method are high temperature (e.g. 800°C to 900°C, preferably 820°C to 860°C) and reduced pressure (10-4 Torr or less).
Lower is preferred. A silicon compound (for example, SiH4) is used as the evaporation material. As the atmospheric gas, O
2, N2O, etc. are used. The thickness of the SiO2 film formed by this CVD method is about 30 to 80 Å, preferably 40 to 60 Å. This SiO2 film is a so-called high temperature oxide film (HTO).
ure Oxide film] formed in the above process.
Even if a pinhole exists in the iO2 thermal oxide film, it will be sufficiently buried to compensate for the pinhole.
【００１０】この発明の方法では、上記工程で得られた
基板を、酵素ガス雰囲気下で熱処理に付される。酸素ガ
ス雰囲気下は、少なくともＯ２ ガスを５０％以上が存
在するのが好ましい。より好ましくは、Ｏ２ ガスのみ
である。Ｏ２ ガス以外に不活性ガス（例えばＮ２ ガ
ス、Ａｒガス）やＯ３ ガスが存在してもよい。熱処理
は、約９００〜１０００℃で、約０．５〜１時間が好ま
しい。なお、Ｏ３ ガスが存在する場合は、熱処理を１
００℃〜２００℃のような低温にすることができる。In the method of the present invention, the substrate obtained in the above step is subjected to heat treatment in an enzyme gas atmosphere. In the oxygen gas atmosphere, it is preferable that at least 50% of O2 gas is present. More preferably, only O2 gas is used. In addition to O2 gas, an inert gas (for example, N2 gas, Ar gas) or O3 gas may be present. The heat treatment is preferably performed at about 900 to 1000°C for about 0.5 to 1 hour. Note that if O3 gas is present, the heat treatment is
The temperature can be as low as 00°C to 200°C.
【００１１】この熱処理工程では、ＨＴＯ膜中に酸素欠
損が存在する際にそれを補い、またＳｉＯ２ ／Ｓｉ界
面における未結合のＳｉ（多くは３価のＳｉ）にＯ２
を結合させて界面準位密度を低下されるのに役立つと考
えられる。[0011] This heat treatment process compensates for oxygen vacancies that exist in the HTO film, and also adds O2 to unbonded Si (mostly trivalent Si) at the SiO2/Si interface.
This is thought to be useful in lowering the interface state density by combining the two.
【００１２】この発明の方法では、場合により更に不活
性ガス（例えばＮ２ガス、Ａｒガス）の雰囲気下で高温
の約９００〜１０００℃で約３０分〜１時間の熱処理を
行ってもよい。この熱処理により、ＨＴＯ膜／ＳｉＯ２
膜間のトラップ準位の一層の低下を行うことができる
。
なおこの処理は、上記のＯ２ ガス雰囲気下の熱処理の
際に、不活性ガスが存在すれば特に必要とされない。[0012] In the method of the present invention, if necessary, heat treatment may be further performed at a high temperature of about 900 to 1000°C for about 30 minutes to 1 hour in an atmosphere of inert gas (eg, N2 gas, Ar gas). Through this heat treatment, HTO film/SiO2
The trap level between the films can be further lowered. Note that this treatment is not particularly required if an inert gas is present during the heat treatment in the O2 gas atmosphere.
【００１３】かくして、Ｓｉ基板上に形成された絶縁膜
上には、その上に必要な各素子を常法に従って形成され
るが、この発明の絶縁膜は長期に安定した絶縁性を提供
することになる。[0013]Thus, each necessary element is formed on the insulating film formed on the Si substrate according to a conventional method, and the insulating film of the present invention provides stable insulation over a long period of time. become.
【００１４】[0014]
【実施例】次に実施例によってこの発明を説明するがこ
の発明を限定するものではない。まずＰ（１００）Ｓｉ
基板を約１％の希フッ化水素水溶液で洗浄後、１０５０
℃で１〜２時間処理してＳｉＯ２ 酸化膜を形成し、上
記希フッ化水素水溶液で除去した。次に塩化水素／酸素
雰囲気下、９００℃の温度にて約１００Åの厚みでＳｉ
Ｏ２ の熱酸化膜をＳｉ基板上に形成させた。この熱酸
化膜の上に、ＳｉＨ４ ＋Ｎ２Ｏを用い８５０℃、２０
０ｍＴｏｒｒでのＣＶＤ法にてＳｉＯ２ 膜を約５０Å
の厚みで形成させた。次に実質的に酸素ガスのみからな
る雰囲気下約９００℃で３０〜６０分間熱処理させた。
最後に電気炉を用いて窒素ガス雰囲気中９００〜１００
０℃で３０〜６０分間熱処理した。EXAMPLES Next, the present invention will be explained by examples, but the present invention is not limited to the following examples. First, P(100)Si
After cleaning the substrate with an approximately 1% dilute hydrogen fluoride aqueous solution,
℃ for 1 to 2 hours to form a SiO2 oxide film, which was removed with the dilute hydrogen fluoride aqueous solution. Next, under a hydrogen chloride/oxygen atmosphere at a temperature of 900°C, Si was deposited to a thickness of approximately 100 Å.
A thermal oxide film of O2 was formed on a Si substrate. On top of this thermal oxide film, SiH4 +N2O was used to heat the film at 850°C for 20 minutes.
A SiO2 film of approximately 50 Å was formed using the CVD method at 0 mTorr.
It was formed with a thickness of . Next, heat treatment was performed at about 900° C. for 30 to 60 minutes in an atmosphere consisting essentially of oxygen gas. Finally, using an electric furnace in a nitrogen gas atmosphere,
Heat treatment was performed at 0°C for 30 to 60 minutes.
【００１５】上記のように処理して得られたＳｉ基板（
ａ）と、Ｓｉ基板を上記のように熱酸化してＳｉＯ２
の熱酸化膜を形成し、ＣＶＤ法によるＳｉＯ２ 膜の積
層と酸素ガス雰囲気下での熱処理を行わずに、最後の熱
処理を行っただけのＳｉ基板（ｂ）の両者を用いてＭＯ
Ｓバラクターを作製し、次のようにして破壊耐圧特性を
比較した。[0015] The Si substrate (
a) and SiO2 by thermally oxidizing the Si substrate as described above.
A thermal oxide film was formed, and the Si substrate (b) was subjected to the final heat treatment without stacking the SiO2 film by the CVD method and heat treatment in an oxygen gas atmosphere.
S varactors were produced and their breakdown voltage characteristics were compared in the following manner.
【００１６】リンをドープしたポリシリコンをパターン
形成して試料のゲートＳｉＯ２ 膜上の電極とし、電極
面積Ｓを４ｍｍ２ とし、８ＭＶ／ｃｍ以上の電界強度
で破壊するに至る前記Ｃモード不良のＭＯＳバラクター
を良品とし、１つのＳｉウエーハ上の約１００ヶのＭＯ
Ｓバラクターを母数として、これに対する上記良品バラ
クターの数の比率すなわち良品比をＰとしたときの欠陥
密度ρを計算した。ｐは、欠陥がアトランダムに存在す
る領域に発生し、その領域に発生した欠陥が複数個あっ
ても１個の欠陥と仮定するいわゆるポアソンの式ρ＝１
ｎＰ／Ｓを用いて算出した。その結果は以下の表のとお
りである。[0016] Polysilicon doped with phosphorus was patterned to form an electrode on the gate SiO2 film of the sample, and the electrode area S was set to 4 mm2. about 100 MOs on one Si wafer.
Using the S varactor as a parameter, the defect density ρ was calculated, where P is the ratio of the number of non-defective varactors to this, that is, the non-defective ratio. p is the so-called Poisson's formula ρ = 1, which assumes that defects occur in a region where they exist randomly, and that even if there are multiple defects in that region, they are one defect.
Calculated using nP/S. The results are shown in the table below.
【００１７】[0017]
【表１】
上記の結果からこの発明の方法による試料（ａ）は、対
照試料（ｂ）に比べてＡモード不良が著しく少なく、欠
陥密度が小さくなっている。また界面準位密度θｓｓ／
ｑも〜１０−１０／ｃｍ２ となっており、ゲート絶縁
膜としても良好な値となっている。[Table 1] From the above results, the sample (a) prepared by the method of the present invention has significantly fewer A-mode defects and has a lower defect density than the control sample (b). Also, the interface state density θss/
q is also ~10-10/cm2, which is a good value for a gate insulating film.
【００１８】[0018]
【発明の効果】この発明を用いれば、大面積ゲート絶縁
膜の欠陥密度を大幅に低減させることが可能となり、大
容量ＭＯＳメモリーに用いた場合良品数が著しく向上す
ることが期待できる。[Effects of the Invention] By using the present invention, it is possible to significantly reduce the defect density of a large-area gate insulating film, and it is expected that the number of non-defective products will be significantly increased when used in a large-capacity MOS memory.
【図１】この発明の方法の効果を示す説明図である。FIG. 1 is an explanatory diagram showing the effects of the method of the present invention.
１ Ｓｉ基板 ２ ＳｉＯ２ の熱酸化膜 ３ ピンホール ４ ＣＶＤ法によるＳｉＯ２ 膜 1 Si substrate 2 SiO2 thermal oxide film 3 Pinhole 4 SiO2 film by CVD method
Claims (3)
化膜を形成し、前記熱酸化膜の上にＣＶＤ法でＳｉＯ２
膜を積層し、酸素ガスを含む雰囲気下で熱処理するこ
とを特徴とする半導体装置の絶縁膜の製造方法。1. A thermally oxidized film of SiO2 is formed on a Si substrate by a thermal oxidation method, and an SiO2 film is formed on the thermally oxidized film by a CVD method.
A method for manufacturing an insulating film for a semiconductor device, which comprises stacking films and heat-treating the films in an atmosphere containing oxygen gas.
燥ガスを用い、約８００℃以上の高温下で行われる請求
項１記載の製造方法。2. The manufacturing method according to claim 1, wherein the heat treatment in an atmosphere containing oxygen gas is performed at a high temperature of about 800° C. or higher using a dry gas.
た後、さらに不活性ガスの雰囲気下で高温短時間の熱処
理に付される請求項１〜２項の何れかに記載の製造方法
。3. The manufacturing method according to claim 1, wherein after the heat treatment in an atmosphere containing oxygen gas, the product is further subjected to high temperature and short time heat treatment in an inert gas atmosphere. .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9435291A JPH04324632A (en) | 1991-04-24 | 1991-04-24 | Manufacture of insulating film of semiconductor device |
| KR1019920006770A KR100312996B1 (en) | 1991-04-24 | 1992-04-22 | Insulation film manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9435291A JPH04324632A (en) | 1991-04-24 | 1991-04-24 | Manufacture of insulating film of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04324632A true JPH04324632A (en) | 1992-11-13 |
Family
ID=14107893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9435291A Pending JPH04324632A (en) | 1991-04-24 | 1991-04-24 | Manufacture of insulating film of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH04324632A (en) |
| KR (1) | KR100312996B1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06318588A (en) * | 1993-03-11 | 1994-11-15 | Nec Corp | Manufacture of semiconductor device |
| JPH07106543A (en) * | 1993-10-07 | 1995-04-21 | Nec Corp | Manufacture of solid-state image sensing device |
| US6847079B2 (en) | 1999-09-13 | 2005-01-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a stacked gate insulation film and a gate electrode and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910001880B1 (en) * | 1988-02-26 | 1991-03-28 | 금성일렉트론 주식회사 | Method manufacturing oxide thin film by 2 stage oxide processing |
-
1991
- 1991-04-24 JP JP9435291A patent/JPH04324632A/en active Pending
-
1992
- 1992-04-22 KR KR1019920006770A patent/KR100312996B1/en not_active IP Right Cessation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06318588A (en) * | 1993-03-11 | 1994-11-15 | Nec Corp | Manufacture of semiconductor device |
| JPH07106543A (en) * | 1993-10-07 | 1995-04-21 | Nec Corp | Manufacture of solid-state image sensing device |
| US6847079B2 (en) | 1999-09-13 | 2005-01-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a stacked gate insulation film and a gate electrode and manufacturing method thereof |
| US7180131B2 (en) | 1999-09-13 | 2007-02-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a stacked gate insulation film and a gate electrode and manufacturing method thereof |
| US7229882B2 (en) | 1999-09-13 | 2007-06-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a field effect semiconductor device having a stacked gate insulation film and a gate electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100312996B1 (en) | 2003-08-06 |
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