JPH04315446A - Semiconductor wafer and semiconductor integrated device using same - Google Patents
Semiconductor wafer and semiconductor integrated device using sameInfo
- Publication number
- JPH04315446A JPH04315446A JP8210691A JP8210691A JPH04315446A JP H04315446 A JPH04315446 A JP H04315446A JP 8210691 A JP8210691 A JP 8210691A JP 8210691 A JP8210691 A JP 8210691A JP H04315446 A JPH04315446 A JP H04315446A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- solder
- semiconductor wafer
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000005520 cutting process Methods 0.000 claims description 29
- 229910000679 solder Inorganic materials 0.000 claims description 29
- 238000007789 sealing Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000000926 separation method Methods 0.000 abstract description 2
- 238000001465 metallisation Methods 0.000 description 28
- 235000012431 wafers Nutrition 0.000 description 13
- 229920000168 Microcrystalline cellulose Polymers 0.000 description 6
- 208000017763 cutaneous neuroendocrine carcinoma Diseases 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 235000019813 microcrystalline cellulose Nutrition 0.000 description 6
- 238000005538 encapsulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010953 base metal Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は裏面メタライズを有する
半導体ウェハの切断に伴って生じる導電性異物の発生を
防止する技術、特に、ハーメチック型のＭＣＣ（マイク
ロ・チップ・キャリア）に用いる半導体チップに適用し
て効果のある技術に関するものである。[Industrial Application Field] The present invention relates to a technology for preventing the generation of conductive foreign matter that occurs when cutting semiconductor wafers having backside metallization, and in particular to semiconductor chips used in hermetic type MCCs (microchip carriers). It concerns techniques that can be applied and are effective.
【０００２】0002
【従来の技術】ハーメチック型ＭＣＣ実装による半導体
集積回路装置の１つにはんだバンプを用いたものがある
。2. Description of the Related Art One type of semiconductor integrated circuit device using hermetic MCC mounting uses solder bumps.
【０００３】図５は従来のハーメチック型ＭＣＣ方式の
半導体集積回路装置の一例を示す断面図である。FIG. 5 is a sectional view showing an example of a conventional hermetic MCC type semiconductor integrated circuit device.
【０００４】この半導体集積回路装置は、上面に裏面メ
タライズ２が形成されると共に、下面に多数の球状のは
んだバンプ（ＣＣＢ）３が一定間隔に設けられた半導体
チップ１と、この半導体チップ１を気密封止するために
平板状の封止基板４（外部及びはんだバンプ３に接続す
るための配線パターンが設けられている）と、“コ”の
形の断面形状を有して封止基板４の周縁及び半導体チッ
プ１の裏面メタライズ２に接続可能なキャップ５とから
構成され、キャップ５と半導体チップ１の裏面メタライ
ズ２及び封止基板４の周縁の間は、背面はんだ６及び封
止はんだ７（はんだ材としては、Ｐｂ／Ｓｎ、Ａｕ／Ｓ
ｎなど）によって接合され、気密封止及び半導体チップ
１の放熱が図られている。This semiconductor integrated circuit device includes a semiconductor chip 1 having a backside metallization 2 formed on its upper surface and a number of spherical solder bumps (CCBs) 3 provided at regular intervals on its lower surface; A flat sealing substrate 4 (provided with a wiring pattern for connecting to the outside and the solder bumps 3) for airtight sealing, and a sealing substrate 4 having a "U"-shaped cross section. and a cap 5 that can be connected to the periphery of the semiconductor chip 1 and the back metallization 2 of the semiconductor chip 1, and between the cap 5 and the periphery of the back metallization 2 of the semiconductor chip 1 and the sealing substrate 4, there is a back solder 6 and a sealing solder 7. (Solder materials include Pb/Sn, Au/S
n, etc.) for airtight sealing and heat dissipation of the semiconductor chip 1.
【０００５】ところで、半導体チップは、１枚の半導体
ウェハに碁盤の目状に同時に多数個が作成され、この半
導体ウェハの裏面には裏面メタライズが全面に形成され
ている。半導体素子及び回路の形成が完了した半導体ウ
ェハは、切断刃によって１つづつのチップに切断分離さ
れ、その１つが半導体チップ１として用いられる。By the way, a large number of semiconductor chips are simultaneously fabricated in a grid pattern on one semiconductor wafer, and a backside metallization is formed on the entire backside of this semiconductor wafer. The semiconductor wafer on which semiconductor elements and circuits have been formed is cut into individual chips by a cutting blade, and one of the chips is used as the semiconductor chip 1.
【０００６】なお、この種の技術に関しては、例えば、
特開昭５５−４８９３６号公報に記載がある。[0006] Regarding this type of technology, for example,
There is a description in JP-A-55-48936.
【０００７】[0007]
【発明が解決しようとする課題】本発明者の検討によれ
ば、切断処理の際、切断刃による半導体基板（シリコン
）の切断は綺麗に行えるのに対し、裏面メタライズの切
断は基板表面からめくれ上がるため、切断というよりは
引き裂かれるように分離され、そのばり状の切断屑がチ
ップ側に残されたままになり、これが半導体集積回路装
置の完成後にショックなどを原因として封止基板上に落
下し、はんだバンプ間を短絡させるという問題がある。[Problem to be Solved by the Invention] According to the study by the present inventor, during the cutting process, the semiconductor substrate (silicon) can be cut cleanly by the cutting blade, but the back side metallization is cut from the surface of the substrate. As the chip rises, it separates as if it were torn rather than cut, and the burr-like cutting debris remains on the chip side, which falls onto the encapsulation substrate due to shock after the semiconductor integrated circuit device is completed. However, there is a problem in that the solder bumps are short-circuited.
【０００８】また、従来においては、裏面メタライズは
背面はんだの下地金属としての利用のみに限られており
、他の利用は考えられていなかった。[0008]Furthermore, conventionally, the use of backside metallization has been limited to only as a base metal for backside solder, and no other uses have been considered.
【０００９】そこで、本発明の目的は、チップ切断分割
時の裏面メタライズの分離不良に起因する導電性異物の
発生を無くし、半導体集積回路装置の信頼性を向上させ
ることのできる技術を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a technique that can eliminate the generation of conductive foreign matter due to poor separation of backside metallization during chip cutting and division, and can improve the reliability of semiconductor integrated circuit devices. It is in.
【００１０】本発明の前記ならびに他の目的と新規な特
徴は、本明細書の記述及び添付図面から明らかになるで
あろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.
【００１２】すなわち、ハーメチック型マイクロ・チッ
プ・キャリア方式の半導体集積回路装置に用いられる半
導体ウェハであって、その放熱面に設けられている金属
膜を、半導体チップの分割のための切断線の両側の所定
幅内には設けないようにしている。That is, in a semiconductor wafer used in a hermetic microchip carrier type semiconductor integrated circuit device, a metal film provided on the heat dissipation surface is placed on both sides of the cutting line for dividing the semiconductor chips. They are not provided within a predetermined width of.
【００１３】[0013]
【作用】上記した手段によれば、切断刃による切断線上
の両側の刃に接触する可能性の有る部位には金属膜を設
けないことより、金属膜は切断の対象とはならない。し
たがって、切断屑による導電性異物は発生せず、ハーメ
チック型ＭＣＣに用いても、パッケージ封入後のはんだ
バンプ間の短絡を招くことがない。[Operation] According to the above-mentioned means, since the metal film is not provided in the area where there is a possibility of contact with the blades on both sides of the cutting line by the cutting blade, the metal film is not cut. Therefore, conductive foreign matter due to cutting debris is not generated, and even when used in a hermetic type MCC, short circuits between solder bumps after encapsulation in a package will not occur.
【００１４】[0014]
【実施例１】図１は本発明による半導体ウェハを示す裏
面図である。また、図２は切断分割した１つの半導体チ
ップを示す正面図である。Embodiment 1 FIG. 1 is a back view of a semiconductor wafer according to the present invention. Further, FIG. 2 is a front view showing one semiconductor chip that has been cut and divided.
【００１５】半導体ウェハ８の表面には、多数の半導体
チップが縦横に形成され、その各々に対応して半導体ウ
ェハ８の裏面には裏面メタライズ９（金属膜）が形成さ
れている。切断線１０は、半導体チップの形成領域の境
界に沿って設けられており、この切断線１０の両側には
所定幅に対しては裏面メタライズ９を設けていない。A large number of semiconductor chips are formed vertically and horizontally on the front surface of the semiconductor wafer 8, and back metallization 9 (metal film) is formed on the back surface of the semiconductor wafer 8 corresponding to each chip. The cutting line 10 is provided along the boundary of the semiconductor chip formation area, and the back metallization 9 is not provided on both sides of the cutting line 10 for a predetermined width.
【００１６】この裏面メタライズ９を設けない幅寸法は
、切断刃（ブレード）の刃幅（例えば３０μｍ）より例
えば２０μｍ程度広くし、全幅を５０μｍにする。The width without the back metallization 9 is, for example, about 20 μm wider than the width of the cutting blade (for example, 30 μm), and the total width is 50 μm.
【００１７】裏面メタライズ９には、例えば、Ａｕ／Ｃ
ｒ／Ｃｕ／Ａｕを順次成膜し、或いはＮｉ／Ａｕ積層膜
が用いられる。切断線幅は、上記各金属を順次蒸着によ
り成膜した後、これに対して周知のホトエッチング技術
により形成する。或いは、リフトオフ法による形成も可
能であり、この方法によれば工程を簡単にすることが可
能になる。The back metallization 9 includes, for example, Au/C.
r/Cu/Au films are sequentially formed, or a Ni/Au laminated film is used. The width of the cutting line is determined by sequentially depositing each of the metals mentioned above and then applying a well-known photoetching technique to the film. Alternatively, formation by a lift-off method is also possible, and this method makes it possible to simplify the process.
【００１８】以上のように構成された半導体ウェハ８を
切断するに際しては、切断線幅を５０μｍした場合、刃
幅が３０μｍの切断刃を用い、これを切断線１０に沿っ
て切断刃を移動させる。すると、切断によって除去され
る部分が切断線１０を中心にして、その左右１５μｍで
あり、裏面メタライズ９には切断刃が及ばない。切断分
離された半導体チップ１１の各々は図２に示す如くであ
り、裏面メタライズ９は端縁はシリコンの外周縁から後
退しており、切断刃には接触していない。したがって、
裏面メタライズ９には異物（ばり）が生ぜず、従来のよ
うに、はんだバンプ間を短絡させる如き事故は生じるこ
とがない。When cutting the semiconductor wafer 8 configured as described above, if the cutting line width is 50 μm, a cutting blade with a blade width of 30 μm is used and the cutting blade is moved along the cutting line 10. . Then, the portion removed by cutting is 15 μm on either side of the cutting line 10, and the cutting blade does not reach the back metallization 9. Each of the cut and separated semiconductor chips 11 is as shown in FIG. 2, and the edge of the back metallization 9 is set back from the outer peripheral edge of the silicon and does not contact the cutting blade. therefore,
No foreign matter (burr) is generated on the back metallization 9, and accidents such as short circuit between solder bumps do not occur as in the conventional case.
【００１９】[0019]
【実施例２】図３は本発明による半導体集積回路装置の
一実施例を示す断面図である。なお、本実施例において
は、図５に示したと同一であるものには同一引用数字を
用いたので、以下においては重複する説明を省略する。Embodiment 2 FIG. 3 is a sectional view showing an embodiment of a semiconductor integrated circuit device according to the present invention. Note that in this embodiment, the same reference numerals are used for the same parts as shown in FIG. 5, and therefore, redundant explanation will be omitted below.
【００２０】本実施例では図２に示した半導体チップ１
１が用いられ、はんだバンプ１２が図５の場合と同様に
下面に規則的に配設されている。封止基板４に半導体チ
ップ１１をＣＣＢ接合した後、背面はんだ６及び封止は
んだ７を介在させてキャップ５を裏面メタライズ９及び
封止基板４に位置決めし、このままリフロー炉に通すこ
とにより、裏面メタライズ９、封止はんだ７及びはんだ
バンプ１２の接続部の各々が溶融して接合が行われる。In this embodiment, the semiconductor chip 1 shown in FIG.
1 is used, and solder bumps 12 are regularly arranged on the lower surface as in the case of FIG. After CCB bonding the semiconductor chip 11 to the sealing substrate 4, the cap 5 is positioned on the back metallization 9 and the sealing substrate 4 with the back solder 6 and the sealing solder 7 interposed, and the back surface is bonded by passing it through a reflow oven. The connection portions of the metallization 9, the sealing solder 7, and the solder bumps 12 are each melted and bonded.
【００２１】裏面メタライズ９は、上記説明から明らか
なように、半導体チップ１１の上面外周部には裏面メタ
ライズ９が設けられておらず、切断の対象にされていな
いので、ばりなどの異物が生じることが無く、半導体集
積回路装置の完成後にはんだバンプ１２間の短絡などを
生じる恐れはない。As is clear from the above description, the back metallization 9 is not provided on the outer periphery of the upper surface of the semiconductor chip 11 and is not cut, so foreign substances such as burrs are generated. Therefore, there is no risk of short-circuiting between the solder bumps 12 after the semiconductor integrated circuit device is completed.
【００２２】[0022]
【実施例３】図４は本発明による半導体集積回路装置の
他の実施例を示す断面図である。なお、本実施例におい
ては、図３に示したと同一であるものには同一引用数字
を用いたので、以下においては重複する説明を省略する
。Embodiment 3 FIG. 4 is a sectional view showing another embodiment of the semiconductor integrated circuit device according to the present invention. Note that in this embodiment, the same reference numerals are used for the same parts as shown in FIG. 3, and therefore, redundant explanation will be omitted below.
【００２３】本実施例は、裏面メタライズを複数に分割
絶縁し、その裏面メタライズ１３，１４，１５の各々を
電源または信号の配線パターンとして用いるようにした
ものである。裏面メタライズ１３，１４，１５は半導体
チップ１１の基板、或いは配線パターンを介してはんだ
バンプ１２のいずれかに接続されている。裏面メタライ
ズ１３，１４，１５を電源用にした場合、各々を異なる
電圧値の電源ラインとして用いることも、同一電圧値で
ありながら複数のブロックに分けた用い方も可能である
。また、信号用と電源用とに分けて用いることもできる
。なお、背面はんだは、裏面メタライズ１３，１４，１
５の各々に対応して背面はんだ１６ａ，１６ｂ，１６ｃ
に分割して設けられている。In this embodiment, the back metallization is divided and insulated into a plurality of parts, and each of the back metallization 13, 14, and 15 is used as a wiring pattern for a power supply or a signal. The back metallization 13, 14, and 15 are connected to either the substrate of the semiconductor chip 11 or the solder bumps 12 via a wiring pattern. When the back metallization 13, 14, and 15 are used for power supply, it is possible to use each as a power supply line with a different voltage value, or to divide it into a plurality of blocks even though they have the same voltage value. Further, it can be used separately for signals and power supply. Note that the backside solder is backside metallized 13, 14, 1.
Back side solder 16a, 16b, 16c corresponding to each of 5.
It is divided into .
【００２４】裏面メタライズ１３，１４，１５を電源に
用いた場合、半導体チップ１１内の素子への電源供給を
最寄りの裏面メタライズ１３，１４，１５から得られる
ため、半導体チップ１１内の電源用配線パターンを最短
にできると共に、電源用配線パターンの長さを短縮し、
更には配線数の低減が可能になる。このため、従来と同
一サイズの半導体チップ１１を用いた場合、その実装密
度を高めることが可能になる。また、レイアウト設計も
簡便になる。When the back metallization 13 , 14 , 15 is used as a power source, the power supply to the elements inside the semiconductor chip 11 can be obtained from the nearest back metallization 13 , 14 , 15 . The pattern can be made as short as possible, and the length of the power supply wiring pattern can be shortened.
Furthermore, the number of wiring lines can be reduced. Therefore, when using the semiconductor chip 11 of the same size as the conventional one, it is possible to increase the packaging density. Additionally, layout design becomes easier.
【００２５】さらに、裏面メタライズ１３，１４，１５
への信号の入出力、電源供給は封止基板以外から引き出
す構成も可能である。この場合、キャップ５が絶縁物で
あることから、キャップ５内に配線パターンを形成し、
これをキャップ５外へ電極（またはリード）として引き
出すことにより、信号の入出力或いは電源供給を独自に
行うことができる。Furthermore, back surface metallization 13, 14, 15
A configuration in which signal input/output and power supply are drawn from sources other than the sealing substrate is also possible. In this case, since the cap 5 is an insulator, a wiring pattern is formed inside the cap 5,
By drawing this out of the cap 5 as an electrode (or lead), signal input/output or power supply can be performed independently.
【００２６】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。[0026] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.
【００２７】[0027]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記の通りである。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions are briefly explained as follows.
It is as follows.
【００２８】すなわち、ハーメチック型マイクロ・チッ
プ・キャリア方式の半導体集積回路装置に用いられる半
導体ウェハであって、その放熱面に設けられている金属
膜を、半導体チップの分割のための切断線の両側の所定
幅内には設けないようにしたので、切断屑による導電性
異物は発生せず、ハーメチック型ＭＣＣに用いても、パ
ッケージ封入後のはんだバンプ間の短絡を招くことがな
く、半導体集積回路装置の信頼性を向上させることがで
きる。That is, in a semiconductor wafer used in a hermetic microchip carrier type semiconductor integrated circuit device, a metal film provided on the heat dissipation surface is placed on both sides of the cutting line for dividing the semiconductor chips. Since the solder bumps are not provided within the predetermined width of the solder bumps, conductive foreign matter is not generated due to cutting debris, and even when used in a hermetic type MCC, short circuits between solder bumps after encapsulation in the package are not caused, and the semiconductor integrated circuit The reliability of the device can be improved.
【図１】本発明による半導体ウェハを示す裏面図である
。FIG. 1 is a back view of a semiconductor wafer according to the present invention.
【図２】図１の半導体ウェハを切断分割した１つの半導
体チップを示す正面図である。FIG. 2 is a front view showing one semiconductor chip obtained by cutting and dividing the semiconductor wafer in FIG. 1;
【図３】本発明による半導体集積回路装置の一実施例を
示す断面図である。FIG. 3 is a cross-sectional view showing an embodiment of a semiconductor integrated circuit device according to the present invention.
【図４】本発明による半導体集積回路装置の他の実施例
を示す断面図である。FIG. 4 is a sectional view showing another embodiment of the semiconductor integrated circuit device according to the present invention.
【図５】従来のハーメチック型ＭＣＣ方式の半導体集積
回路装置の一例を示す断面図である。FIG. 5 is a cross-sectional view showing an example of a conventional hermetic MCC type semiconductor integrated circuit device.
１ 半導体チップ ２ 裏面メタライズ ３ はんだバンプ（ＣＣＢ） ４ 封止基板 ５ キャップ ６ 背面はんだ ７ 封止はんだ ８ 半導体ウェハ ９ 裏面メタライズ（金属膜） １０ 切断線 １１ 半導体チップ １２ はんだバンプ １３，１４，１５ 裏面メタライズ 1 Semiconductor chip 2 Back side metallization 3 Solder bump (CCB) 4 Sealing substrate 5 Cap 6 Back side solder 7 Sealing solder 8 Semiconductor wafer 9 Back side metallization (metal film) 10 Cutting line 11 Semiconductor chip 12 Solder bump 13, 14, 15 Back side metallization
Claims (3)
ャリア方式の半導体集積回路装置に用いられる半導体ウ
ェハであって、その放熱面に設けられている金属膜を、
半導体チップの分割のための切断線の両側の所定幅内に
は設けないことを特徴とする半導体ウェハ。Claim 1: A semiconductor wafer used in a hermetic microchip carrier type semiconductor integrated circuit device, wherein a metal film provided on a heat dissipation surface of the semiconductor wafer is
A semiconductor wafer characterized in that no cutting line is provided within a predetermined width on both sides of a cutting line for dividing semiconductor chips.
、この封止基板への搭載面にはんだバンプが設けられた
請求項１記載の半導体チップと、この半導体チップの金
属膜に内面が背面はんだによって接合されると共に、前
記半導体チップを覆うようにして周端縁が前記封止基板
上に封止はんだによって接合されるキャップとを具備す
ることを特徴とする半導体集積回路装置。2. A semiconductor chip according to claim 1, comprising: a sealing substrate on which a wiring pattern is formed; solder bumps are provided on a surface to be mounted on the sealing substrate; 1. A semiconductor integrated circuit device comprising: a cap that is bonded by solder and whose peripheral edge is bonded to the sealing substrate by sealing solder so as to cover the semiconductor chip.
れた複数のブロックに分割され、各々が前記半導体チッ
プの電源もしくは信号回路に接続され、或いは前記キャ
ップを通して外部に接続されることを特徴とする請求項
２記載の半導体集積回路装置。3. The metal film is divided into a plurality of electrically isolated blocks, each of which is connected to a power source or a signal circuit of the semiconductor chip, or connected to the outside through the cap. 3. The semiconductor integrated circuit device according to claim 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8210691A JPH04315446A (en) | 1991-04-15 | 1991-04-15 | Semiconductor wafer and semiconductor integrated device using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8210691A JPH04315446A (en) | 1991-04-15 | 1991-04-15 | Semiconductor wafer and semiconductor integrated device using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04315446A true JPH04315446A (en) | 1992-11-06 |
Family
ID=13765158
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8210691A Pending JPH04315446A (en) | 1991-04-15 | 1991-04-15 | Semiconductor wafer and semiconductor integrated device using same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04315446A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5531017A (en) * | 1994-02-14 | 1996-07-02 | International Business Machines Corporation | Thin film magnetic head fabrication method |
| JP2006339354A (en) * | 2005-06-01 | 2006-12-14 | Tdk Corp | Semiconductor ic and its manufacturing method, module with built-in semiconductor ic and its manufacturing method |
| WO2008132559A1 (en) * | 2007-04-27 | 2008-11-06 | Freescale Semiconductor, Inc. | Semiconductor wafer processing |
-
1991
- 1991-04-15 JP JP8210691A patent/JPH04315446A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5531017A (en) * | 1994-02-14 | 1996-07-02 | International Business Machines Corporation | Thin film magnetic head fabrication method |
| JP2006339354A (en) * | 2005-06-01 | 2006-12-14 | Tdk Corp | Semiconductor ic and its manufacturing method, module with built-in semiconductor ic and its manufacturing method |
| EP1729341A3 (en) * | 2005-06-01 | 2014-03-26 | TDK Corporation | Semiconductor IC and its manufacturing method, and module with embedded semiconductor IC and its manufacturing method |
| WO2008132559A1 (en) * | 2007-04-27 | 2008-11-06 | Freescale Semiconductor, Inc. | Semiconductor wafer processing |
| US8456023B2 (en) | 2007-04-27 | 2013-06-04 | Freescale Semiconductor, Inc. | Semiconductor wafer processing |
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