JPH0430755B2 - - Google Patents
Info
- Publication number
- JPH0430755B2 JPH0430755B2 JP15038684A JP15038684A JPH0430755B2 JP H0430755 B2 JPH0430755 B2 JP H0430755B2 JP 15038684 A JP15038684 A JP 15038684A JP 15038684 A JP15038684 A JP 15038684A JP H0430755 B2 JPH0430755 B2 JP H0430755B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- region
- charge injection
- gate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- 230000015556 catabolic process Effects 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims 2
- 239000012212 insulator Substances 0.000 claims 1
- 238000002513 implantation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000014759 maintenance of location Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000002784 hot electron Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、浮遊ゲート型半導体不揮発性メモリ
に関する。さらに詳細には、電荷注入領域、絶縁
膜、制御ゲート、絶縁膜、浮遊ゲート、絶縁膜の
層構造、すなわち半導体（Ｓ）−絶縁膜（Ｉ）−金
属（Ｍ）−絶縁膜（Ｉ）−金属（Ｍ）−絶縁膜（Ｉ）
構造（以下この構造をSIMIMIと略す）を用いる
ことにより、5V以下の低電圧書き込みを実現し、
飛躍的に保持特性及び繰り返しの書き込み特性を
向上させた、まつたく新しい構造の半導体不揮発
性メモリに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a floating gate type semiconductor nonvolatile memory. More specifically, the layer structure of the charge injection region, insulating film, control gate, insulating film, floating gate, and insulating film, that is, semiconductor (S) - insulating film (I) - metal (M) - insulating film (I) - Metal (M) - Insulating film (I)
By using this structure (hereinafter abbreviated as SIMIMI), low voltage writing of 5V or less is realized.
This invention relates to a semiconductor nonvolatile memory with a new structure that has dramatically improved retention characteristics and repeated write characteristics.
従来のアバランシエ注入、チヤンネル注入ある
いはトンネル注入を用いた半導体不揮発性メモリ
の書き込み電圧には10V以上が必要であつた。 Conventional semiconductor nonvolatile memory using avalanche injection, channel injection, or tunnel injection requires a write voltage of 10 V or more.
また従来、半導体基板と浮遊ゲート間の絶縁膜
は、保持特性維持のため100Å程度必要であつた。
しかし100Å程度の膜厚の絶縁膜は書き込み回数
を重ねると、絶縁膜の劣化の進行により、104回
以上の書き替えを要する用途には不向きであつ
た。 Furthermore, conventionally, the insulating film between the semiconductor substrate and the floating gate required a thickness of about 100 Å in order to maintain retention characteristics.
However, an insulating film with a thickness of about 100 Å is unsuitable for applications that require rewriting more than 10 4 times because the insulating film deteriorates as the number of writes increases.
本発明は以上のような欠点を克服するためにな
されたものである。以下図を用いて本発明を詳述
する。 The present invention has been made to overcome the above-mentioned drawbacks. The present invention will be explained in detail below using the figures.
第１図に本発明の不揮発性半導体メモリの構造
断面図を示す。一例として、半導体基板１がＰ型
で、注入電荷が電子である場合について説明する
が、注入電荷を正孔にすることも可能である。基
本的には半導体基板１上の電荷注入領域２、厚さ
d1の非常に薄い絶縁膜７、制御ゲート５、厚さd2
の薄い絶縁膜８、浮遊ゲート６、絶縁膜１０の層
状構造になつている。非常に薄い絶縁膜７は厚さ
d1が35〜50Å程度と薄く作製する。非常に薄い絶
縁膜の膜質は100Å程度の薄い絶縁膜と比較して
繰返しの電荷注入に対し特性の安定していること
が知られている。これは35〜50Å程度の絶縁膜の
場合繰り返し書き込みにより発生する欠陥、つま
りトラツプに電子が捕獲されにくいからである。
非常に薄い絶縁膜７の膜厚は電荷注入時に制御ゲ
ート５に印加しなければならない電圧によつて決
定される。通常シリコンの酸化絶縁膜の場合、耐
圧は10MV／cmであり書き込み電圧3.5Vならば、
35Åまで薄くすることができる。制御ゲート５の
材質はポリシリコンが一般的であるが、アルミニ
ウムでもよいし、モリブデン、タングステン、タ
ンタル、チタンなど高融点金属やそのシリサイド
も用いることができる。制御ゲート５上の薄い絶
縁膜８は厚さd2が100Å以上のものを用いる。浮
遊ゲート６は、制御ゲート５と同様、ポリシリコ
ンの他、種々の金属を使用することができる。読
み出し用トランジスタのソース３及びドレイン４
は、電荷注入領域と同様のN+拡散層により形成
されている。浮遊ゲート６をゲート電極とし、絶
縁膜９を介して基板表面領域１１にチヤネルを形
成してい。浮遊ゲート６に書き込まれた電荷によ
つて読み出しトランジスタの閾値電圧が変動し、
これを“０”、“１”に対応させる。読み出し用ト
ランジスタのゲート絶縁膜９の膜厚d3は100Åか
ら1000Å程度である。浮遊ゲート６はフイールド
の絶縁膜１０で覆われている。 FIG. 1 shows a cross-sectional view of the structure of a nonvolatile semiconductor memory according to the present invention. As an example, a case will be described in which the semiconductor substrate 1 is of P type and the injected charges are electrons, but it is also possible to use holes as the injected charges. Basically, the charge injection region 2 on the semiconductor substrate 1, the thickness
Very thin insulating film 7 of d 1 , control gate 5, thickness d 2
It has a layered structure of a thin insulating film 8, a floating gate 6, and an insulating film 10. The thickness of the very thin insulating film 7 is
It is made thin with d1 of about 35 to 50 Å. It is known that the film quality of a very thin insulating film is more stable against repeated charge injection compared to a thin insulating film of about 100 Å. This is because in the case of an insulating film of about 35 to 50 Å, electrons are less likely to be captured by defects, that is, traps, which occur due to repeated writing.
The thickness of the very thin insulating film 7 is determined by the voltage that must be applied to the control gate 5 during charge injection. In the case of a normal silicon oxide insulating film, the withstand voltage is 10 MV/cm, and if the write voltage is 3.5 V,
It can be made as thin as 35 Å. The material of the control gate 5 is generally polysilicon, but aluminum may also be used, and high-melting point metals such as molybdenum, tungsten, tantalum, and titanium, and their silicides can also be used. The thin insulating film 8 on the control gate 5 has a thickness d 2 of 100 Å or more. Similar to the control gate 5, the floating gate 6 can be made of various metals in addition to polysilicon. Source 3 and drain 4 of read transistor
is formed by an N + diffusion layer similar to the charge injection region. Floating gate 6 is used as a gate electrode, and a channel is formed in substrate surface region 11 via insulating film 9. The threshold voltage of the read transistor changes depending on the charge written to the floating gate 6,
This corresponds to "0" and "1". The film thickness d3 of the gate insulating film 9 of the read transistor is approximately 100 Å to 1000 Å. The floating gate 6 is covered with a field insulating film 10.
次に本発明の電荷注入方法と特徴について述べ
る。第１図のＡ−A′線断面に沿つたエネルギー
バンド図を第２図に示す。制御ゲート５に圧電圧
を印加することにより、電子は電荷注入領域２か
ら非常に薄い絶縁膜７へトンネル注入され、制御
ゲート領域５でホツトエレクトロンを発生する。
非常に薄い絶縁膜を電子が透過するために制御ゲ
ート電圧を絶縁障壁の高さに相当する3.2V程度
にすればよい。注入された電荷は制御ゲート領域
８で更にホツトエレクトロンを発生する。制御ゲ
ート領域５と浮遊ゲート間の絶縁障壁は同様に
3.2ev程度あるので発生したホツトエレクトロン
は容易に浮遊ゲート領域６に注入される。書き込
み効率を上げるには制御ゲート電極５は電子の平
均自由行程以下の厚さをもつ金属であることが望
ましい。また制御ゲート５に書き込み電圧を印加
すると、浮遊ゲート６は容量結合して、ほぼ同程
度の電圧がかかり、従つて絶縁膜８には電界がか
からない。絶縁膜８の厚さd2は注入効率によらな
いので保持特性を充分に保証できる厚さに任意に
設定することができる。 Next, the charge injection method and features of the present invention will be described. FIG. 2 shows an energy band diagram taken along the section A-A' in FIG. 1. By applying a piezoelectric voltage to the control gate 5, electrons are tunnel-injected from the charge injection region 2 into the very thin insulating film 7, generating hot electrons in the control gate region 5.
In order for electrons to pass through a very thin insulating film, the control gate voltage should be set to about 3.2V, which corresponds to the height of the insulating barrier. The injected charges further generate hot electrons in the control gate region 8. The insulation barrier between the control gate region 5 and the floating gate is similarly
Since the voltage is about 3.2 ev, the generated hot electrons are easily injected into the floating gate region 6. In order to increase writing efficiency, the control gate electrode 5 is desirably made of a metal having a thickness equal to or less than the mean free path of electrons. Furthermore, when a write voltage is applied to the control gate 5, the floating gate 6 is capacitively coupled and approximately the same voltage is applied, so that no electric field is applied to the insulating film 8. The thickness d2 of the insulating film 8 does not depend on the injection efficiency and can be arbitrarily set to a thickness that can sufficiently guarantee the retention characteristics.
このように本発明での電荷注入方法によれば、
3.2V程度でトンネル注入が可能であり、従つて
電荷注入領域の絶縁膜は最低32Å程度まで薄くす
ることができ、繰り返し書き込みに対し安定な絶
縁膜を使用することができる。また浮遊ゲート６
の下の絶縁膜８に関しては厚さは保持特性を保証
できるよう任意に設けることができ、また電界が
かからないので104回以上の繰り返し書き込みに
対する安定性も優れている。 As described above, according to the charge injection method of the present invention,
Tunnel injection is possible at about 3.2 V, and therefore the insulating film in the charge injection region can be made as thin as at least about 32 Å, making it possible to use an insulating film that is stable against repeated writing. Also floating gate 6
The thickness of the insulating film 8 below can be set arbitrarily so as to guarantee retention characteristics, and since no electric field is applied, it has excellent stability against repeated writing over 10 4 times.
さらに本発明によれば注入方式は面注入であ
り、アバランシエ注入、チヤンネル注入方式のよ
うな線注入方式に比較して絶縁膜へのダメージも
少なくなる。 Further, according to the present invention, the implantation method is surface implantation, which causes less damage to the insulating film than line implantation methods such as avalanche implantation and channel implantation.
注入電荷発生方法の他の実施例について述べ
る。第３図にツエナーブレークダウン注入方式の
断面図を示す。注入電荷が電子の場合を示す。Ｐ
型基板２１上にN+領域２２と、ツエナブレーク
ダウン注入領域２９を近接して設ける。制御ゲー
ト領域２５とN+領域２２は正の同電位を印加し、
P+電荷注入領域２９でツエナーブレークダウン
をおこす。発生した電子は制御ゲート２５をトン
ネルし、浮遊ゲート２６に注入される。この様子
を第４図のエネルギーバンド図に示す。P+領域
でエネルギーバンドが強く曲げられツエナーブレ
ークダウンをおこして電子を発生し、浮遊ゲート
領域２６にトンネル注入する様子を示している。 Another example of the injection charge generation method will be described. FIG. 3 shows a cross-sectional view of the Zener breakdown injection method. The case where the injected charge is an electron is shown. P
An N + region 22 and a Zener breakdown implantation region 29 are provided on a mold substrate 21 in close proximity. The same positive potential is applied to the control gate region 25 and the N + region 22,
Zener breakdown occurs in the P + charge injection region 29. The generated electrons tunnel through the control gate 25 and are injected into the floating gate 26. This situation is shown in the energy band diagram of FIG. The energy band is strongly bent in the P + region, causing Zener breakdown and generating electrons, which are tunnel-injected into the floating gate region 26.
以上詳述したように本発明による半導体不揮発
性メモリによれば、SIMIMI構造を用いて、電荷
をトンネル注入することにより、5V以下、最低
3.2Vの低電圧で電子を注入することができ、そ
のため、50Åから32Åの非常に薄い絶縁膜を使用
することができ、保持特性、及び信頼性向上を同
時に成し遂げることができるものである。 As detailed above, according to the semiconductor non-volatile memory according to the present invention, by tunneling charge using the SIMIMI structure,
Electrons can be injected at a voltage as low as 3.2V, which makes it possible to use a very thin insulating film of 50 Å to 32 Å, thereby improving retention characteristics and reliability at the same time.
第１図は本発明の浮遊ゲート型半導体不揮発性
メモリの一実施例の構造断面図、第２図は第１図
のＡ−A′線に沿つたエネルギーバンド図、第３
図は本発明の他の実施例の構造断面図、第４図は
第３図のＢ−B′線に沿つたエネルギーバンド図
である。
１…半導体基板、２…電荷注入領域、３…ソー
ス領域、４…ドレイン領域、５…制御ゲート領
域、６…浮遊ゲート領域、７…非常に薄い絶縁
膜、８…薄い絶縁膜、９…ゲート絶縁膜、１０…
フイールド絶縁膜、１１…チヤネル領域、２１…
半導体基板、２２…N+領域、２３…ドレイン領
域、２４…ソース領域、３１…チヤネル領域、２
５…制御ゲート領域、２６…浮遊ゲート領域、２
７…絶縁膜、２８…絶縁膜、２０…フイールド絶
縁膜。
FIG. 1 is a structural cross-sectional view of an embodiment of the floating gate type semiconductor nonvolatile memory of the present invention, FIG. 2 is an energy band diagram along line A-A' in FIG. 1, and FIG.
The figure is a structural sectional view of another embodiment of the present invention, and FIG. 4 is an energy band diagram along line BB' in FIG. 3. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Charge injection region, 3... Source region, 4... Drain region, 5... Control gate region, 6... Floating gate region, 7... Very thin insulating film, 8... Thin insulating film, 9... Gate Insulating film, 10...
Field insulating film, 11... Channel region, 21...
Semiconductor substrate, 22...N + region, 23... Drain region, 24... Source region, 31... Channel region, 2
5... Control gate region, 26... Floating gate region, 2
7... Insulating film, 28... Insulating film, 20... Field insulating film.
Claims (1)
分に設けられた前記基板と逆導電型の電荷注入領
域と、該電荷注入領域上に設けられた第１の絶縁
膜と、第１の該絶縁膜上に設けられた制御ゲート
と、該制御ゲート上に設けられた第２の絶縁膜
と、該第２の絶縁膜上に設けられた浮遊デートと
から成り、前記電荷注入領域から電荷をトンネル
注入により前記浮遊ゲートに注入することを特徴
とする半導体不揮発性メモリ。 ２ 第１導電型の半導体基板と、該基板の表面部
分に設けられた前記基板と同導電型の高不純物濃
度の電荷注入領域と前記基板と逆導電型の高不純
物濃度領域と、該高不純物濃度領域と前記電荷注
入濃域上に設けられた第１の絶縁膜と、該第１の
絶縁膜上に設けられた制御ゲートと、該制御ゲー
ト上に設けられた第２の絶縁膜と、該第２の絶縁
膜上に設けられた浮遊ゲートとから成り、前記電
荷注入領域から電荷をツエナーブレークダウン１
２より発生させて前記浮遊ゲートに電荷をトンネ
ル注入させることを特徴とする半導体不揮発性メ
モリ。 ３ 電荷注入領域から離れて、半導体基板表面上
に設けられた読み出し用トランジスタのソース及
びドレイン領域と、該ソース及びドレイン領域に
挟まれた前記半導体基板表面領域上のチヤネル領
域と、該チヤネル領域上に設けられたゲート絶縁
膜と、該ゲート絶縁膜上に設けられ、前記第１項
または第２項記載の浮遊ゲートの一部に接続され
ている浮遊ゲートの他の部分とを設けたことを特
徴とする特許請求の範囲第１項または第２項記載
の半導体不揮発性メモリ。[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, a charge injection region of a conductivity type opposite to that of the substrate provided on a surface portion of the substrate, and a first insulator provided on the charge injection region. a control gate provided on the first insulating film, a second insulating film provided on the control gate, and a floating date provided on the second insulating film, A semiconductor nonvolatile memory characterized in that charge is injected from the charge injection region into the floating gate by tunnel injection. 2 a semiconductor substrate of a first conductivity type; a charge injection region with a high impurity concentration of the same conductivity type as the substrate provided on a surface portion of the substrate; a high impurity concentration region with a conductivity type opposite to the substrate; a first insulating film provided on the concentrated region and the charge injection concentrated region, a control gate provided on the first insulating film, and a second insulating film provided on the control gate; a floating gate provided on the second insulating film, and transfers charges from the charge injection region to Zener breakdown 1.
2. A semiconductor nonvolatile memory characterized in that charges are tunnel-injected into the floating gate by generating charges from the above. 3. A source and drain region of a readout transistor provided on the surface of the semiconductor substrate away from the charge injection region, a channel region on the surface region of the semiconductor substrate sandwiched between the source and drain regions, and a region on the channel region. A gate insulating film provided on the gate insulating film, and another part of the floating gate provided on the gate insulating film and connected to a part of the floating gate according to the above item 1 or 2. A semiconductor nonvolatile memory according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15038684A JPS6129177A (en) | 1984-07-19 | 1984-07-19 | Semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15038684A JPS6129177A (en) | 1984-07-19 | 1984-07-19 | Semiconductor nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6129177A JPS6129177A (en) | 1986-02-10 |
| JPH0430755B2 true JPH0430755B2 (en) | 1992-05-22 |
Family
ID=15495856
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15038684A Granted JPS6129177A (en) | 1984-07-19 | 1984-07-19 | Semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6129177A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050056200A (en) * | 2002-08-13 | 2005-06-14 | 제네럴 세미컨덕터, 인코포레이티드 | A dmos device with a programmable threshold voltage |
| JP5644757B2 (en) | 2011-12-28 | 2014-12-24 | 株式会社日本自動車部品総合研究所 | Pressure control device |
-
1984
- 1984-07-19 JP JP15038684A patent/JPS6129177A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6129177A (en) | 1986-02-10 |
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