JPH0430199B2 - - Google Patents
Info
- Publication number
- JPH0430199B2 JPH0430199B2 JP57141143A JP14114382A JPH0430199B2 JP H0430199 B2 JPH0430199 B2 JP H0430199B2 JP 57141143 A JP57141143 A JP 57141143A JP 14114382 A JP14114382 A JP 14114382A JP H0430199 B2 JPH0430199 B2 JP H0430199B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- paste
- ceramic substrate
- electronic component
- printing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004020 conductor Substances 0.000 claims description 24
- 239000000919 ceramic Substances 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 238000007747 plating Methods 0.000 claims description 13
- 238000010304 firing Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910052746 lanthanum Inorganic materials 0.000 claims description 4
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910017309 Mo—Mn Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000011572 manganese Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 2
- 239000011230 binding agent Substances 0.000 description 2
- 230000000740 bleeding effect Effects 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000010959 steel Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003779 heat-resistant material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052704 radon Inorganic materials 0.000 description 1
- SYUHGPGVQRZVTB-UHFFFAOYSA-N radon atom Chemical compound [Rn] SYUHGPGVQRZVTB-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Description
【発明の詳細な説明】
本発明はセラミツク基板、特に抵抗素子を組み
込んだセラミツク基板から成る電子部品実装構造
体の製造法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an electronic component mounting structure made of a ceramic substrate, particularly a ceramic substrate incorporating a resistance element.
従来、アルミナ粉末にシリカ等のフラツクスを
加え、さらに有機バインダで固めてシート状にし
たグリーンシートに抵抗素子（単に抵抗とも称
す。）を内蔵する場合、(1)、グリーンシートを還
元性雰囲気で焼成して得たセラミツク板に低温焼
成の導体ペースト（たとえば銅ペースト）を印刷
した後、酸化性低温雰囲気で焼成して厚膜抵抗を
形成する方法、(2)、グリーンシートを還元性雰囲
気で焼成して得たセラミツク板の表面のモリブテ
ン（Mo）−マンガン（Mn）あるいはタングステ
ン（Ｗ）等からなる導体層表面にめつきを施して
金めつき膜で被つた後、抵抗形成領域にカーボン
ペーストを印刷しかつ焼成することによつて抵抗
を形成する方法、が知られている。 Conventionally, when a resistance element (also simply referred to as a resistor) is built into a green sheet made by adding flux such as silica to alumina powder and solidifying it with an organic binder, (1) the green sheet is placed in a reducing atmosphere. A method of printing a low-temperature-fired conductor paste (for example, copper paste) on a ceramic plate obtained by firing, and then firing it in an oxidizing low-temperature atmosphere to form a thick film resistor. (2) A green sheet is printed in a reducing atmosphere. After plating the surface of the conductor layer made of molybdenum (Mo)-manganese (Mn) or tungsten (W) on the surface of the fired ceramic plate and covering it with a gold plating film, carbon is applied to the resistor formation area. A method of forming a resistor by printing and firing a paste is known.
しかし、前者の方法は焼成後のセラミツク板上
に導体ペーストを印刷するため、導体ペーストは
セラミツク板上に滲むようにして拡がる傾向があ
り、精緻なパターンが作り難い。したがつて、フ
エイスダウン・ボンデイングチツプ用の接続用ラ
ンドのパターンも精緻となり難く、チツプの搭載
が難しい。また、導体ペースト（Cuペースト）
はガラスを含むため配線層の抵抗が大きくなる欠
点があるとともに、半田の濡れが悪く、チツプ搭
載時の接合性が低い欠点である。 However, in the former method, since the conductive paste is printed on the ceramic board after firing, the conductive paste tends to ooze and spread on the ceramic board, making it difficult to create a precise pattern. Therefore, it is difficult to form a connection land pattern for a face-down bonding chip with precision, making it difficult to mount the chip. Also, conductive paste (Cu paste)
Since it contains glass, it has the disadvantage that the resistance of the wiring layer is high, and it also has poor solder wettability and poor bonding properties when mounting chips.
また、後者の導体層表面を金めつき膜で被い酸
化雰囲気下の抵抗形成時に導体層が酸化するのを
防止する方法では、高価な金を用いるためコスト
が高くなる難点があるとともに、カーボンペース
トによる抵抗は信頼性が低い欠点がある。 In addition, the latter method, in which the surface of the conductor layer is covered with a gold plating film to prevent the conductor layer from oxidizing when forming a resistor in an oxidizing atmosphere, has the disadvantage of increasing costs due to the use of expensive gold. Paste resistance has the disadvantage of low reliability.
したがつて、本発明の目的は、信頼性の高い抵
抗素子を有した安価な電気部品実装構造体の製造
法を提供するものである。 Therefore, an object of the present invention is to provide a method for manufacturing an inexpensive electrical component mounting structure having a highly reliable resistance element.
かかる目的を達成するための本発明は、アルミ
ナを主成分とするグリーンシートの表面にMo−
Mn、Ｗから選ばれた一つの導体材料を主成分と
する導体ペーストを所望パターンに印刷する段階
と、そのシートを還元雰囲気で焼成して前記導体
材料から成る導体層を有するセラミツク基板を形
成する段階と、前記セラミツク基板表面に導出す
る前記導体層の少なくとも抵抗接続端子部分表面
及び電子部品が搭載されるべき部分表面に銅めつ
き層を施す段階と、そのセラミツク基板の抵抗形
成領域に前記抵抗端子接続部分の銅めつき層に接
するようにしてランタンボライドを主成分とする
抵抗ペーストを印刷する段階と、酸素を含まない
不活性または還元性雰囲気で前記印刷された抵抗
体を焼成する段階と、前記電子部品が搭載される
べき部分表面の銅めつき層に半田を介して電子部
品を取り付ける段階と、から成ることを特徴とす
るものである。 In order to achieve such an object, the present invention provides Mo-
A step of printing a conductive paste mainly composed of one conductive material selected from Mn and W into a desired pattern, and firing the sheet in a reducing atmosphere to form a ceramic substrate having a conductive layer made of the conductive material. a step of applying a copper plating layer to at least the surface of the resistor connection terminal portion of the conductor layer led out to the surface of the ceramic substrate and the surface of the portion on which electronic components are to be mounted; A step of printing a resistor paste mainly composed of lanthanum boride so as to be in contact with the copper plating layer of the terminal connection part, and a step of firing the printed resistor in an inert or reducing atmosphere that does not contain oxygen. and attaching the electronic component via solder to the copper plating layer on the surface of the portion on which the electronic component is to be mounted.
第１図は本発明の一実施例によるセラミツク基
板の製造方法を示すフローチヤート、第２図ａ〜
ｃは同じく各製造段階でのワークの断面図、第３
図は同じくセラミツク基板の一部を示す平面図で
ある。 FIG. 1 is a flowchart showing a method for manufacturing a ceramic substrate according to an embodiment of the present invention, and FIG.
c is also a cross-sectional view of the workpiece at each manufacturing stage, the third
The figure is also a plan view showing a part of the ceramic substrate.
セラミツク基板を製造するには、先ずグリーン
シートおよび導体ペーストならびに絶縁ペースト
を用意した後、第２図ａに示すように、グリーン
シート１上に導体ペースト２および絶縁ペースト
３を繰り返して印刷し（第１図のフローチヤート
参照）、多層板４を形成する。そして、この多層
板４を常用の還元雰囲気で焼成して第２図ｂで示
すような焼成板５を形成し、第３図に示すよう
に、対となる抵抗接続端子６、部品搭載用ランド
７を含む配線層８を焼成板５の内部および表面に
亘つて設ける。 To manufacture a ceramic substrate, first prepare a green sheet, conductive paste, and insulating paste, and then print conductive paste 2 and insulating paste 3 repeatedly on green sheet 1, as shown in Figure 2a. 1), the multilayer board 4 is formed. Then, this multilayer board 4 is fired in a commonly used reducing atmosphere to form a fired board 5 as shown in FIG. 2b, and as shown in FIG. A wiring layer 8 including wiring layer 7 is provided inside and over the surface of fired board 5.
前記グリーンシート１はアルミナ粉末にシリカ
などのフラツクスを加え、有機バインダによつて
シート状にしたものである。この結果、絶縁・導
体ペーストの印刷時にグリーンシート１はペース
ト中の溶剤を吸収し易くなり、印刷層の側方への
滲みが少なくなる。したがつて、印刷パターンの
微細化、精緻化が可能となり、前記部品搭載用ラ
ンド７の各間隙の縮小化も可能となる。 The green sheet 1 is made by adding flux such as silica to alumina powder and forming it into a sheet using an organic binder. As a result, when printing an insulating/conductive paste, the green sheet 1 easily absorbs the solvent in the paste, reducing sideward bleeding of the printed layer. Therefore, it is possible to make the printed pattern finer and more precise, and it is also possible to reduce the gaps between the component mounting lands 7.
前記導体ペーストはグリーンシート１の焼成温
度によつて劣化しないMo−Mn、Ｗ等の高耐熱
材料を主成分としている。そして、前記部品搭載
用ランド７の幅は10μｍ、ピツチは100μｍとな
り、従来のそれぞれの数値200μｍに対して大幅
に小さくなる。なお、実施例では部品搭載用ラド
ン７は多層板４に内部の導体ペースト層２にスル
ーホールに埋め込んだ導体ペーストによる接続部
９で電気的に接続された構造となつているが、多
層板４上に延在させて所定の導体ペースト層に接
続されるようにしてもよい。また、各導体ペース
ト層はたとえば20μｍ程度の厚さに、絶縁ペース
ト層はたとえば100μｍ程度の厚さに、グリーン
シート１はたとえば100μｍの厚さになつている。 The conductor paste is mainly composed of a highly heat-resistant material such as Mo-Mn and W, which does not deteriorate depending on the firing temperature of the green sheet 1. The width of the component mounting land 7 is 10 μm, and the pitch is 100 μm, which are significantly smaller than the conventional values of 200 μm. In the embodiment, the component mounting Radon 7 has a structure in which it is electrically connected to the multilayer board 4 by a connection part 9 made of a conductor paste embedded in a through hole in the conductor paste layer 2 inside the multilayer board 4. It may be made to extend upward and be connected to a predetermined conductive paste layer. Further, each conductor paste layer has a thickness of, for example, about 20 μm, the insulating paste layer has a thickness of, for example, about 100 μm, and the green sheet 1 has a thickness of, for example, 100 μm.
つぎに、この多層板４を常用の焼成処理、すな
わち還元性雰囲気下で焼成し、硬化させる。導体
ペースト層は導体層１０となり、グリーンシート
１および絶縁ペースト層は一体化されたセラミツ
ク板１１となる。 Next, this multilayer board 4 is subjected to a conventional firing process, that is, fired in a reducing atmosphere to harden it. The conductor paste layer becomes a conductor layer 10, and the green sheet 1 and the insulating paste layer become an integrated ceramic board 11.
つぎに、銅めつき処理を施して、セラミツク板
１１の上面に露出している導体層１０の表面に
2μｍ程度の厚さに銅めつき膜１２を形成する
〔第２図ｂ参照〕。 Next, copper plating is applied to the surface of the conductor layer 10 exposed on the top surface of the ceramic plate 11.
A copper plating film 12 is formed to a thickness of about 2 μm [see FIG. 2b].
つぎに、同図ｃに示すように、対となる抵抗接
続端子６間に亘つてランタンボライド（LaB6）
を主成分とする抵抗ペーストを印刷した後、中性
（不活性）あるいは還元性雰囲気で焼成（800〜
900℃で50分）し、抵抗（抵抗素子）１３を形成
する。このLaB6は印刷による銅厚膜に接続可能
な抵抗ペーストとして開発市販されているもので
あり、本発明者等によつて銅めつき膜との間でも
良好な電気的接続が行えることを実験によつて確
認しているものである。このLaB6は酸素を含ま
ない不活性（中性）ガス、あるいは還元ガス雰囲
気で焼成処理される特長がある。この結果、抵抗
形成時には、Ｗ等からなる前記導体層１０の酸化
は防止できることになり、導体層１０の劣化は生
じない。 Next, as shown in FIG .
After printing a resistance paste whose main component is
900° C. for 50 minutes) to form a resistor (resistance element) 13. This LaB 6 has been developed and commercially available as a resistive paste that can be connected to a thick printed copper film, and the inventors have conducted experiments to demonstrate that it can form a good electrical connection even with a copper plated film. This has been confirmed by. This LaB 6 has the feature that it can be fired in an oxygen-free inert (neutral) gas or reducing gas atmosphere. As a result, when forming a resistor, the conductor layer 10 made of W or the like can be prevented from being oxidized, and no deterioration of the conductor layer 10 occurs.
このようなセラミツク基板１４にあつては、表
面の電子部品搭載用ランド７に半田を介して電子
部品であるICチツプ１６をフエイスダウン・ボ
ンデイングによつて固定する。半田１５はあらか
じめICチツプ１６の電極部にバンプ電極の形と
して形成しておく。 In the case of such a ceramic substrate 14, an IC chip 16, which is an electronic component, is fixed to the electronic component mounting land 7 on the surface via solder by face-down bonding. The solder 15 is formed in advance in the form of a bump electrode on the electrode portion of the IC chip 16.
このような実施例によれば、導体層を形成する
ための導体ペーストの印刷は、吸湿性のあるグリ
ーンシート上に行なわれる。この結果、ペースト
中の溶剤がグリーンシートに印刷されてにじみが
起きず、微細パターン化が可能となる。したがつ
て、ICチツプ等の部品をフエイスダウン・ボン
デイングで実装する際の部品搭載用ランドの縮小
化、ランド間ピツチの狭小化が可能となり、部品
のバンプ電極に各ランドは適正に対応できるよう
になつて実装が可能となる。 According to such an embodiment, the printing of the conductor paste for forming the conductor layer is carried out on a hygroscopic green sheet. As a result, the solvent in the paste is printed onto the green sheet without bleeding, making it possible to form fine patterns. Therefore, when mounting components such as IC chips by face-down bonding, it is possible to reduce the size of the component mounting land and narrow the pitch between the lands, so that each land can appropriately correspond to the bump electrode of the component. It becomes possible to implement it.
また、配線層の表面は抵抗値が極めて小さい鋼
めつき膜で被われていることから、配線層の抵抗
値は従来に比較して小さくなる。また、銅めつき
膜は従来のようなガラスフリツト（シリカ）等を
含まないピユアーな鋼であることから、ICチツ
プ実装時に用いる半田との濡れ性が良好となり、
信頼度の高い実装が可能となる。 Furthermore, since the surface of the wiring layer is covered with a steel plating film having an extremely low resistance value, the resistance value of the wiring layer is smaller than that of the conventional wiring layer. In addition, since the copper plating film is made of pure steel and does not contain conventional glass frit (silica), it has good wettability with the solder used when mounting IC chips.
Highly reliable implementation becomes possible.
また、ランタンボライドは従来のカーボン抵抗
に比較して良質の抵抗を形作る。また、ランタン
ボライドの焼成は酸素を含まない雰囲気で行なえ
ることから、従来のように配線層を高価な金で被
う必要もなく、少なくともランタンボライドとの
接続部にのみ安価な銅を介在させればよくなる。
この結果、コストの低減が図れる。なお、露出す
る配線層全長に亘つて設ければ、前述のように配
線層の抵抗値の減少化、半田の濡れ性向上化を図
ることができるようになる。 Lanthamboride also forms a high quality resistor compared to traditional carbon resistors. Additionally, since lanthanum boride can be fired in an oxygen-free atmosphere, there is no need to cover the wiring layer with expensive gold as in the past, and at least only the connection with lanthanum boride can be made of inexpensive copper. It will be better if you intervene.
As a result, costs can be reduced. Note that if it is provided over the entire length of the exposed wiring layer, the resistance value of the wiring layer can be reduced and the solder wettability can be improved as described above.
なお、本発明は前記実施例に限定されない。 Note that the present invention is not limited to the above embodiments.
以上のように、本発明によれば、精緻で抵抗値
が小さくかつ半田との濡れ性が良好な高品質の抵
抗素子を有するセラミツク基板を安価に提供する
ことができる。 As described above, according to the present invention, it is possible to provide at a low cost a ceramic substrate having a high-quality resistive element that is precise, has a low resistance value, and has good wettability with solder.
第１図は本発明の一実施例によるセラミツク基
板の製造方法を示すフローチヤート、第２図ａ〜
ｃは同じく各製造段階でのワークの断面図、第３
図は同じくセラミツク基板の一部を示す平面図で
ある。
１……グリーンシート、２……導体ペースト、
３……絶縁ペースト、５……焼成板、６……抵抗
接続端子、７……部品搭載ランド、８……配線
層、１０……導体層、１２……銅めつき膜、１３
……抵抗、１４……セラミツク基板、１５……半
田、１６……ICチツプ。
FIG. 1 is a flowchart showing a method for manufacturing a ceramic substrate according to an embodiment of the present invention, and FIG.
c is also a cross-sectional view of the workpiece at each manufacturing stage, the third
The figure is also a plan view showing a part of the ceramic substrate. 1...green sheet, 2...conductor paste,
3... Insulating paste, 5... Baked board, 6... Resistance connection terminal, 7... Component mounting land, 8... Wiring layer, 10... Conductor layer, 12... Copper plating film, 13
...Resistor, 14...Ceramic board, 15...Solder, 16...IC chip.
Claims (1)
面にMo−Mn、Ｗから選ばれた一つの導体材料
を主成分とする導体ペーストを所望パターンに印
刷する段階と、 そのシートを還元雰囲気で焼成して前記導体材
料から成る導体層を有するセラミツク基板を形成
する段階と、 前記セラミツク基板表面に導出する前記導体層
の少なくとも抵抗接続端子部分表面及び電子部品
が搭載されるべき部分表面に銅めつき層を施す段
階と、 そのセラミツク基板の抵抗形成領域に前記抵抗
端子接続部分の銅めつき層に接するようにしてラ
ンタンボライドを主成分とする抵抗ペーストを印
刷する段階と、 酸素を含まない不活性または還元性雰囲気で前
記印刷された抵抗体を焼成する段階と、 前記電子部品が搭載されるべき部分表面の銅め
つき層に半田を介して電子部品を取り付ける段階
と、 から成ることを特徴とする電子部品実装体の製造
法。[Claims] 1. A step of printing a conductive paste mainly composed of one conductive material selected from Mo-Mn and W on the surface of a green sheet mainly composed of alumina, and printing the sheet in a desired pattern. firing in a reducing atmosphere to form a ceramic substrate having a conductor layer made of the conductor material; and at least the surface of the resistance connection terminal portion of the conductor layer led out to the surface of the ceramic substrate and the surface of the portion on which electronic components are to be mounted. printing a resistor paste containing lanthanum boride as a main component on the resistor forming area of the ceramic substrate in contact with the copper plating layer of the resistor terminal connecting portion; firing the printed resistor in an inert or reducing atmosphere that does not contain the electronic component; and attaching the electronic component via solder to the copper plating layer on the surface of the part on which the electronic component is to be mounted. A method for manufacturing an electronic component mounting body, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14114382A JPS5932194A (en) | 1982-08-16 | 1982-08-16 | Ceramic board and method of producing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14114382A JPS5932194A (en) | 1982-08-16 | 1982-08-16 | Ceramic board and method of producing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5932194A JPS5932194A (en) | 1984-02-21 |
| JPH0430199B2 true JPH0430199B2 (en) | 1992-05-21 |
Family
ID=15285160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14114382A Granted JPS5932194A (en) | 1982-08-16 | 1982-08-16 | Ceramic board and method of producing same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5932194A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02254785A (en) * | 1989-03-29 | 1990-10-15 | Ngk Insulators Ltd | Manufacture of circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56146201A (en) * | 1980-04-14 | 1981-11-13 | Matsushita Electric Ind Co Ltd | Alumina circuit board with glazed resistor |
| JPS58153394A (en) * | 1982-03-08 | 1983-09-12 | 日立化成工業株式会社 | Method of producing ceramic multilayer circuit board with resistor |
-
1982
- 1982-08-16 JP JP14114382A patent/JPS5932194A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56146201A (en) * | 1980-04-14 | 1981-11-13 | Matsushita Electric Ind Co Ltd | Alumina circuit board with glazed resistor |
| JPS58153394A (en) * | 1982-03-08 | 1983-09-12 | 日立化成工業株式会社 | Method of producing ceramic multilayer circuit board with resistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5932194A (en) | 1984-02-21 |
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