JPH04297086A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH04297086A JPH04297086A JP3048107A JP4810791A JPH04297086A JP H04297086 A JPH04297086 A JP H04297086A JP 3048107 A JP3048107 A JP 3048107A JP 4810791 A JP4810791 A JP 4810791A JP H04297086 A JPH04297086 A JP H04297086A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- integrated circuit
- hybrid integrated
- board
- trimming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 238000009966 trimming Methods 0.000 abstract description 23
- 239000010410 layer Substances 0.000 abstract description 17
- 239000011229 interlayer Substances 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 description 16
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Adjustable Resistors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、混成集積回路に係り、
特に混成集積回路基板に形成される抵抗体のトリミング
に関するものである。[Industrial Application Field] The present invention relates to a hybrid integrated circuit.
In particular, it relates to trimming of resistors formed on hybrid integrated circuit boards.
【０００２】0002
【従来の技術】図３は従来の混成集積回路のトリミング
される抵抗体部分の断面図であり、図４はトリミングさ
れた抵抗体部分の斜視図である。これらの図において、
１は混成集積回路の主体である基板、２はこの基板１上
に形成された抵抗体、３は混成集積回路上の他の電子部
品（図示せず）と抵抗体２とを接続するための導体、４
は前記基板１上の抵抗体２の取り付けられた面と相対す
る面に取り付けられた裏面導体、５は前記抵抗体２の抵
抗値を増加させるためのトリミング部である。2. Description of the Related Art FIG. 3 is a sectional view of a trimmed resistor portion of a conventional hybrid integrated circuit, and FIG. 4 is a perspective view of the trimmed resistor portion. In these figures,
1 is a substrate which is the main body of the hybrid integrated circuit, 2 is a resistor formed on this substrate 1, and 3 is a resistor for connecting other electronic components (not shown) on the hybrid integrated circuit to the resistor 2. conductor, 4
5 is a back conductor attached to the surface of the substrate 1 opposite to the surface on which the resistor 2 is attached, and 5 is a trimming portion for increasing the resistance value of the resistor 2.
【０００３】次に、動作について説明する。抵抗体２の
幅ＷＲ をトリミング部５において、トリミング幅ＷＴ
だけせまくすることにより、電流の流れる幅がＷＲ
−ＷＴ となり、抵抗体２の抵抗値を増加させ、混成集
積回路の電流等の調整を行っている。Next, the operation will be explained. The width WR of the resistor 2 is changed to the trimming width WT in the trimming section 5.
By making it as narrow as possible, the width of the current can be reduced to WR.
-WT, the resistance value of the resistor 2 is increased, and the current of the hybrid integrated circuit is adjusted.
【０００４】0004
【発明が解決しようとする課題】従来の混成集積回路の
抵抗体２のトリミングは以上のように行われているので
、抵抗体２をトリミングしない場合の抵抗値から大幅に
、例えば１００倍の抵抗値まで増加させる必要がある場
合に、抵抗体２の幅ＷＲ にトリミング幅ＷＴ を非常
に近くする必要がある。この場合、抵抗体２の幅ＷＲ
とトリミング幅ＷＴ が等しくなって断線となり、抵抗
の開放が起きないようにするために、トリミング装置の
精度が必要となるという問題点があった。[Problems to be Solved by the Invention] Since the trimming of the resistor 2 of the conventional hybrid integrated circuit is performed as described above, the resistance value is significantly increased, for example, 100 times the resistance value when the resistor 2 is not trimmed. If it is necessary to increase the trimming width WT to a certain value, it is necessary to make the trimming width WT very close to the width WR of the resistor 2. In this case, the width WR of the resistor 2
There is a problem in that the trimming device needs to be highly accurate in order to prevent the trimming width WT from becoming equal and causing a wire breakage, thereby preventing the resistor from opening.
【０００５】また、混成集積回路の基板１を他の材質の
ケ−ス（図示ぜす）に取り付ける場合に、トリミング幅
ＷＴ を抵抗体２の幅ＷＲ 近くまでトリミングを行う
と、基板１とケ−スとの熱膨張係数の差により、温度の
変化においてバイメタルとなり、抵抗体２のトリミング
の残りの幅ＷＲ −ＷＴ が短い場合に抵抗体２の開放
が起こりやすくなるという問題点があった。Furthermore, when the substrate 1 of the hybrid integrated circuit is attached to a case made of another material (not shown), if the trimming width WT is trimmed to be close to the width WR of the resistor 2, the substrate 1 and the case will be separated. - Due to the difference in thermal expansion coefficient between the resistor element 2 and the metal element, the resistor element 2 becomes bimetallic due to a change in temperature, and when the remaining trimmed width WR -WT of the resistor element 2 is short, there is a problem that the resistor element 2 is likely to open.
【０００６】本発明は、上記のような問題点を解消する
ためになされたもので、トリミングしない場合の抵抗値
から大幅に抵抗値を増加させる場合のトリミングが可能
となり、かつトリミング装置の精度をあまり要求せず、
温度の変化におけるバイメタル効果による抵抗の開放を
引き起こしにくい抵抗体を持つ混成集積回路を得ること
を目的とする。The present invention has been made to solve the above-mentioned problems, and enables trimming to significantly increase the resistance value from the resistance value without trimming, and improves the precision of the trimming device. Don't ask too much,
The purpose of this invention is to obtain a hybrid integrated circuit having a resistor that is less likely to cause open resistance due to bimetallic effects due to temperature changes.
【０００７】[0007]
【課題を解決するための手段】本発明に係る混成集積回
路は、混成集積回路基板を多層基板とし、この多層基板
の表面と層間に別々の抵抗体を設け、２つ以上の各抵抗
体を導体スル−ホ−ルにより並列接続したものである。[Means for Solving the Problems] A hybrid integrated circuit according to the present invention has a hybrid integrated circuit board that is a multilayer board, separate resistors are provided on the surface of the multilayer board and between the layers, and two or more resistors are connected to each other. They are connected in parallel using conductor through holes.
【０００８】[0008]
【作用】本発明における混成集積回路は、抵抗体を多層
基板の表面と層間に別々に設け、２つ以上の各抵抗体を
導体スル−ホ−ルにより並列接続したことにより、多層
基板表面の抵抗体に対しトリミングを行い、多層基板表
面の抵抗体が開放になったとしても、層間の抵抗体が並
列接続されているため、回路としては開放にならない。[Operation] In the hybrid integrated circuit of the present invention, resistors are provided separately on the surface of the multilayer substrate and between the layers, and two or more resistors are connected in parallel using conductor through holes. Even if the resistor on the surface of the multilayer board becomes open by trimming the resistor, the circuit will not become open because the resistors between the layers are connected in parallel.
【０００９】[0009]
【実施例】以下、本発明について説明する。図１は本発
明の一実施例を示す混成集積回路の要部の断面図であり
、図２は、図１の等価回路である。図１，図２において
、１ａは混成集積回路の主体である基板を多層とした時
の回路パタ−ンが設けられる側の上層基板であり、１ｂ
は下層基板である。２ａは前記上層基板１ａの表面に設
けられた表面抵抗体、２ｂは前記上層基板１ａと下層基
板１ｂの層間に設けられた層間抵抗体、３は混成集積回
路上の他の電子部品と前記表面抵抗体２ａとを接続する
導体、４は前記下層基板１ｂの層間抵抗体２ｂの取り付
けられた面と相対する面に取り付けられた裏面導体、６
は前記表面抵抗体２ａと層間抵抗体２ｂとを並列接続す
るための導体スル−ホ−ルである。表面抵抗体２ａと層
間抵抗体２ｂは導体スル−ホ−ル６により電気的に並列
接続される。また、表面抵抗体２ａは上層基板１ａの表
面に設けられているため、トリミングが可能となり、層
間抵抗体２ｂは上層基板１ａと下層基板１ｂの層間に設
けられているため、トリミングは不可能となる。このた
め、表面抵抗体２ａの抵抗値に対し層間抵抗体２ｂの抵
抗値を大きくし、トリミングにより目的とする最大の抵
抗値に層間抵抗体２ｂの抵抗値を等しくすることにより
、表面抵抗体１ａが開放になったとしても、層間抵抗体
２ｂが並列接続されているため、抵抗全体では開放とは
ならない。このため、表面抵抗体２ａのトリミング装置
に対し精度が要求されず、安価な装置でトリミングが可
能となる。また、温度の変化によるバイメタル効果が起
きても、層間抵抗体２ｂはトリミングされていないため
、作成時の抵抗体幅のままであり、抵抗体の開放が非常
に起こりにくくなる。[Example] The present invention will be explained below. FIG. 1 is a sectional view of a main part of a hybrid integrated circuit showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit of FIG. In FIGS. 1 and 2, 1a is the upper layer substrate on the side where a circuit pattern is provided when the main substrate of the hybrid integrated circuit is multilayered, and 1b
is the lower substrate. 2a is a surface resistor provided on the surface of the upper layer substrate 1a, 2b is an interlayer resistor provided between the layers of the upper layer substrate 1a and the lower layer substrate 1b, and 3 is a surface resistor provided on the surface of the hybrid integrated circuit. A conductor connecting the resistor 2a, 4 is a back conductor attached to the surface of the lower substrate 1b opposite to the surface on which the interlayer resistor 2b is attached, 6
is a conductor through-hole for connecting the surface resistor 2a and the interlayer resistor 2b in parallel. The surface resistor 2a and the interlayer resistor 2b are electrically connected in parallel through conductor through holes 6. Furthermore, since the surface resistor 2a is provided on the surface of the upper layer substrate 1a, trimming is possible, and the interlayer resistor 2b is provided between the upper layer substrate 1a and the lower layer substrate 1b, so trimming is not possible. Become. Therefore, by increasing the resistance value of the interlayer resistor 2b with respect to the resistance value of the surface resistor 2a, and making the resistance value of the interlayer resistor 2b equal to the desired maximum resistance value by trimming, the surface resistor 1a Even if it becomes open, the entire resistance will not become open because the interlayer resistor 2b is connected in parallel. Therefore, precision is not required for the trimming device for the surface resistor 2a, and trimming can be performed using an inexpensive device. Further, even if a bimetal effect occurs due to a change in temperature, since the interlayer resistor 2b is not trimmed, the width of the resistor remains the same as when it was created, making it extremely difficult for the resistor to open.
【００１０】なお、上記実施例では、多層基板を用いて
２つの抵抗体２ａ，２ｂを並列接続した場合について説
明したが、抵抗体の数はこれに限らず、３つ以上を並列
接続しても同様の効果が得られる。[0010] In the above embodiment, the case was explained in which two resistors 2a and 2b were connected in parallel using a multilayer board, but the number of resistors is not limited to this, and three or more resistors can be connected in parallel. A similar effect can be obtained.
【００１１】[0011]
【発明の効果】以上説明したように、本発明によれば、
混成集積回路基板を多層基板とし、この多層基板の表面
と層間に別々の抵抗体を設け、２つ以上の各抵抗体を導
体スル−ホ−ルにより並列接続したので、トリミングに
よる抵抗値の調整範囲を広くとっても、安価なトリミン
グ装置で抵抗値の調整が可能となり、バイメタル効果に
おいても抵抗の開放がなくなる。[Effects of the Invention] As explained above, according to the present invention,
The hybrid integrated circuit board is a multilayer board, separate resistors are provided on the surface of this multilayer board and between the layers, and two or more resistors are connected in parallel using conductor through holes, so the resistance value can be adjusted by trimming. Even if the range is widened, the resistance value can be adjusted using an inexpensive trimming device, and even in the bimetal effect, there is no open resistance.
【図１】本発明による混成集積回路の抵抗部分の断面図
である。FIG. 1 is a cross-sectional view of a resistive portion of a hybrid integrated circuit according to the invention.
【図２】本発明による抵抗部分の等価回路図である。FIG. 2 is an equivalent circuit diagram of a resistor section according to the present invention.
【図３】従来例の混成集積回路の抵抗部分の断面図であ
る。FIG. 3 is a cross-sectional view of a resistor portion of a conventional hybrid integrated circuit.
【図４】図３の従来例の斜視図である。FIG. 4 is a perspective view of the conventional example shown in FIG. 3;
１ａ 上層基板 １ｂ 下層基板 ２ａ 表面抵抗体 ２ｂ 層間抵抗体 ３ 導体 ４ 裏面導体 ５ トリミング部 ６ 導体スル−ホ−ル 1a Upper layer board 1b Lower layer board 2a Surface resistor 2b Interlayer resistor 3 Conductor 4 Back conductor 5 Trimming section 6 Conductor through hole
Claims (1)
膜抵抗体を持つ混成集積回路において、混成集積回路基
板を多層基板とし、この多層基板の表面と層間に別々の
抵抗体を設け、２つ以上の各抵抗体を導体スル−ホ−ル
により並列接続したことを特徴とする混成集積回路。1. A hybrid integrated circuit having a thick film resistor that is trimmed to adjust current, etc., wherein the hybrid integrated circuit board is a multilayer board, separate resistors are provided on the surface of the multilayer board and between the layers, and two resistors are provided. A hybrid integrated circuit characterized in that two or more resistors are connected in parallel through conductor through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3048107A JPH04297086A (en) | 1991-03-13 | 1991-03-13 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3048107A JPH04297086A (en) | 1991-03-13 | 1991-03-13 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04297086A true JPH04297086A (en) | 1992-10-21 |
Family
ID=12794094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3048107A Pending JPH04297086A (en) | 1991-03-13 | 1991-03-13 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04297086A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011023697A (en) * | 2009-07-17 | 2011-02-03 | Samsung Electro-Mechanics Co Ltd | Multilayer wiring board and method of manufacturing the same |
| JP2016008946A (en) * | 2014-06-26 | 2016-01-18 | 京セラ株式会社 | Wiring board, temperature sensing element, and temperature sensing device |
-
1991
- 1991-03-13 JP JP3048107A patent/JPH04297086A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011023697A (en) * | 2009-07-17 | 2011-02-03 | Samsung Electro-Mechanics Co Ltd | Multilayer wiring board and method of manufacturing the same |
| JP2016008946A (en) * | 2014-06-26 | 2016-01-18 | 京セラ株式会社 | Wiring board, temperature sensing element, and temperature sensing device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6292091B1 (en) | Resistor and method of adjusting resistance of the same | |
| JPS60192304A (en) | Chip resistor | |
| JPH04297086A (en) | Hybrid integrated circuit | |
| JPH07106759A (en) | Thin-film multilayered substrate | |
| JPS6041859B2 (en) | semiconductor container | |
| JPH02126528A (en) | Semiconductor integrated circuit | |
| JPH0730242A (en) | Thin-film circuit substrate | |
| JPS63253659A (en) | Thick-film hybrid integrated circuit device | |
| JP2006019323A (en) | Resistance composition, chip resistor and their manufacturing method | |
| JP2581253B2 (en) | Hybrid integrated circuit board | |
| JPH0728060B2 (en) | Magnetic resistance element | |
| JPH02288290A (en) | Hybrid integrated circuit | |
| JPS62276801A (en) | Hybrid integrated circuit device | |
| JPH0134337Y2 (en) | ||
| JPH04174589A (en) | Substrate for thick-film hybrid ic | |
| JP2003078227A (en) | Thick film circuit board | |
| JPS6336641Y2 (en) | ||
| JPH0581059B2 (en) | ||
| JPH0553285B2 (en) | ||
| GB2136206A (en) | Fused ceramic capacitor | |
| JPS6362301A (en) | Thin film integrated circuit | |
| JPS63169058A (en) | Thin film integrated circuit | |
| JP2904853B2 (en) | Laser trimming protection member | |
| JPS5680152A (en) | Thin-film type integrated circuit device | |
| JP2001144400A (en) | Resistance structure of wiring board |