JPH0428249A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0428249A JPH0428249A JP13321590A JP13321590A JPH0428249A JP H0428249 A JPH0428249 A JP H0428249A JP 13321590 A JP13321590 A JP 13321590A JP 13321590 A JP13321590 A JP 13321590A JP H0428249 A JPH0428249 A JP H0428249A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- wiring
- silicon film
- fusing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000010438 heat treatment Methods 0.000 claims abstract description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 64
- 239000000758 substrate Substances 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- 229910052782 aluminium Inorganic materials 0.000 description 13
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012216 screening Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に冗長ビットにつながる
プログラマブル素子を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a programmable element connected to a redundant bit.
近年の半導体装置、特に半導体記憶装置では大容量化が
進められているが、チップ当たりの記憶容量が増加する
のに伴い製造歩留りを実用的な水準以上に保持すること
が次第に困難になりつつある。この歩留り低下は、全記
憶容量のうちの僅かに数ビットの記憶素子が動作してい
ないことが原因となる場合が多く、このような不良を救
済して歩留りの向上を図るために装置の一部に冗長ビッ
トおよびプログラマブル素子を設け、このプログラマブ
ル素子を例えば断線させることで不良ビットを冗長ビッ
トに切り替えるようにした技術が採用されている。In recent years, the capacity of semiconductor devices, especially semiconductor memory devices, has been increasing, but as the storage capacity per chip increases, it is becoming increasingly difficult to maintain manufacturing yields above a practical level. . This decrease in yield is often caused by the fact that only a few bits of memory elements out of the total memory capacity are not operating. A technique has been adopted in which a redundant bit and a programmable element are provided in a section, and a defective bit is switched to a redundant bit by, for example, disconnecting the programmable element.
例えば、第５図にはこの種の冗長ビットにつながるプロ
グラマブル素子を示しており、半導体基板１に形成する
アルミニウム配線の一部を、多結晶シリコン膜５で構成
している。この多結晶シリコン膜５はその両端において
コンタクト８によりアルミニウム配線１０に電気接続さ
れている。For example, FIG. 5 shows a programmable element connected to this type of redundant bit, in which a part of the aluminum wiring formed on the semiconductor substrate 1 is made of a polycrystalline silicon film 5. This polycrystalline silicon film 5 is electrically connected to aluminum wiring 10 by contacts 8 at both ends thereof.
そして、不良救済時には、このアルミニウム配線１０を
通して多結晶シリコン膜５に過電流を通流させることで
、多結晶シリコン膜５の抵抗によって発生される熱によ
り多結晶シリコン膜５自身が溶断されることになる。Then, when repairing a defect, by passing an overcurrent through the polycrystalline silicon film 5 through this aluminum wiring 10, the polycrystalline silicon film 5 itself is fused due to the heat generated by the resistance of the polycrystalline silicon film 5. become.
なお、この他にもレーザにより配線一部を断線させるよ
うにしたプログラマブル素子も提案されているが、ここ
ではその説明は省略する。In addition, a programmable element in which a portion of the wiring is disconnected using a laser has also been proposed, but a description thereof will be omitted here.
このような多結晶シリコン膜５をプログラマブル素子と
する半導体装置では、不良救済時に多結晶シリコン膜５
に電流を流して溶断を行っているが、実際には多結晶シ
リコン膜５において発生された熱の殆ど（９９，９％）
は周辺に放散され、多結晶シリコン膜５を溶断する熱と
して有効に作用していない。このため、溶断するのに必
要な熱量を発生させるためには、極めて大きな電力を長
時間にわたって供給する必要がある。この不良救済は通
常半導体装置の選別試験時等に行われるが、このように
長時間にわたって電流を供給しなげればならないために
、選別スループットが低下されるという問題が生じてい
る。In a semiconductor device using such a polycrystalline silicon film 5 as a programmable element, the polycrystalline silicon film 5 is
However, in reality, most of the heat generated in the polycrystalline silicon film 5 (99.9%)
is dissipated to the periphery and does not effectively act as heat to melt down the polycrystalline silicon film 5. Therefore, in order to generate the amount of heat necessary for fusing, it is necessary to supply an extremely large amount of electric power over a long period of time. This defect relief is normally performed during a screening test of semiconductor devices, but since current must be supplied for such a long period of time, a problem arises in that the screening throughput is reduced.
また、従来のプログラマブル素子では、多結晶シリコン
膜５のいずれの箇所で溶断されるかが特定されないため
、多結晶シリコン膜５が延設される領域にはこれと交差
して他の配線を配置することができず、配線の自由度を
低下させるという問題もある。In addition, in conventional programmable elements, since it is not specified at which point on the polycrystalline silicon film 5 the polycrystalline silicon film 5 is fused, other wiring is placed in the region where the polycrystalline silicon film 5 is extended to intersect therewith. There is also the problem that the degree of freedom in wiring is reduced.
本発明の目的は、プログラマブル素子の溶断を容易に行
い、かつ配線の自由度を高めることを可能にした半導体
装置を提供することにある。An object of the present invention is to provide a semiconductor device in which programmable elements can be easily blown out and wiring can be more flexible.
本発明の半導体装置は、冗長回路につながるプログラマ
ブル素子としての溶断用配線に交差配置される加熱用配
線を設け、この加熱用配線への通電によって溶断用配線
の一部を加熱するように構成している。The semiconductor device of the present invention is configured such that a heating wiring is provided to intersect with the fusing wiring as a programmable element connected to a redundant circuit, and a part of the fusing wiring is heated by applying current to the heating wiring. ing.
本発明によれば、加熱用配線に通電して発生される熱に
より溶断用配線の一部を加熱することにより、溶断用配
線の特定箇所における熱量を高め、この部分ににおいて
溶断用配線を迅速に溶断することが可能となる。According to the present invention, by heating a part of the fusing wiring with the heat generated when the heating wiring is energized, the amount of heat at a specific point of the fusing wiring is increased, and the fusing wiring is quickly installed in this part. This makes it possible to melt the material.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１実施例を示す図であり、同図（ａ
）は平面図、同図（ｂ）はそのＡ−Ａ線に沿う断面図で
ある。図において、１は半導体基板であり、図示しない
領域に記憶素子を形成しである。この半導体基板１の表
面に設けた絶縁膜２上には、０．２μｍの厚さの加熱用
多結晶シリコン膜３を所要パターンに形成している。こ
の加熱用多結晶シリコン膜３上にはＰＳＧ等の第２の絶
縁膜４を０．１μｍの厚さに形成し、この上にプログラ
マブル素子としての溶断用多結晶シリコン膜５を所要パ
ターンにかつ前記加熱用多結晶シリコン膜３と交差する
ように形成する。この溶断用多結晶シリコン膜５上には
０．５μｍの厚さのＰＳＧかなる第３の絶縁膜６を形成
する。しかる上で、前記第２の絶縁膜４および第３の絶
縁膜６にそれぞれコンタクトホール７．８を開設し、こ
のコンタクトホール７．８を通して加熱用多結晶シリコ
ン膜３と溶断用多結晶シリコン膜５にそれぞれアルミニ
ウム配線９，１０を接続する。FIG. 1 is a diagram showing a first embodiment of the present invention, and FIG.
) is a plan view, and figure (b) is a sectional view taken along the line A-A. In the figure, 1 is a semiconductor substrate, on which a memory element is formed in an area not shown. On an insulating film 2 provided on the surface of this semiconductor substrate 1, a polycrystalline silicon film 3 for heating with a thickness of 0.2 μm is formed in a desired pattern. On this polycrystalline silicon film 3 for heating, a second insulating film 4 such as PSG is formed to a thickness of 0.1 μm, and on this, a polycrystalline silicon film 5 for fusing as a programmable element is formed in a desired pattern. It is formed to intersect with the heating polycrystalline silicon film 3. A third insulating film 6 made of PSG and having a thickness of 0.5 μm is formed on this polycrystalline silicon film 5 for fusing. Then, contact holes 7.8 are formed in the second insulating film 4 and the third insulating film 6, respectively, and the polycrystalline silicon film 3 for heating and the polycrystalline silicon film for fusing are connected through the contact holes 7.8. 5 are connected to aluminum wirings 9 and 10, respectively.
ここで、前記溶断用多結晶シリコン膜５の幅寸法は溶断
され易いように可及的に細くし、加熱用多結晶シリコン
膜３の幅寸法は可及的に太くしている。Here, the width of the polycrystalline silicon film 5 for melting is made as thin as possible so that it can be easily cut by melting, and the width of the polycrystalline silicon film 3 for heating is made as thick as possible.
この構成によれば、半導体装置の不良救済に際しては、
アルミニウム配線９を通して加熱用多結晶シリジン膜３
に電流を通流すれば、該加熱用多結晶シリコン膜３で発
生される熱によって溶断用多結晶シリコン膜５の交差部
、ここでは中央部が加熱される。これと同時に、溶断用
多結晶シリコン膜５に通電を行えば、溶断用多結晶シリ
コン膜５自身が発生する熱が加えられ、これらの熱によ
って溶断用多結晶シリコン膜５の溶断が可能となる。こ
の場合、溶断用多結晶シリコン膜５の溶断箇所は加熱用
多結晶シリコン膜３と交差されている箇所となることは
言うまでもない。According to this configuration, when repairing a defective semiconductor device,
Polycrystalline silidine film 3 for heating is passed through aluminum wiring 9
When a current is passed through the heating polycrystalline silicon film 3, the intersection of the fusing polycrystalline silicon film 5, here the central part, is heated by the heat generated in the heating polycrystalline silicon film 3. At the same time, if the polycrystalline silicon film 5 for fusing is energized, the heat generated by the polycrystalline silicon film 5 itself for fusing is applied, and the polycrystalline silicon film 5 for fusing can be fused by this heat. . In this case, it goes without saying that the melting point of the polycrystalline silicon film 5 for melting is the part where the polycrystalline silicon film 3 for heating intersects.
したがって、この半導体装置では、加熱用多結晶シリコ
ン膜３と溶断用多結晶シリコン膜５に同時に電流を通流
し、それぞれで発生される熱により溶断用多結晶シリコ
ン膜５を溶断するため、極めて短い時間で溶断を行うこ
とができ、選別スル−プント等を向上することができる
。Therefore, in this semiconductor device, current is passed through the heating polycrystalline silicon film 3 and the fusing polycrystalline silicon film 5 at the same time, and the heat generated in each fuses the fusing polycrystalline silicon film 5, so that the current is extremely short. Cutting can be done in a short amount of time, and the sorting throughput can be improved.
また、溶断用多結晶シリコン膜５は溶断箇所が特定され
るため、他の箇所において他の配線を交差配置すること
が可能となり、配線の自由度を向上させることができる
。Further, since the melting point of the polycrystalline silicon film 5 for blowing is specified, it becomes possible to cross-arrange other wires at other points, and the degree of freedom of wiring can be improved.
第２図は本発明の第２実施例の平面図であり、第１実施
例と同一部分には同一符号を付しである。FIG. 2 is a plan view of a second embodiment of the present invention, in which the same parts as in the first embodiment are given the same reference numerals.
この実施例では、加熱用多結晶シリコン膜３の幅寸法を
溶断用多結晶シリコン膜５の幅寸法に比較して十分に太
くする一方で、加熱用多結晶シリコン族３と溶断用多結
晶シリコン膜５に接続されるアルミニウム配線９．１０
の一部をアルミニウム配線１０で共用化し、電流供給ラ
インを共通にしている。In this embodiment, while the width dimension of the heating polycrystalline silicon film 3 is made sufficiently thicker than the width dimension of the fusing polycrystalline silicon film 5, the heating polycrystalline silicon group 3 and the fusing polycrystalline silicon Aluminum wiring 9.10 connected to membrane 5
A part of the aluminum wiring 10 is used in common to provide a common current supply line.
この場合には加熱用多結晶シリコン膜３と溶断用多結晶
シリコン膜５に同時に同じ電流を通流させて溶断用多結
晶シリコン膜５の溶断を行うことになる。このように同
じ電流を通流しても、加熱用多結晶シリコン膜３は幅寸
法を大きくして耐熱性を高めているため、自身が溶断さ
れることばない。これにより、アルミニウム配線の簡略
化を図ることができる。In this case, the same current is made to flow through the heating polycrystalline silicon film 3 and the fusing polycrystalline silicon film 5 at the same time to blow out the fusing polycrystalline silicon film 5. Even when the same current is passed through the heating polycrystalline silicon film 3, the heating polycrystalline silicon film 3 is not blown out because its width is increased to improve its heat resistance. Thereby, the aluminum wiring can be simplified.
第３図は本発明の第３実施例を示す平面図である。この
実施例では、溶断用多結晶シリコン膜５の上層にさらに
第３の絶縁膜６を挟んで第２の加熱用多結晶シリコン膜
１１を形成し、その両端をコンタクトボール１２を介し
てアルミニウム配線１３に接続している。また、下層の
加熱用多結晶シリコン膜３と第２の加熱用多結晶シリコ
ン膜１１とはそれぞれ平面形状を逆向きの７字型に形成
し、それぞれの中間部で溶断用多結晶シリコン膜５の中
央部分を上下方向に挟むように配置している。FIG. 3 is a plan view showing a third embodiment of the present invention. In this embodiment, a second polycrystalline silicon film 11 for heating is formed on the polycrystalline silicon film 5 for fusing with a third insulating film 6 interposed therebetween, and aluminum wiring is connected to both ends of the polycrystalline silicon film 11 via contact balls 12. It is connected to 13. Further, the lower polycrystalline silicon film 3 for heating and the second polycrystalline silicon film 11 for heating are each formed in a figure 7 shape with opposite directions in plan view, and the polycrystalline silicon film 5 for fusing is formed in the middle of each. They are arranged so that the central part of the is sandwiched between them in the vertical direction.
この構成によれば、加熱用多結晶シリコン膜３および第
２の加熱用多結晶シリコン膜１１にそれぞれ電流を通流
することで、溶断用多結晶シリコン膜５の中央部を上下
から加熱し、この部分における溶断用多結晶シリコン膜
５の溶断をさらに迅速に行うことが可能となる。According to this configuration, by passing current through the heating polycrystalline silicon film 3 and the second heating polycrystalline silicon film 11, the central portion of the fusing polycrystalline silicon film 5 is heated from above and below, The polycrystalline silicon film 5 for melting in this portion can be cut more quickly.
なお、第４図に示すように、下層の加熱用多結晶シリコ
ン膜３と上層の第２の加熱用多結晶シリコン膜１１とを
上下方向に重ねたパターンに形成し、コンタクトホール
７によって各多結晶シリコン膜３，１１をアルミニウム
配線９に共通に接続させてもよい。このようにすれば、
アルミニウム配線９を通して双方の加熱用多結晶シリコ
ン膜３゜１１に同時に通電を行うことができ、かつ溶断
用多結晶シリコン膜５の中央部分を上下方向からそれぞ
れ加熱させることができ、アルミニウム配線の簡略化を
図ることができる。As shown in FIG. 4, the lower heating polycrystalline silicon film 3 and the upper heating second polycrystalline silicon film 11 are formed in a vertically overlapping pattern, and each polycrystalline silicon film is The crystalline silicon films 3 and 11 may be commonly connected to the aluminum wiring 9. If you do this,
It is possible to energize both heating polycrystalline silicon films 3° 11 through the aluminum wiring 9 at the same time, and to heat the central portion of the fusing polycrystalline silicon film 5 from above and below, respectively, which simplifies the aluminum wiring. It is possible to aim for
なお、加熱用多結晶シリコン膜で構成した加熱用配線は
多結晶シリコン以外の素材で構成してもよい。Note that the heating wiring made of the heating polycrystalline silicon film may be made of a material other than polycrystalline silicon.
以上説明したように本発明は、プログラマブル素子とし
ての溶断用配線に交差配置した加熱用配線に通電するこ
とにより溶断用配線の一部を加熱するように構成してい
るので、溶断用配線を特定箇所において迅速に溶断する
ことが可能となり、スループットの向上および配線自由
度の向上を図ることができる。As explained above, the present invention is configured to heat a part of the fusing wiring by energizing the heating wiring arranged to intersect with the fusing wiring as a programmable element, so that the fusing wiring can be specified. It becomes possible to quickly melt the wire at a certain point, thereby improving throughput and wiring flexibility.
第１図は本発明の第１実施例を示し、同図（ａ）は平面
図、同図（ｂ）′はそのｌ−Ａ線に沿う断面図、第２図
は本発明の第２実施例の平面図、第３図は本発明の第３
実施例の平面図、第４図は第３実施例の変形例を示す平
面図、第５図は従来のプログラマブル素子の平面図であ
る。
１・・・半導体基板、２・・・絶縁膜、３・・・加熱用
多結晶シリコン膜、４・・・第２の絶縁膜、訃・・溶断
用多結晶シリコン膜、６・・・第３の絶縁膜、７，８・
・・コンタクトホール、９．ＩＯ・・・アルミニウム配
線、１１・・・第２の加熱用多結晶シリコン膜、１２・
・・コンタクトホール、１３・・・アルミニウム配線。
■
Ｕ）
のFIG. 1 shows a first embodiment of the present invention, FIG. 1A is a plan view, FIG. The plan view of the example, FIG. 3, is the third embodiment of the present invention.
FIG. 4 is a plan view showing a modification of the third embodiment, and FIG. 5 is a plan view of a conventional programmable element. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Polycrystalline silicon film for heating, 4... Second insulating film, 2... Polycrystalline silicon film for fusing, 6... Th. 3 insulating film, 7, 8.
...Contact hole, 9. IO...aluminum wiring, 11...second polycrystalline silicon film for heating, 12.
...Contact hole, 13...Aluminum wiring. ■ U) of
Claims (1)
し、該配線に通電することで前記溶断用配線を溶断する
ように構成した半導体装置において、前記溶断用配線と
交差配置される加熱用配線を設け、この加熱用配線への
通電によって前記溶断用配線の一部を加熱するように構
成したことを特徴とする半導体装置。1. In a semiconductor device configured such that a part of the wiring connected to a redundant circuit is made up of a fusing wiring, and the fusing wiring is fused by supplying current to the wiring, a heating device arranged to intersect with the fusing wiring 1. A semiconductor device, characterized in that a heating wiring is provided, and a part of the fusing wiring is heated by energizing the heating wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13321590A JP2913768B2 (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13321590A JP2913768B2 (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0428249A true JPH0428249A (en) | 1992-01-30 |
| JP2913768B2 JP2913768B2 (en) | 1999-06-28 |
Family
ID=15099421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13321590A Expired - Lifetime JP2913768B2 (en) | 1990-05-23 | 1990-05-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2913768B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0696812A1 (en) * | 1994-08-10 | 1996-02-14 | International Business Machines Corporation | Thermally activated noise immune fuse |
| WO2005119779A1 (en) * | 2004-06-03 | 2005-12-15 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and manufacturing method of the same |
| JP2007305939A (en) * | 2006-05-15 | 2007-11-22 | Nec Electronics Corp | Semiconductor device and method for blowing out electric fuse |
| US7714408B2 (en) | 2006-10-04 | 2010-05-11 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device and manufacturing method thereof |
| US7719872B2 (en) | 2005-12-28 | 2010-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Write-once nonvolatile memory with redundancy capability |
| US7782651B2 (en) | 2006-10-24 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including storage device and method for driving the same |
| US7994607B2 (en) | 2007-02-02 | 2011-08-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US8759946B2 (en) | 2006-11-17 | 2014-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US8981524B2 (en) | 2007-03-14 | 2015-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a plurality of antifuse memory cells |
-
1990
- 1990-05-23 JP JP13321590A patent/JP2913768B2/en not_active Expired - Lifetime
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0696812A1 (en) * | 1994-08-10 | 1996-02-14 | International Business Machines Corporation | Thermally activated noise immune fuse |
| WO2005119779A1 (en) * | 2004-06-03 | 2005-12-15 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and manufacturing method of the same |
| US8114719B2 (en) | 2004-06-03 | 2012-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Memory device and manufacturing method of the same |
| JP2011049593A (en) * | 2004-06-03 | 2011-03-10 | Semiconductor Energy Lab Co Ltd | Memory device and data writing method |
| US7719872B2 (en) | 2005-12-28 | 2010-05-18 | Semiconductor Energy Laboratory Co., Ltd. | Write-once nonvolatile memory with redundancy capability |
| JP2007305939A (en) * | 2006-05-15 | 2007-11-22 | Nec Electronics Corp | Semiconductor device and method for blowing out electric fuse |
| US8372730B2 (en) | 2006-05-15 | 2013-02-12 | Renesas Electronics Corporation | Method for cutting an electric fuse |
| US7714408B2 (en) | 2006-10-04 | 2010-05-11 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device and manufacturing method thereof |
| US8330249B2 (en) | 2006-10-04 | 2012-12-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device with driver circuit and memory element |
| US7782651B2 (en) | 2006-10-24 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including storage device and method for driving the same |
| US8274814B2 (en) | 2006-10-24 | 2012-09-25 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device including storage device and method for driving the same |
| US8687407B2 (en) | 2006-10-24 | 2014-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including storage device and method for driving the same |
| US8759946B2 (en) | 2006-11-17 | 2014-06-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US7994607B2 (en) | 2007-02-02 | 2011-08-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US8981524B2 (en) | 2007-03-14 | 2015-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a plurality of antifuse memory cells |
| US9356030B2 (en) | 2007-03-14 | 2016-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device having antifuse with semiconductor and insulating films as intermediate layer |
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| Publication number | Publication date |
|---|---|
| JP2913768B2 (en) | 1999-06-28 |
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