JPH04278714A - Igbt driving circuit - Google Patents
Igbt driving circuitInfo
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- JPH04278714A JPH04278714A JP3065696A JP6569691A JPH04278714A JP H04278714 A JPH04278714 A JP H04278714A JP 3065696 A JP3065696 A JP 3065696A JP 6569691 A JP6569691 A JP 6569691A JP H04278714 A JPH04278714 A JP H04278714A
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Abstract
Description
【０００１】［発明の目的］[Object of the invention]
【０００２】0002
【産業上の利用分野】本発明は、ＩＧＢＴ（インシュレ
ーテッド・ゲート・バイポーラ・トランジスタ）のスイ
ッチング特性を改善したＩＧＢＴ駆動回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IGBT (Insulated Gate Bipolar Transistor) drive circuit with improved switching characteristics.
【０００３】0003
【従来の技術】近年、新世代のパワースイッチング素子
としてＩＧＢＴが注目されている。このＩＧＢＴは、Ｍ
ＯＳＦＥＴの高入力インピーダンス特性・高速性とバイ
ポーラトランジスタの高伝導度（低飽和電圧）特性とを
両立させた素子で、その優れた特性を生かして、例えば
、低騒音インバータ、ＡＣサーボモータ駆動装置など、
高速素子が不可欠な装置への採用が拡大しつつある。2. Description of the Related Art In recent years, IGBTs have attracted attention as a new generation power switching element. This IGBT is M
It is a device that combines the high input impedance characteristics and high speed characteristics of an OSFET with the high conductivity (low saturation voltage) characteristics of a bipolar transistor.By taking advantage of its excellent characteristics, it can be used, for example, in low-noise inverters, AC servo motor drive devices, etc. ,
Their use in equipment that requires high-speed elements is expanding.
【０００４】このＩＧＢＴは、ゲートに図７に示す矩形
波状のゲート信号を与えることにより、そのゲート信号
の立ち上がりでオンし、立ち下がり（ゲート信号の遮断
）でターンオフするようになっている。By applying a rectangular waveform gate signal shown in FIG. 7 to the gate, this IGBT is turned on at the rising edge of the gate signal and turned off at the falling edge (blocking of the gate signal).
【０００５】[0005]
【発明が解決しようとする課題】ところで、将来的に、
ＩＧＢＴの利用度・有用性を大きく伸ばせるか否かは、
ＩＧＢＴの特長の１つであるスイッチングの高速性を更
に向上できるかどうかにかかっており、高速性が現在の
重要な技術的課題となっている。[Problem to be solved by the invention] By the way, in the future,
Whether or not the usage and usefulness of IGBT can be greatly increased depends on
This depends on whether high-speed switching, which is one of the features of IGBTs, can be further improved, and high-speed performance is currently an important technical issue.
【０００６】この技術的課題の背景には、ＩＧＢＴのコ
レクタ・エミッタ間電圧とターンオフ時間（スイッチン
グ特性）との間のいわゆるトレードオフの関係がある。
即ち、図５に示すように、ゲート電圧を十分に大きな値
Ｖｇｏにして、ＩＧＢＴが過飽和状態になっているとき
には、コレクタ・エミッタ間電圧は低い値Ｖｃｅｏ に
抑えられるが、この電圧Ｖｃｅｏ では、図６に示すよ
うに、入力容量（ゲート・エミッタ間の容量）が大きい
値Ｃｏ になるので、放電に時間がかかり、ターンオフ
時間が長くなってしまう。The background to this technical problem is the so-called trade-off relationship between the collector-emitter voltage and turn-off time (switching characteristics) of the IGBT. That is, as shown in FIG. 5, when the gate voltage is set to a sufficiently large value Vgo and the IGBT is in an oversaturated state, the collector-emitter voltage is suppressed to a low value Vceo. As shown in Fig. 6, since the input capacitance (capacitance between the gate and emitter) becomes a large value Co, it takes time to discharge and the turn-off time becomes long.
【０００７】一方、ゲート電圧を、例えば飽和状態を維
持する限界レベルＶｇ１（図５参照）まで低下させると
、コレクタ・エミッタ間電圧は過飽和時に比べて大幅に
上昇し、Ｖｃｅ１ という高い電圧になってしまい、損
失が増大するという欠点がある。その反面、コレクタ・
エミッタ間電圧と入力容量との間には、図６に示すよう
に、コレクタ・エミッタ間電圧が上昇するほど、入力容
量が低下して、充電電荷量も減り、ターンオフ時間が短
くなるという関係があるので、スイッチングの高速化に
はコレクタ・エミッタ間電圧を高くした方（即ちゲート
電圧を低くした方）が有利である。On the other hand, when the gate voltage is lowered, for example, to the limit level Vg1 (see FIG. 5) that maintains the saturation state, the collector-emitter voltage increases significantly compared to when it is oversaturated, reaching a high voltage of Vce1. This has the disadvantage of increasing losses. On the other hand, the collector
As shown in Figure 6, there is a relationship between the emitter voltage and the input capacitance: as the collector-emitter voltage increases, the input capacitance decreases, the amount of charge decreases, and the turn-off time shortens. Therefore, it is advantageous to increase the collector-emitter voltage (that is, decrease the gate voltage) to increase the switching speed.
【０００８】しかしながら、上述したように、コレクタ
・エミッタ間電圧が上昇するほど（即ちゲート電圧が低
くなるほど）、損失が増大して、効率が悪くなってしま
う欠点があり、これがスイッチングの高速化に大きな障
害となっていた。However, as mentioned above, there is a drawback that the higher the collector-emitter voltage (that is, the lower the gate voltage), the higher the loss and the lower the efficiency. This was a major obstacle.
【０００９】本発明はこの様な事情を考慮してなされた
もので、従ってその目的は、損失の増加を抑えつつ、Ｉ
ＧＢＴのターンオフ時間を短くできて、スイッチングを
高速化をできるＩＧＢＴ駆動回路を提供することにある
。[0009] The present invention has been made in consideration of such circumstances, and therefore, its purpose is to suppress the increase in loss while increasing the I.
An object of the present invention is to provide an IGBT drive circuit that can shorten the turn-off time of the GBT and speed up switching.
【００１０】［発明の構成］[Configuration of the invention]
【００１１】[0011]
【課題を解決するための手段】本発明のＩＧＢＴ駆動回
路は、ＩＧＢＴのゲートに、ＩＧＢＴのオン時間に相当
する時間幅のゲート信号を与えてＩＧＢＴをオン・オフ
させるものにおいて、前記ゲート信号の発生期間の最終
段階で、前記ＩＧＢＴが過飽和状態から抜け出すのに必
要な時間だけ前記ゲート信号の電圧レベルを飽和状態が
維持可能な最小レベルまで低下させるように構成したも
のである。Means for Solving the Problems The IGBT drive circuit of the present invention turns on and off the IGBT by applying a gate signal having a time width corresponding to the on time of the IGBT to the gate of the IGBT, wherein At the final stage of the generation period, the voltage level of the gate signal is lowered to the minimum level at which the saturation state can be maintained by the time required for the IGBT to come out of the oversaturation state.
【００１２】0012
【作用】上記手段によれば、ゲート信号の発生期間の最
終段階で、ＩＧＢＴが過飽和状態から抜け出すのに必要
な時間だけゲート信号の電圧レベル（ゲート電圧）を飽
和状態が維持可能な最小レベルまで低下させる。この様
に、ＩＧＢＴのターンオフの直前の段階で、ゲート信号
の電圧レベルが低下すれば、それに応じて、コレクタ・
エミッタ間電圧が上昇し（図５参照）、入力容量が低下
して（図６参照）、充電電荷量も減り、ターンオフ時間
が短くなる。[Operation] According to the above means, at the final stage of the gate signal generation period, the voltage level of the gate signal (gate voltage) is reduced to the minimum level at which the saturation state can be maintained for the time necessary for the IGBT to come out of the supersaturation state. lower. In this way, if the voltage level of the gate signal decreases just before the turn-off of the IGBT, the collector voltage level decreases accordingly.
The emitter voltage increases (see FIG. 5), the input capacitance decreases (see FIG. 6), the amount of charged charge also decreases, and the turn-off time becomes shorter.
【００１３】この場合、ターンオフの直前で、ゲート電
圧を低下させるだけであるから、ターンオン当初からゲ
ート電圧を低くする場合とは異なり、損失の増加が最小
限に抑えられて、効率の低下も極めて少なく、極めて実
用的である。In this case, since the gate voltage is only lowered immediately before turn-off, unlike the case where the gate voltage is lowered from the beginning of turn-on, the increase in loss is kept to a minimum and the drop in efficiency is also extremely low. It is very practical.
【００１４】[0014]
【実施例】以下、本発明の第１実施例を図１及び図２に
基づいて説明する。ＩＧＢＴ駆動回路Ａは、第１の信号
発生回路１、第２の信号発生回路２及びゲート信号波形
形成回路３とから構成される。そして、このゲート信号
波形形成回路３から出力されるゲート信号Ｓ３ がＩＧ
ＢＴ４のゲートＧに与えられ、このＩＧＢＴ４がターン
オンして負荷５が駆動される。Embodiment A first embodiment of the present invention will be described below with reference to FIGS. 1 and 2. The IGBT drive circuit A includes a first signal generation circuit 1, a second signal generation circuit 2, and a gate signal waveform forming circuit 3. Then, the gate signal S3 output from this gate signal waveform forming circuit 3 is
The signal is applied to the gate G of BT4, turns on IGBT4, and drives load 5.
【００１５】上記第１の信号発生回路１から出力される
第１の信号Ｓ１ は、図２（ａ）に示すように、矩形波
状であり、その電圧レベルＶｇｏがゲート信号Ｓ３ の
初期電圧レベルＶｇｏと同一になっている。また、第１
の信号Ｓ１ のパルス幅Ｔ１ は、ゲート信号Ｓ３ の
パルス幅Ｔ３ よりも、後述する第２の信号Ｓ２ のパ
ルス幅Ｔ２ 分だけ短く、即ちＴ１ ＝Ｔ３ −Ｔ２
に設定されている。そして、この第１の信号Ｓ１ の立
ち上がり時期は、ゲート信号Ｓ３ の立ち上がり時期と
同時である。The first signal S1 outputted from the first signal generating circuit 1 has a rectangular waveform as shown in FIG. 2(a), and its voltage level Vgo is equal to the initial voltage level Vgo of the gate signal S3. is the same as Also, the first
The pulse width T1 of the signal S1 is shorter than the pulse width T3 of the gate signal S3 by the pulse width T2 of the second signal S2, which will be described later, that is, T1 = T3 - T2.
is set to . The rising timing of this first signal S1 is the same as the rising timing of the gate signal S3.
【００１６】一方、第２の信号発生回路２から出力され
る第２の信号Ｓ２ は、図２（ｂ）に示すように、矩形
波状であり、その電圧レベルＶｇ１がゲート信号Ｓ３
の最終電圧レベルＶｇ１と同一になっている。また、第
２の信号Ｓ２ のパルス幅Ｔ２ は、ＩＧＢＴ４が過飽
和状態（Ｖｇｏ）から抜け出すのに必要な時間に設定さ
れている。そして、この第２の信号Ｓ２ の立ち上がり
時期は、第１の信号Ｓ１ の立ち下がり時期と同時であ
る。On the other hand, the second signal S2 outputted from the second signal generating circuit 2 has a rectangular waveform as shown in FIG. 2(b), and its voltage level Vg1 is equal to the gate signal S3.
The final voltage level Vg1 is the same as that of Vg1. Further, the pulse width T2 of the second signal S2 is set to the time required for the IGBT 4 to escape from the supersaturation state (Vgo). The rising timing of this second signal S2 is the same as the falling timing of the first signal S1.
【００１７】また、ゲート信号波形形成回路３は上述し
た第１の信号Ｓ１ と第２の信号Ｓ２とを重畳させてゲ
ート信号Ｓ３ を形成する。これにより、ゲート信号Ｓ
３ の発生期間Ｔ３ の最終段階で、ＩＧＢＴ４が過飽
和状態（Ｖｇｏ）から抜け出すのに必要な時間Ｔ２ だ
け、ゲート信号Ｓ３ の電圧レベル（ゲート電圧）を飽
和状態が維持可能な最小レベルＶｇ１まで低下させる構
成となっている。Furthermore, the gate signal waveform forming circuit 3 forms a gate signal S3 by superimposing the above-mentioned first signal S1 and second signal S2. As a result, the gate signal S
3, the voltage level (gate voltage) of the gate signal S3 is lowered to the minimum level Vg1 at which the saturation state can be maintained by the time T2 necessary for the IGBT 4 to escape from the supersaturation state (Vgo). The structure is as follows.
【００１８】上記構成によれば、ゲート信号Ｓ３ の発
生期間Ｔ３ の最終段階で、ＩＧＢＴ４が過飽和状態（
Ｖｇｏ）から抜け出すのに必要な時間Ｔ２ だけ、ゲー
ト信号Ｓ３ の電圧レベル（ゲート電圧）を飽和状態が
維持可能な最小レベルＶｇ１まで低下させる。これによ
り、ＩＧＢＴ４は、ターンオフの直前の段階で、ゲート
電圧が過飽和電圧ＶｇｏからＶｇ１へ抜け出してコレク
タ・エミッタ間電圧がＶｃｅｏ からＶｃｅ１へ上昇す
る（図５参照）。このコレクタ・エミッタ間電圧の上昇
により、図６に示すように、入力容量がＣｏ からＣ１
へ低下して、その入力容量の低下分に相当する量の電
荷が放電され、充電電荷量が減少する。この状態で、ゲ
ート信号Ｓ３が遮断されるので、従来のように過飽和状
態（Ｖｇｏ）から一気に遮断する場合に比して、放電が
速やかに行われて、ＩＧＢＴ４が速やかにターンオフす
るようになり、従来に比してターンオフ時間が短くなる
。According to the above configuration, at the final stage of the generation period T3 of the gate signal S3, the IGBT4 enters the supersaturated state (
The voltage level (gate voltage) of the gate signal S3 is lowered to the minimum level Vg1 at which the saturation state can be maintained by the time T2 required to escape from Vgo). As a result, in the IGBT 4, the gate voltage drops from the oversaturation voltage Vgo to Vg1 immediately before turn-off, and the collector-emitter voltage increases from Vceo to Vce1 (see FIG. 5). Due to this rise in collector-emitter voltage, the input capacitance increases from Co to C1, as shown in Figure 6.
The amount of charge corresponding to the decrease in input capacitance is discharged, and the amount of charged charge decreases. In this state, the gate signal S3 is cut off, so compared to the conventional case where the gate signal S3 is cut off all at once from the supersaturated state (Vgo), the discharge occurs quickly and the IGBT 4 is quickly turned off. The turn-off time is shorter than before.
【００１９】この場合、ターンオフの直前で、ゲート電
圧を低下させるだけであるから、ターンオン当初からゲ
ート電圧を低くする場合とは異なり、損失の増加が最小
限に抑えられて、効率の低下も極めて少なく、極めて実
用的である。In this case, since the gate voltage is only lowered immediately before turn-off, unlike the case where the gate voltage is lowered from the beginning of turn-on, the increase in loss is minimized and the drop in efficiency is also extremely low. It is very practical.
【００２０】尚、ゲート信号Ｓ３ の作り方は、上記第
１実施例に限定されず、図３や図４にに示す本発明の第
２実施例、第３実施例のようにしても良い。The method of generating the gate signal S3 is not limited to the first embodiment described above, but may be similar to the second and third embodiments of the present invention shown in FIGS. 3 and 4.
【００２１】即ち、図３に示す本発明の第２実施例では
、第１の信号発生回路１から出力される第１の信号Ｓ１
は、電圧レベルがＶｇｏの矩形波で、ゲート信号Ｓ３
の初期電圧レベルＶｇｏと等しい電圧レベルとなって
いる。
この第１の信号Ｓ１ は、パルス幅Ｔ３ がゲート信号
Ｓ３ のパルス幅Ｔ３ と同一で、また、立ち上がり時
期もゲート信号Ｓ３ の立ち上がり時期と同時である。That is, in the second embodiment of the present invention shown in FIG.
is a rectangular wave whose voltage level is Vgo, and the gate signal S3
The voltage level is equal to the initial voltage level Vgo of . The first signal S1 has a pulse width T3 that is the same as the pulse width T3 of the gate signal S3, and its rise time is also the same as the rise time of the gate signal S3.
【００２２】一方、第２の信号発生回路２から出力され
る第２の信号Ｓ２ は、−Ｖｇ２なる負の電圧レベルの
矩形波で、そのパルス幅Ｔ２ は、ＩＧＢＴ４が過飽和
状態（Ｖｇｏ）から抜け出すのに必要な時間に設定され
ている。この第２の信号Ｓ２ は、第１の信号Ｓ１ の
立ち上がりから（Ｔ３ −Ｔ２ ）秒後に出力されて、
ゲート信号波形形成回路３で第１の信号Ｓ１ と重畳さ
れ、ゲート信号Ｓ３ が形成される。On the other hand, the second signal S2 output from the second signal generating circuit 2 is a rectangular wave with a negative voltage level of -Vg2, and its pulse width T2 is such that the IGBT 4 comes out of the oversaturation state (Vgo). is set at the required time. This second signal S2 is output (T3 - T2) seconds after the rise of the first signal S1,
The gate signal waveform forming circuit 3 superimposes the signal on the first signal S1 to form a gate signal S3.
【００２３】この場合、第１及び第２の両信号Ｓ１ ，
Ｓ２ の重畳により、ゲート信号Ｓ３ の電圧レベルが
、ターンオフ直前のＴ２ 秒間は、Ｖｇｏ−Ｖｇ２に低
下することになる。従って、Ｖｇｏ−Ｖｇ２＝Ｖｇ１（
ここで、Ｖｇ１は飽和状態が維持可能な最小電圧）とな
るように、第２の信号Ｓ２ の電圧レベル（−Ｖｇ２）
を設定すれば、第１実施例と全く同じゲート信号Ｓ３
が得られる。In this case, both the first and second signals S1,
Due to the superposition of S2, the voltage level of the gate signal S3 drops to Vgo-Vg2 for T2 seconds immediately before turn-off. Therefore, Vgo-Vg2=Vg1(
Here, the voltage level (-Vg2) of the second signal S2 is set so that Vg1 is the minimum voltage that can maintain the saturation state.
is set, the gate signal S3 is exactly the same as in the first embodiment.
is obtained.
【００２４】また、図４に示す本発明の第３実施例では
、第１の信号発生回路１から出力される第１の信号Ｓ１
は、電圧レベルがＶｇ３の矩形波で、Ｖｇ１＋Ｖｇ３
＝Ｖｇｏとなるように、Ｖｇ３が設定されている。ここ
で、Ｖｇ１は飽和状態が維持可能な最小電圧であり、Ｖ
ｇｏはゲート信号Ｓ３ の初期電圧レベルである。そし
て、この第１の信号Ｓ１ は、立ち上がり時期がゲート
信号Ｓ３ の立ち上がり時期と同時で、パルス幅Ｔ１
がゲート信号Ｓ３ のパルス幅Ｔ３ よりもＴ２ だけ
短くなるように設定されている（Ｔ１ ＝Ｔ３ −Ｔ２
）。ここで、Ｔ２ は、ＩＧＢＴ４が過飽和状態（Ｖ
ｇｏ）から抜け出すのに必要な時間である。Further, in the third embodiment of the present invention shown in FIG. 4, the first signal S1 output from the first signal generating circuit 1
is a rectangular wave whose voltage level is Vg3, and Vg1+Vg3
Vg3 is set so that =Vgo. Here, Vg1 is the minimum voltage that can maintain the saturation state, and Vg1 is the minimum voltage that can maintain the saturation state, and
go is the initial voltage level of the gate signal S3. The rising timing of this first signal S1 is the same as the rising timing of the gate signal S3, and the pulse width T1
is set to be shorter than the pulse width T3 of the gate signal S3 by T2 (T1 = T3 - T2
). Here, T2 means that IGBT4 is in a supersaturated state (V
This is the time required to get out of (go).
【００２５】一方、第２の信号発生回路２から出力され
る第２の信号Ｓ２ は、電圧レベルがＶｇ１の矩形波で
、そのパルス幅Ｔ３ は、ゲート信号Ｓ３ のパルス幅
Ｔ３ と同一である。この第２の信号Ｓ２ は、第１の
信号Ｓ１ と同時に出力されて、ゲート信号波形形成回
路３で第１の信号Ｓ１ と重畳され、ゲート信号Ｓ３
が形成される。On the other hand, the second signal S2 outputted from the second signal generating circuit 2 is a rectangular wave with a voltage level of Vg1, and its pulse width T3 is the same as that of the gate signal S3. This second signal S2 is output simultaneously with the first signal S1, is superimposed on the first signal S1 in the gate signal waveform forming circuit 3, and is then output as the gate signal S3.
is formed.
【００２６】これら第１及び第２の両信号Ｓ１ ，Ｓ２
の重畳により、ゲート信号Ｓ３ は、立ち上がりから
Ｔ１ 秒間は、電圧レベルが、Ｖｇ１＋Ｖｇ３＝Ｖｇｏ
となり、この後、ターンオフ直前のＴ２秒間は、Ｖｇ１
に低下するので、第１実施例と全く同じゲート信号Ｓ３
が得られる。Both the first and second signals S1 and S2
Due to the superposition of the gate signal S3, the voltage level is Vg1+Vg3=Vgo
After this, for T2 seconds immediately before turn-off, Vg1
Therefore, the gate signal S3 is exactly the same as in the first embodiment.
is obtained.
【００２７】上記第１乃至第３の各実施例では、ゲート
信号Ｓ３ を形成するために、第１及び第２の両信号Ｓ
１ ，Ｓ２ を重畳させるようにしたが、これ以外の方
法でゲート信号Ｓ３ を形成するようにしても良いこと
は言うまでもない。In each of the first to third embodiments described above, both the first and second signals S are used to form the gate signal S3.
1 and S2 are superimposed, but it goes without saying that other methods may be used to form the gate signal S3.
【００２８】[0028]
【発明の効果】本発明は以上の説明から明らかなように
、ゲート信号の発生期間の最終段階で、ＩＧＢＴが過飽
和状態から抜け出すのに必要な時間だけ、ゲート信号の
電圧レベルを飽和状態が維持可能な最小レベルまで低下
させるようにしたので、ＩＧＢＴのターンオフの直前の
段階で、コレクタ・エミッタ間電圧を上昇させて、ター
ンオフ時間を短くすることができ、スイッチングを高速
化できると共に、ターンオン当初からゲート電圧を低く
する場合とは異なり、損失の増加が最小限に抑えられて
、効率の低下も極めて少なく、極めて実用的であるとい
う優れた効果を奏する。As is clear from the above description, the present invention maintains the voltage level of the gate signal in the saturated state for the time necessary for the IGBT to come out of the supersaturated state at the final stage of the gate signal generation period. Since the voltage is lowered to the minimum possible level, the collector-emitter voltage can be increased just before the IGBT turns off, shortening the turn-off time, speeding up switching, and increasing the voltage from the moment the IGBT is turned on. Unlike the case where the gate voltage is lowered, the increase in loss is suppressed to a minimum, the decrease in efficiency is extremely small, and the excellent effects are extremely practical.
【図１】本発明の第１実施例を示すブロック図FIG. 1 is a block diagram showing a first embodiment of the present invention.
【図２】
各信号の波形図[Figure 2]
Waveform diagram of each signal
【図３】本発明の第２実施例を示す各信号の波形図[Fig. 3] Waveform diagram of each signal showing the second embodiment of the present invention
【図
４】本発明の第３実施例を示す各信号の波形図[Fig. 4] Waveform diagram of each signal showing the third embodiment of the present invention
【図５】
ＩＧＢＴのゲート電圧とコレクタ・エミッタ間電圧との
関係を示す特性図[Figure 5]
Characteristic diagram showing the relationship between IGBT gate voltage and collector-emitter voltage
【図６】ＩＧＢＴのコレクタ・エミッタ間電圧と入力容
量との関係を示す特性図[Figure 6] Characteristic diagram showing the relationship between collector-emitter voltage and input capacitance of IGBT
【図７】従来のゲート信号の波形図[Figure 7] Waveform diagram of conventional gate signal
１は第１の信号発生回路、２は第２の信号発生回路、３
はゲート信号波形形成回路、４はＩＧＢＴ、５は負荷で
ある。1 is a first signal generation circuit, 2 is a second signal generation circuit, 3
1 is a gate signal waveform forming circuit, 4 is an IGBT, and 5 is a load.
Claims (1)
時間に相当する時間幅のゲート信号を与えてＩＧＢＴを
オン・オフさせるＩＧＢＴ駆動回路において、前記ゲー
ト信号の発生期間の最終段階で、前記ＩＧＢＴが過飽和
状態から抜け出すのに必要な時間だけ前記ゲート信号の
電圧レベルを飽和状態が維持可能な最小レベルまで低下
させるように構成したことを特徴とするＩＧＢＴ駆動回
路。1. In an IGBT drive circuit that turns on and off the IGBT by applying a gate signal having a time width corresponding to the on-time of the IGBT to the gate of the IGBT, the IGBT is turned on and off at the final stage of the generation period of the gate signal. An IGBT drive circuit characterized in that the voltage level of the gate signal is lowered to a minimum level at which a saturation state can be maintained by the time necessary to escape from a supersaturation state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3065696A JPH04278714A (en) | 1991-03-06 | 1991-03-06 | Igbt driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3065696A JPH04278714A (en) | 1991-03-06 | 1991-03-06 | Igbt driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04278714A true JPH04278714A (en) | 1992-10-05 |
Family
ID=13294436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3065696A Pending JPH04278714A (en) | 1991-03-06 | 1991-03-06 | Igbt driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04278714A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000232347A (en) * | 1999-02-08 | 2000-08-22 | Toshiba Corp | Gate circuit and gate circuit control method |
| JP2003229751A (en) * | 2002-02-06 | 2003-08-15 | Nissan Motor Co Ltd | Current control type semiconductor element driving circuit and current control type semiconductor element driving device |
| JP2005045590A (en) * | 2003-07-23 | 2005-02-17 | Mitsubishi Electric Corp | Semiconductor device |
| KR100627126B1 (en) * | 2004-03-19 | 2006-09-25 | 닛산 지도우샤 가부시키가이샤 | Drive circuit for voltage driven type semiconductor element |
| JP2012186998A (en) * | 2012-05-09 | 2012-09-27 | Mitsubishi Electric Corp | Gate drive circuit |
| US8610485B2 (en) | 2007-09-12 | 2013-12-17 | Mitsubishi Electric Corporation | Gate drive circuit |
-
1991
- 1991-03-06 JP JP3065696A patent/JPH04278714A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000232347A (en) * | 1999-02-08 | 2000-08-22 | Toshiba Corp | Gate circuit and gate circuit control method |
| JP2003229751A (en) * | 2002-02-06 | 2003-08-15 | Nissan Motor Co Ltd | Current control type semiconductor element driving circuit and current control type semiconductor element driving device |
| JP2005045590A (en) * | 2003-07-23 | 2005-02-17 | Mitsubishi Electric Corp | Semiconductor device |
| US7151401B2 (en) | 2003-07-23 | 2006-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor apparatus |
| KR100627126B1 (en) * | 2004-03-19 | 2006-09-25 | 닛산 지도우샤 가부시키가이샤 | Drive circuit for voltage driven type semiconductor element |
| US8610485B2 (en) | 2007-09-12 | 2013-12-17 | Mitsubishi Electric Corporation | Gate drive circuit |
| JP2012186998A (en) * | 2012-05-09 | 2012-09-27 | Mitsubishi Electric Corp | Gate drive circuit |
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