JPH0427707B2 - - Google Patents
Info
- Publication number
- JPH0427707B2 JPH0427707B2 JP55073519A JP7351980A JPH0427707B2 JP H0427707 B2 JPH0427707 B2 JP H0427707B2 JP 55073519 A JP55073519 A JP 55073519A JP 7351980 A JP7351980 A JP 7351980A JP H0427707 B2 JPH0427707 B2 JP H0427707B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- cmos
- region
- type
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 230000003071 parasitic effect Effects 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims 9
- 239000000758 substrate Substances 0.000 claims 9
- 238000009792 diffusion process Methods 0.000 claims 6
- 238000002955 isolation Methods 0.000 claims 6
- 230000015572 biosynthetic process Effects 0.000 claims 4
- 229910052698 phosphorus Inorganic materials 0.000 claims 3
- 239000011574 phosphorus Substances 0.000 claims 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims 2
- 229910052796 boron Inorganic materials 0.000 claims 2
- -1 Phosphorus ions Chemical class 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 230000000295 complement effect Effects 0.000 claims 1
- 238000007796 conventional method Methods 0.000 claims 1
- 230000005669 field effect Effects 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図ＡないしＧはBi−CMOSトランジスタ
の従来の製造方法の一例を工程順に示す断面図、
第２図ａないしｆはこの発明に係るBi−CMOS
トランジスタの製造方法の一実施例を工程順に示
す断面図、第３図と第４図はこの発明により製造
されるBi−CMOSトランジスタにおいて形成さ
れる寄生トランジスタの構造の概略を示す断面図
である。
６１……第１のマスク、７１……第２のマス
ク、８１……第３のマスク、９１……第４のマス
ク、１００……基体、１０２，１０３……埋込
層、１０４……Ｐ型半導体層（エピタキシヤル成
長層）、１０５……バイポーラ素子側のＮウエル、
１０６……CMOS素子側のＮウエル、１０７…
…ベース領域、１０８……ソース、１０９……ド
レイン、１１０……Ｐ型領域、１１１，１１２…
…チヤンネルストツパ、１１３……エミツタ領
域、１１４……ソース、１１５……ドレイン、１
１６……N+領域、１１７，１１９……ゲート
SiO2層、１１８，１２０……ゲート電極。
FIGS. 1A to 1G are cross-sectional views showing an example of a conventional manufacturing method of Bi-CMOS transistors in the order of steps;
Figures 2a to 2f are Bi-CMOS according to the present invention.
FIGS. 3 and 4 are cross-sectional views showing an example of a method for manufacturing a transistor in the order of steps, and FIGS. 3 and 4 are cross-sectional views schematically showing the structure of a parasitic transistor formed in a Bi-CMOS transistor manufactured according to the present invention. 61...First mask, 71...Second mask, 81...Third mask, 91...Fourth mask, 100...Base, 102, 103...Buried layer, 104...P type semiconductor layer (epitaxial growth layer), 105...N-well on the bipolar element side,
106...N-well on the CMOS element side, 107...
... Base region, 108 ... Source, 109 ... Drain, 110 ... P type region, 111, 112 ...
... Channel stopper, 113 ... Emitter region, 114 ... Source, 115 ... Drain, 1
16...N + area, 117,119...gate
SiO 2 layer, 118, 120...gate electrode.
Claims (1)
ジスタとCMOSトランジスタとを形成する半導
体集積回路装置の製造方法において、 第１のマスク６１を介して、第１導電型の半導
体にてなる基板１００上に第２導電型の不純物を
導入することにより少なくとも第１及び第２の２
つの埋込層１０２，１０３を形成する工程と、 上記基板及び上記第１及び第２埋込層の上に第
１導電型のエピタキシヤル層１０４を形成する工
程と、 第２のマスクを介して、上記第１埋込層上及び
第２埋込層の一部上の上記エピタキシヤル層内に
第２導電型の不純物を上記第１及び第２埋込層ま
で拡散し到達させることで、上記エピタキシヤル
層を介在させてバイポーラトランジスタ用の第２
導電型領域１０５と、CMOSトランジスタの第
２導電型のウエル１０６とを形成する工程と、 第３のマスクを介して、第１導電型の不純物を
導入することにより、上記バイポーラトランジス
タ用第２導電型領域内にベース領域１０７と、上
記CMOSトランジスタの第２導電型のウエル内
にソース及びドレイン領域１０８，１０９と、上
記CMOSトランジスタの第２導電型の上記ウエ
ルに隣接し上記第２埋込層上の上記エピタキシヤ
ル層１１０内にチヤンネルストツパ領域１１１，
１１２とを形成する工程と、 第４のマスクを介して、第２導電型の不純物を
導入することにより、上記バイポーラトランジス
タの上記ベース領域内にエミツタ領域１１３と、
上記バイポーラトランジスタ用第２導電型領域内
に電極とのオーミツクコンタクトを改善するため
の領域１１６と、上記チヤンネルストツパ領域の
内側に上記CMOSトランジスタのソース及びド
レイン領域１１４，１１５とを形成する工程と、 を備えたことを特徴とする半導体集積回路装置の
製造方法。 【特許請求の範囲】 この発明は半導体集積回路装置の製造方法に関
し、特に同一基板上にバイポーラトランジスタと
相補型電界効果トランジスタ（以下CMOSトラ
ンジスタという。）とを形成した、いわゆるBi−
CMOSトランジスタの製造方法に関する。 この種のBi−CMOSトランジスタの従来の製
造方法は第１図ＡないしＧに示す通りである。 即ち、 (A) Ｐ型シリコン基板１０に第１のマスク１１を
用いてN+型埋込層１２を拡散する。 (B) 基板１０上にＮ型のエピタキシヤル層１３を
成長させる。 (C) 開口２０を有する第２のマスク２１を用いて
Ｐ型拡散を行ない、バイポーラ素子を分散する
ためのP+型の分離領域１４を形成する。 (D) 次いで、開口３０を有する第３のマスク３１
を用いてＮチヤンネルMOSトランジスタ用の
P-ウエル１５をＰ型拡散により形成する。こ
のとき分離領域１４のP+層も拡散が進み、基
板１０に到達し分離が完成する。 (E) 次いで第４のマスク４１を用いてバイポーラ
素子のベース領域１６、CMOS素子のＰチヤ
ンネルMOSトランジスタのソース・ドレイン
領域１７ａ，１７ｂ、ＮチヤンネルMOSトラ
ンジスタのP+チヤンネルストツパ１８等を形
成するためのN+型拡散を行なう。 (F) その後第５のマスク５１を用いてバイポーラ
素子のエミツタ領域１９、CMOS素子のＮチ
ヤンネルMOSトランジスタのソース，ドレイ
ン領域２０ａ，２０ｂ、ＰチヤンネルMOSト
ランジスタのチヤンネルストツパ２２を形成す
るためのN+型拡散を行なう。 (G) そしてCMOS素子の各MOSトランジスタの
ゲートとなる部分にゲート酸化膜を形成し、コ
ンタクトホトリソン，Ａ配線等の工程を経て
Bi−CMOS構造が完成される。 上述のように従来の製造方法においては、バイ
ポーラ素子用の分離領域を形成するための工程
（第１図Ｃ）とウエルを形成するための工程（第
１図Ｄ）とを必要としており、また上記各工程に
別個のマスク２１と３１とを用意しなければなら
なかつた。 さらに、Bi−CMOSトランジスタにおいては、
寄生トランジスタのラツチアツプを防止する必要
があり、従来は、このラツチアツプを防止するた
め寄生トランジスタのエミツタ，コレクタ，ベー
ス各領域の濃度プロフアイルをパラメータに入れ
た各寄生トランジスタのスケールデイメンシヨン
を決定しなければならず設計的にも困難な問題を
含んでいた。 この発明は上述の事情に鑑みてなされたもの
で、Bi−CMOSトランジスタの製造方法におい
て、バイポーラトランジスタの分離とCMOSト
ランジスタのウエルの形成とを１つのマスクによ
つて１つの工程で行なうことにより、従来の製造
方法に比してマスク数と工程数とを低減できると
ともに寄生トランジスタによるラツチアツプを効
果的に防止できるBi−CMOSトランジスタの製
造方法を提供することを目的とするものである。 以下にこの発明の一実施例を図面とともに説明
する。 第２図ａないし、ｆは本発明の一実施例に係る
Bi−CMOSトランジスタの製造方法を工程順に
示すものである。 (a) たとえば「100」方位で1015／cm3の不純物濃
度を有するＰ型半導体にてなる基体１００に
SiO2膜にてなる第１のマスク６１の開口６２，
６３を介してリンを選択拡散して、たとえば不
純物濃度３×1019／cm3のN+型埋込層１０２，
１０３を形成する。 (b) 次にマスク６１を除去した後、基体１００上
にたとえばボロンを用いて５〜10×1014／cm3の
不純物濃度で、Ｐ型半導体層１０４を膜厚６〜
10μでエピタキシヤル成形法により形成する。 (c) このＰ型半導体層１０４に第２のマスク７１
を用いて開口７２，７３を介して、リンイオン
を60KeVで４×1012／cm3で注入し、さらにたと
えば15時間拡散して、埋込層１０２，１０３上
にバイポーラ素子側のＮウエル１０５，
CMOS側のＮウエル１０６を形成する。Ｎウ
エル１０５はバイポーラトランジスタのコレク
タ領域となる。 Ｎウエル１０５はエピタキシヤル成長層であ
るＰ型半導体層１０４によつて分離される。 (d) 次に第３のマスク８１の開口８２ａ，８２
ｂ，８２ｃ，８２ｄ，８２ｅを介して、ボロン
を用いて不純物濃度５〜８×1018／cm3のP+型の
半導体層を拡散により形成して、バイポーラ素
子側のＮウエル１０５にバイポーラトランジス
タのベース領域１０７を形成するとともに、
CMOSトランジスタ側のＮウエル１０６には
ＰチヤンネルMOSトランジスタのソース１０
８とドレイン１０９ならびにＮウエル１０６に
隣接したＰ型領域１１０には、この領域１１０
の表面の導電型が反転するのを防止するチヤン
ネルストツパ１１１，１１２を形成する。 (e) 次に第４のマスク９１の開口９２ａ，９２
ｂ，９２ｃ，９２ｄを介して、リンを用いて不
純物濃度1019／cm3のN+型半導体層を拡散によ
り形成して、バイポーラトランジスタのエミツ
タ領域１１３を形成するとともに、Ｐ型領域１
１０において、チヤンネルストツパ１１１，１
１２の内側にＮチヤンネルMOSトランジスタ
のソース１１４とドレイン１１５を形成する。
またバイポーラ素子側のＮウエル１０５には接
続電極とのオーミツクコンタクトを改善するた
めのN+領域１１６を形成する。 (f) その後公知の方法により、PMOSトランジ
スタ側のドレイン１０９とソース１０８に跨る
ゲートSiO2層１１７を形成して、その上にゲ
ート電極１１８を形成する一方、NMOSトラ
ンジスタ側のドレイン１１５とソース１１４と
の跨るゲートSiO2層１１９を形成して、その
上にゲート電極１２０を形成する。 さらに各MOSトランジスタのソースとドレイ
ンならびにバイポーラトランジスタのコレクタ，
ベース，エミツタに電極１２０ないし１２６を形
成する。 上述のようにして、Ｎウエル１０５にてなるコ
レクタとベース１０７とエミツタ１１３とによつ
てバイポーラトランジスタが構成され、また
SiO2層１１７をゲート絶縁膜、電極１１８をゲ
ート電極とし、ソース１０８，ドレイン１０９と
その間のＮ型領域をチヤンネルとするＰチヤンネ
ルMOSトランジスタおよびSiO2層１１９をゲー
ト絶縁膜、電極１２０をゲート電極とし、ソース
１１４とドレイン１１５とその間のＰ型領域をチ
ヤンネルとするＮチヤンネルMOSトランジスタ
が構成される。またバイポーラトランジスタはエ
ピタキシヤル成長層であるＰ型半導体層１０４に
よつて分離されている。 以上の説明から判るように、この発明によれば
Bi−CMOSトランジスタの製造方法において、
バイポーラ素子の分離とCMOSトランジスタ用
のウエルの形成とをただ１つのマスク（実施例で
は第２のマスク７１）を用いた１つの工程（第２
図ｃ）によつてなされる。これに対して従来の製
造方法においてはバイポーラ素子の分離領域の形
成とCMOSトランジスタのウエル形成は別個の
工程で行なわれ、それぞれ別個のマスク（前述の
例では第２のマスク２１と第３のマスク３１）が
必要であつた。 この比較から明らかなように、この発明によれ
ばBi−CMOSトランジスタの製造時に要するマ
スク数を従来の方法に比して少なくすることが出
来、工程も簡単となり、安価にかつ容易にBi−
CMOSトランジスタを製造出来る。 また、この発明によればCMOSトランジスタ
における、いわゆるラツチアツプを有効に防止す
ることが出来る。 即ちこの発明により製造されるCMOSトラン
ジスタにおいてはＮ−MOSのドレイン領域１１
４とＰ型のエピタキシヤル層１０４とN+埋込層
１０３とで形成される第１の寄生トランジスタの
断面図は第３図のようになり、そのベース領域は
エピタキシヤル層で形成されるために、この第１
の寄生トランジスタのhFEが小さくなり、またベ
ース巾W1も大きくなるのでさらにhFEが小さくな
り、ラツチアツプの防止に効果的である。 またPMOSのドレイン領域１０８とＮウエル
１０６とN+埋込層１０３とで形成される第２の
寄生トランジスタの断面図は第４図のようにな
り、そのベース領域にN+層が入つているのでhFE
は小さくなり、ラツチアツプが防止される。[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device in which at least a bipolar transistor and a CMOS transistor are formed on the same substrate, a substrate made of a semiconductor of a first conductivity type is removed through a first mask 61. By introducing a second conductivity type impurity onto 100, at least the first and second
a step of forming two buried layers 102 and 103; a step of forming an epitaxial layer 104 of a first conductivity type on the substrate and the first and second buried layers; , by diffusing a second conductivity type impurity into the epitaxial layer on the first buried layer and a part of the second buried layer to reach the first and second buried layers, A second layer for bipolar transistors with an intervening epitaxial layer.
The second conductive type for the bipolar transistor is formed by forming the conductive type region 105 and the second conductive type well 106 of the CMOS transistor, and introducing the first conductive type impurity through the third mask. a base region 107 in the type region, source and drain regions 108 and 109 in the well of the second conductivity type of the CMOS transistor, and the second buried layer adjacent to the well of the second conductivity type of the CMOS transistor. A channel stopper region 111 is provided in the upper epitaxial layer 110,
112, and introducing a second conductivity type impurity through a fourth mask, an emitter region 113 is formed in the base region of the bipolar transistor;
Step of forming a region 116 for improving ohmic contact with the electrode in the second conductivity type region for the bipolar transistor, and source and drain regions 114 and 115 of the CMOS transistor inside the channel stopper region. A method for manufacturing a semiconductor integrated circuit device, comprising: and. [Scope of Claims] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to a method for manufacturing a semiconductor integrated circuit device, in which a bipolar transistor and a complementary field effect transistor (hereinafter referred to as a CMOS transistor) are formed on the same substrate.
Related to a method for manufacturing a CMOS transistor. A conventional manufacturing method for this type of Bi-CMOS transistor is shown in FIGS. 1A to 1G. That is, (A) an N + type buried layer 12 is diffused into a P type silicon substrate 10 using a first mask 11; (B) An N-type epitaxial layer 13 is grown on the substrate 10. (C) P type diffusion is performed using a second mask 21 having an opening 20 to form a P + type isolation region 14 for dispersing bipolar elements. (D) Next, a third mask 31 having an opening 30
for N-channel MOS transistor using
A P - well 15 is formed by P-type diffusion. At this time, the P + layer in the isolation region 14 also diffuses and reaches the substrate 10, completing the isolation. (E) Next, using the fourth mask 41, the base region 16 of the bipolar element, the source/drain regions 17a and 17b of the P channel MOS transistor of the CMOS element, the P + channel stopper 18 of the N channel MOS transistor, etc. are formed. Perform N + type diffusion for (F) After that, the fifth mask 51 is used to form the emitter region 19 of the bipolar device, the source and drain regions 20a and 20b of the N-channel MOS transistor of the CMOS device, and the channel stopper 22 of the P-channel MOS transistor. Perform + type diffusion. (G) Then, a gate oxide film is formed on the part that will become the gate of each MOS transistor of the CMOS element, and after processes such as contact photolithography and A wiring, etc.
Bi-CMOS structure is completed. As mentioned above, the conventional manufacturing method requires a step for forming an isolation region for a bipolar element (FIG. 1C) and a step for forming a well (FIG. 1D). Separate masks 21 and 31 had to be prepared for each of the above steps. Furthermore, in Bi-CMOS transistors,
It is necessary to prevent latch-up of parasitic transistors. Conventionally, in order to prevent latch-up, the scale dimension of each parasitic transistor is determined using the concentration profiles of the emitter, collector, and base regions of the parasitic transistor as parameters. This also involved difficult design issues. This invention was made in view of the above-mentioned circumstances, and is a method for manufacturing a Bi-CMOS transistor, in which separation of bipolar transistors and formation of a well of a CMOS transistor are performed in one step using one mask. It is an object of the present invention to provide a method for manufacturing a Bi-CMOS transistor that can reduce the number of masks and steps compared to conventional manufacturing methods and can effectively prevent latch-up due to parasitic transistors. An embodiment of the present invention will be described below with reference to the drawings. Figures 2a to 2f relate to an embodiment of the present invention.
A method for manufacturing a Bi-CMOS transistor is shown in order of steps. (a) For example, a substrate 100 made of a P-type semiconductor having an impurity concentration of 10 15 /cm 3 in the “100” direction
The opening 62 of the first mask 61 made of SiO 2 film,
For example, by selectively diffusing phosphorus through the N + type buried layer 102 with an impurity concentration of 3×10 19 /cm 3 ,
103 is formed. (b) Next, after removing the mask 61, a P-type semiconductor layer 104 is formed on the substrate 100 using boron, for example, with an impurity concentration of 5 to 10×10 14 /cm 3 to a thickness of 6 to 10.
Formed by epitaxial molding method with a thickness of 10μ. (c) A second mask 71 is applied to this P-type semiconductor layer 104.
Phosphorus ions are injected at 4×10 12 /cm 3 at 60 KeV through the openings 72 and 73 using the same method, and are further diffused for, for example, 15 hours to form N wells 105 on the bipolar element side on the buried layers 102 and 103.
An N-well 106 on the CMOS side is formed. N-well 105 becomes the collector region of the bipolar transistor. N-well 105 is separated by P-type semiconductor layer 104, which is an epitaxially grown layer. (d) Next, the openings 82a and 82 of the third mask 81
A P + type semiconductor layer with an impurity concentration of 5 to 8×10 18 /cm 3 is formed by diffusion using boron through the N-well 105 on the bipolar element side through B, 82 c, 82 d, and 82 e. While forming the base region 107 of
The N well 106 on the CMOS transistor side has the source 10 of a P channel MOS transistor.
8 and the drain 109 as well as the P type region 110 adjacent to the N well 106.
Channel stoppers 111 and 112 are formed to prevent the conductivity type of the surface from being reversed. (e) Next, the openings 92a and 92 of the fourth mask 91
An N + -type semiconductor layer with an impurity concentration of 10 19 /cm 3 is formed using phosphorus via diffusion to form the emitter region 113 of the bipolar transistor, and the P-type region 1
10, the channel stopper 111,1
A source 114 and a drain 115 of an N-channel MOS transistor are formed inside the transistor 12.
Further, an N + region 116 is formed in the N well 105 on the bipolar element side to improve ohmic contact with the connection electrode. (f) Thereafter, by a known method, a gate SiO 2 layer 117 is formed spanning the drain 109 and source 108 on the PMOS transistor side, and a gate electrode 118 is formed thereon, while the drain 115 and source 114 on the NMOS transistor side are formed. A gate SiO 2 layer 119 is formed over the gate electrode 120, and a gate electrode 120 is formed thereon. Furthermore, the source and drain of each MOS transistor and the collector of the bipolar transistor,
Electrodes 120 to 126 are formed on the base and emitter. As described above, a bipolar transistor is constituted by the collector formed by the N-well 105, the base 107, and the emitter 113, and
A P-channel MOS transistor in which the SiO 2 layer 117 is a gate insulating film, the electrode 118 is a gate electrode, and the source 108, drain 109 and an N-type region therebetween is a channel, and the SiO 2 layer 119 is a gate insulating film, and the electrode 120 is a gate electrode. An N-channel MOS transistor is constructed in which the source 114, the drain 115, and the P-type region therebetween serve as a channel. Further, the bipolar transistors are separated by a P-type semiconductor layer 104, which is an epitaxially grown layer. As can be seen from the above explanation, according to this invention
In the manufacturing method of Bi-CMOS transistor,
Isolation of bipolar elements and formation of wells for CMOS transistors are performed in one process (second mask 71 in the embodiment) using only one mask (second mask 71 in the embodiment).
This is done according to figure c). In contrast, in conventional manufacturing methods, the formation of the isolation region of the bipolar element and the well formation of the CMOS transistor are performed in separate steps, using separate masks (in the above example, the second mask 21 and the third mask 21). 31) was necessary. As is clear from this comparison, according to the present invention, the number of masks required when manufacturing Bi-CMOS transistors can be reduced compared to the conventional method, the process is simple, and Bi-CMOS transistors can be manufactured easily and inexpensively.
Can manufacture CMOS transistors. Furthermore, according to the present invention, so-called latch-up in CMOS transistors can be effectively prevented. That is, in the CMOS transistor manufactured according to the present invention, the N-MOS drain region 11
The cross-sectional view of the first parasitic transistor formed by the P-type epitaxial layer 104 and the N + buried layer 103 is as shown in FIG. 3, and its base region is formed by the epitaxial layer. In this first
Since the h FE of the parasitic transistor becomes smaller and the base width W 1 also becomes larger, the h FE becomes further smaller, which is effective in preventing latch-up. The cross-sectional view of the second parasitic transistor formed by the PMOS drain region 108, N well 106, and N + buried layer 103 is as shown in Fig. 4, and the N + layer is included in the base region. So h FE
becomes smaller and latch-up is prevented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7351980A JPS56169359A (en) | 1980-05-30 | 1980-05-30 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7351980A JPS56169359A (en) | 1980-05-30 | 1980-05-30 | Semiconductor integrated circuit device |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58226204A Division JPS59188162A (en) | 1983-11-29 | 1983-11-29 | Semiconductor integrated circuit device |
| JP8545890A Division JPH0316166A (en) | 1990-03-31 | 1990-03-31 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56169359A JPS56169359A (en) | 1981-12-26 |
| JPH0427707B2 true JPH0427707B2 (en) | 1992-05-12 |
Family
ID=13520567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7351980A Granted JPS56169359A (en) | 1980-05-30 | 1980-05-30 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56169359A (en) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57206064A (en) * | 1981-06-15 | 1982-12-17 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| JPS57206063A (en) * | 1981-06-15 | 1982-12-17 | Toshiba Corp | Semiconductor substrate and manufacture therefor |
| JPS58170048A (en) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | Semiconductor device |
| JPS58182863A (en) * | 1982-04-21 | 1983-10-25 | Hitachi Ltd | Semiconductor device |
| JPS58225663A (en) * | 1982-06-23 | 1983-12-27 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6080267A (en) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
| JPH0622274B2 (en) * | 1983-11-02 | 1994-03-23 | 株式会社日立製作所 | Semiconductor integrated circuit device |
| JPS60101963A (en) * | 1983-11-08 | 1985-06-06 | Iwatsu Electric Co Ltd | Manufacture of complementary type filed effect transistor |
| JPS60218866A (en) * | 1984-04-13 | 1985-11-01 | Mitsubishi Electric Corp | Complementary mos semiconductor device |
| KR890004420B1 (en) * | 1986-11-04 | 1989-11-03 | 삼성반도체통신 주식회사 | Manufacturing method of bicmos device |
| JPS6325964A (en) * | 1987-02-13 | 1988-02-03 | Seiko Epson Corp | Cmos type semiconductor integrated circuit device |
| JP2689114B2 (en) * | 1987-05-30 | 1997-12-10 | 株式会社リコー | Method for manufacturing semiconductor integrated circuit device |
-
1980
- 1980-05-30 JP JP7351980A patent/JPS56169359A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56169359A (en) | 1981-12-26 |
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