JPH04271119A - Dry-etching equipment - Google Patents
Dry-etching equipmentInfo
- Publication number
- JPH04271119A JPH04271119A JP4782491A JP4782491A JPH04271119A JP H04271119 A JPH04271119 A JP H04271119A JP 4782491 A JP4782491 A JP 4782491A JP 4782491 A JP4782491 A JP 4782491A JP H04271119 A JPH04271119 A JP H04271119A
- Authority
- JP
- Japan
- Prior art keywords
- substrate sample
- ion sheath
- dry etching
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001312 dry etching Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 description 26
- 238000005530 etching Methods 0.000 description 19
- 239000007789 gas Substances 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000011109 contamination Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000001179 sorption measurement Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 239000002826 coolant Substances 0.000 description 1
- 239000000498 cooling water Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 230000003301 hydrolyzing effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
［発明の目的］ [Purpose of the invention]
【０００１】0001
【産業上の利用分野】この発明は、ドライエッチング装
置の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to improvements in dry etching equipment.
【０００２】0002
【従来の技術】半導体装置等の製造では、例えばＳｉ等
の半導体基板（ウエハ）上にＡｌ（アルミニューム）あ
るいはＡｌ合金（例えばＡｌ−Ｓｉ−Ｃｕ合金）材によ
る配線処理を施す工程がある。従来の配線加工は、基板
上に形成したＡｌ等の層をドライエッチング処理して行
われるが、従来のドライエッチングは、図５に示すよう
に、反応室１内の下部電極１１上に静電チャック電極１
２を介して基板試料２が載置され、反応ガス導入口１３
に接続されたガスボンベ３から供給の、例えばハロゲン
を含んだＣｌ２ やＳｉＣｌ４ 等の塩素系ガス雰囲気
中で行われる。１４は上部電極であって真空容器１５に
取付けられるとともに、絶縁体１６により電気的に絶縁
された下部電極１１との間に整合回路４１を介して高周
波（ＲＦ）電源４が接続される。2. Description of the Related Art In the manufacture of semiconductor devices, etc., there is a step of performing wiring processing using Al (aluminum) or an Al alloy (eg, Al-Si-Cu alloy) material on a semiconductor substrate (wafer) such as Si. Conventional wiring processing is performed by dry etching a layer such as Al formed on a substrate, but in conventional dry etching, as shown in FIG. Chuck electrode 1
A substrate sample 2 is placed through the reaction gas inlet 13.
The process is carried out in an atmosphere of a chlorine-based gas such as Cl2 or SiCl4 containing halogen, which is supplied from a gas cylinder 3 connected to the gas cylinder 3. Reference numeral 14 denotes an upper electrode, which is attached to the vacuum vessel 15, and a radio frequency (RF) power source 4 is connected between it and the lower electrode 11, which is electrically insulated by an insulator 16, via a matching circuit 41.
【０００３】真空容器１５の上部蓋の外側には、電磁石
または永久磁石による磁界発生装置５が設置されている
。磁界発生装置５は上部電極１４の表面付近に電極と平
行な磁界を形成し、上，下部電極１４，１１間で放電さ
せたときに、マグネトロン放電を起こさせ、高密度プラ
ズマを生成させるものである。[0003] A magnetic field generating device 5 using an electromagnet or a permanent magnet is installed outside the upper lid of the vacuum container 15 . The magnetic field generator 5 forms a magnetic field parallel to the surface of the upper electrode 14, and when discharge is caused between the upper and lower electrodes 14 and 11, a magnetron discharge is generated and high-density plasma is generated. be.
【０００４】なお、１７は夫々矢印Ｙ１方向への排気口
であって、図示しないターボ分子ポンプ等の排気ポンプ
に接続され反応室１内のガス圧力がエッチング時にほぼ
一定となるように制御される。[0004] Reference numerals 17 denote exhaust ports in the direction of arrow Y1, which are connected to exhaust pumps such as turbo molecular pumps (not shown) and are controlled so that the gas pressure within the reaction chamber 1 remains approximately constant during etching. .
【０００５】ドライエッチングの開始前の基板試料２は
、Ｓｉウエハー等の基板を下地としたＡｌ層上にフォト
レジストが形成され、Ａｌ層がエッチングされることに
よって、配線パターンが形成される。そこで、正テーパ
状の良好な異方性からなるエッチング形状は、境界領域
におけるエッチング作用とデポ（堆積）作用との競争反
応を利用しつつ形成されるが、それには基板試料２の温
度を制御してエッチング生成物を過飽和とし、エッチン
グ部の側壁に堆積を起こさせることによって保護膜を形
成し、側壁部のアンダーカットを防ぐようにしている。In the substrate sample 2 before the start of dry etching, a photoresist is formed on an Al layer with a substrate such as a Si wafer as a base, and a wiring pattern is formed by etching the Al layer. Therefore, an etched shape with good anisotropy in the form of a positive taper is formed by utilizing the competitive reaction between the etching action and the deposition action in the boundary region, but this requires controlling the temperature of the substrate sample 2. The etching product is supersaturated and deposited on the sidewall of the etched portion, thereby forming a protective film to prevent undercutting of the sidewall.
【０００６】ところで、図５に示すような従来のドライ
エッチング装置では、エッチング速度を早め枚葉処理速
度を高めるために、各上，下部電極１４，１１に印加す
るＲＦ電力を大とし、プラズマの密度を高めることが要
求される。しかしエッチング速度を早めると、反応室１
内には多くのＲＦ電流が流れて、基板試料２の温度は上
昇し、熱に弱いフォトレジスト層の変形は避け難いもの
となる。そこで、フォトレジストの変形を防ぎ、保護膜
形成による良好なエッチング壁を形成するために、下部
電極１１内部に配管１８により冷却水等の冷却媒体を矢
印Ｙ２方向に流して、基板試料２の温度上昇を押えると
同時に、下部電極１１をＡｌやＣｕ等で形成し、基板試
料２との間に良好な熱伝導が行われるように構成された
。基板試料２を下部電極１１上に密着させるのに、機械
的にチャックする方式もあるが、図６にも要部を拡大し
て示すような、静電気力を利用した静電チャック方式が
採用されている。静電チャックは、静電チャック電極１
２を下部電極１１と基板試料２との間に介在させたもの
で、静電チャック電極１２はＣｕ等の内部金属１２ａの
外側をポリイミド樹脂やセラミックで覆って構成される
。また、静電チャック電極１２の内部金属１２ａには図
示しない直流電源から５ＫＶ程度までの直流正電圧が供
給されている。従って、下部電極１４，１１間にプラズ
マが生成されると、そのプラズマを介して基板試料２と
上部電極１４との間が導通して零電位となるから、静電
チャック電極１２の内部金属１２ａと基板試料２との間
に直流高電圧が印加されて、静電的に互いに吸引チャッ
クされる。また、プラズマ形成によるドライエッチング
では、図６にも点線Ａで示すように基板試料２の形状に
沿い覆うように基板試料２上高さＨの位置に薄い空間電
荷の層、即ちプラズマの中の負の電位を有する物体の周
囲に陽イオンが集まってなるイオンシース（Ｉｏｎ
Ｓｈｅａｔｈ：イオン鞘）（Ａ）が形成され、基板試料
２はこのイオンシースに対し垂直な方向性を有してエッ
チングされる。イオンシース幅（高さＨ）は反応室１内
のガス圧等に関係し、ガス圧が低くなるに従って幅は大
きくなる。ところで、枚葉処理される試料基板２は搬入
出のため、図６に拡大して示すように、基板試料２の周
囲先端部は、静電チャック電極１２側から長さＬだけは
み出させ、下部電極１１面上にも高さｈの空隙が開くよ
うに載置され、基板試料２の静電吸着を阻害しないよう
に、また静電チャック電極１２の上面をプラズマから保
護するように構成されている。実際の長さＬ及び高さｈ
は２ｍｍ前後に設定されている。また、下部電極１１上
面及び静電チャック電極１２の側面をプラズマから保護
するために絶縁保護膜１９が被覆されているが、この絶
縁保護膜１９には、耐エッチング性の高い石英やアルミ
ナ、あるいは基板試料２を汚染することの少ない窒化シ
リコン、炭化シンコン等のセラミックスあるいはポリイ
ミド等の有機樹脂が使用される。By the way, in a conventional dry etching apparatus as shown in FIG. 5, in order to increase the etching speed and increase the single wafer processing speed, the RF power applied to each of the upper and lower electrodes 14 and 11 is increased, and the plasma is increased. Increased density is required. However, if the etching rate is increased, reaction chamber 1
A large amount of RF current flows inside the substrate sample 2, and the temperature of the substrate sample 2 rises, making it difficult to avoid deformation of the heat-sensitive photoresist layer. Therefore, in order to prevent deformation of the photoresist and form a good etching wall by forming a protective film, a cooling medium such as cooling water is flowed in the direction of the arrow Y2 through the pipe 18 inside the lower electrode 11, and the temperature of the substrate sample 2 is At the same time, the lower electrode 11 was formed of Al, Cu, or the like to suppress the rise, and was configured to have good heat conduction between it and the substrate sample 2. Although there is a mechanical chuck method to bring the substrate sample 2 into close contact with the lower electrode 11, an electrostatic chuck method using electrostatic force is adopted, as shown in FIG. 6 with an enlarged view of the main part. ing. The electrostatic chuck has an electrostatic chuck electrode 1
2 is interposed between the lower electrode 11 and the substrate sample 2, and the electrostatic chuck electrode 12 is constructed by covering the outside of an internal metal 12a such as Cu with polyimide resin or ceramic. Further, a DC positive voltage of up to about 5 KV is supplied to the internal metal 12a of the electrostatic chuck electrode 12 from a DC power source (not shown). Therefore, when plasma is generated between the lower electrodes 14 and 11, conduction occurs between the substrate sample 2 and the upper electrode 14 through the plasma, resulting in zero potential, so that the internal metal 12a of the electrostatic chuck electrode 12 A DC high voltage is applied between the substrate sample 2 and the substrate sample 2, and they are electrostatically attracted to each other and chucked. In addition, in dry etching by plasma formation, a thin space charge layer is formed at a height H above the substrate sample 2 so as to follow and cover the shape of the substrate sample 2, as shown by the dotted line A in FIG. An ion sheath (Ion) is made up of positive ions gathered around an object with negative potential.
An ion sheath (A) is formed, and the substrate sample 2 is etched in a direction perpendicular to this ion sheath. The ion sheath width (height H) is related to the gas pressure within the reaction chamber 1, and the width increases as the gas pressure decreases. By the way, since the sample substrate 2 to be single-wafer processed is carried in and out, as shown in an enlarged view in FIG. It is placed so that a gap of height h is opened also on the surface of the electrode 11, and is configured so as not to inhibit the electrostatic adsorption of the substrate sample 2 and to protect the upper surface of the electrostatic chuck electrode 12 from plasma. There is. Actual length L and height h
is set at around 2 mm. Further, an insulating protective film 19 is coated to protect the upper surface of the lower electrode 11 and the side surface of the electrostatic chuck electrode 12 from plasma. Ceramics such as silicon nitride and silicon carbide, or organic resins such as polyimide, which hardly contaminate the substrate sample 2, are used.
【０００７】しかしながら、上記構成のもとでエッチン
グが行われると、基板試料２加工上面のみならず周囲端
部の裏側にもエッチング生成物（デポ）が堆積する。そ
の堆積物は、基板試料２の表側でエッチング溝の内側壁
に堆積されるのと同質ではあるが、突出し部の外側に露
出して付着するから、基板試料２の搬送中に搬送装置等
と接触して脱落し、クリーンルーム内を汚染する欠点が
あった。また、その堆積物が空気中の水分と結合し、加
水解離する場合には、汚染片（パーティクル）となって
散乱拡大する欠点があった。However, when etching is performed under the above configuration, etching products (deposits) are deposited not only on the processed top surface of the substrate sample 2 but also on the back side of the peripheral edge. The deposit is of the same quality as that deposited on the inner wall of the etching groove on the front side of the substrate sample 2, but because it is exposed and attached to the outside of the protrusion, it is difficult to avoid contact with the transfer device etc. during the transfer of the substrate sample 2. It has the disadvantage that it comes into contact and falls off, contaminating the inside of the clean room. Furthermore, when the deposits combine with moisture in the air and undergo hydrolytic dissociation, they become contaminant particles (particles) that are scattered and spread.
【０００８】[0008]
【発明が解決しようとする課題】従来のドライエッチン
グ装置は、一方の電極上に載置した基板試料が、その電
極及びチャック部分からはみ出た部分の裏面に、エッチ
ング特有の堆積物が付着し、それが基板試料の搬送中等
に剥離して空間を汚染するという欠点があった。[Problems to be Solved by the Invention] In the conventional dry etching apparatus, deposits peculiar to etching adhere to the back surface of the part of the substrate sample placed on one electrode that protrudes from the electrode and the chuck part. This has the disadvantage that it peels off during transportation of the substrate sample and contaminates the space.
【０００９】この発明は、上記従来の欠点を解消し、エ
ッチングに際し、基板試料裏面への堆積物の付着を少な
くし、空間の汚染を少なくし得るドライエッチング装置
を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a dry etching apparatus which can eliminate the above-mentioned conventional drawbacks, reduce the amount of deposits attached to the back surface of a substrate sample during etching, and reduce contamination of the space.
【００１０】［発明の構成］[Configuration of the invention]
【００１１】[0011]
【課題を解決するための手段】この発明は、真空容器内
に第１及び第２の電極が対向配置され、かつこの両電極
者間に放電電力が供給されてプラズマを形成するドライ
エッチング装置において、前記第１の電極上に載置され
てエッチングされる基板試料の周囲先端の近傍は、その
先端部から前記プラズマによって基板試料表面上に誘起
されるイオンシース幅の少なくとも１／２の長さの範囲
内には前記基板試料以外の構造物が存在しないように構
成したことを特徴とする。[Means for Solving the Problems] The present invention provides a dry etching apparatus in which first and second electrodes are disposed facing each other in a vacuum container, and discharge power is supplied between the two electrodes to form plasma. , the vicinity of the peripheral tip of the substrate sample placed on the first electrode and etched has a length from the tip of at least 1/2 of the width of the ion sheath induced on the substrate sample surface by the plasma. The structure is characterized in that no structure other than the substrate sample exists within the range.
【００１２】0012
【作用】この発明によるドライエッチング装置は、イオ
ンシース（Ａ）からそのイオンシース幅Ｈの約１／２を
越える領域には、デポ（堆積）が生じないことに着目し
てなされたもので、基板試料の先端周囲は、その先端部
から前記プラズマによって基板試料表面に誘起されるイ
オンシース幅Ｈの少なくとも１／２の長さの範囲内に基
板試料以外の構造物が存在しないように構成した結果、
基板試料の裏側には、エッチング時の堆積が生ぜず、基
板搬送時等に堆積物が剥離して汚染源となるようなこと
がない。[Operation] The dry etching apparatus according to the present invention has been developed with the focus on the fact that no deposits are formed in a region exceeding about 1/2 of the ion sheath width H from the ion sheath (A). The area around the tip of the substrate sample was configured such that no structure other than the substrate sample existed within a length range of at least 1/2 of the ion sheath width H induced on the substrate sample surface by the plasma from the tip. result,
No deposits are formed on the back side of the substrate sample during etching, and no deposits are peeled off during substrate transportation and become a source of contamination.
【００１３】[0013]
【実施例】以下、この発明によるドライエッチング装置
の一実施例を図１及び図４を参照し、詳細に説明する。
なお、図５及び図６に示した従来の構成と同一構成には
同一符号を付して詳細な説明は省略する。即ち、図１に
示すように、真空容器１５からなる反応室１内には、プ
ラズマを形成するため下，上部電極１１，１４からなる
第１及び第２の電極が対向して配置され、下部電極１１
の上には、基板試料２が載置されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a dry etching apparatus according to the present invention will be described in detail below with reference to FIGS. 1 and 4. Components that are the same as the conventional configurations shown in FIGS. 5 and 6 are designated by the same reference numerals, and detailed description thereof will be omitted. That is, as shown in FIG. 1, in a reaction chamber 1 consisting of a vacuum vessel 15, first and second electrodes consisting of lower and upper electrodes 11 and 14 are disposed facing each other to form plasma. Electrode 11
A substrate sample 2 is placed on top of the substrate.
【００１４】半導体ウエハー等の基板試料２と上部電極
５との間は、静電チャックにより吸着された後も、ミク
ロ状態では、図２に示すように、夫々の面に凹凸がある
から、完全な密着状態にあるわけではない。そこで、こ
の実施例では実質的に密着状態とし良好な熱伝導率を保
持させるため、基板試料２と静電チャック電極１２との
間の間隙部２０に、吸排管６ａを介して、数トル（Ｔｏ
ｒｒ）程度のガスを導入させている。吸排管６ａには、
ガス導入装置６１及び排気装置６２が接続され、排気装
置６２は、基板試料２の裏面のガス圧力が真空容器１５
内の真空度に影響を与えない程度のレベルに保持するた
めの調整用である。Even after the substrate sample 2 such as a semiconductor wafer and the upper electrode 5 are adsorbed by the electrostatic chuck, in the micro state, as shown in FIG. They are not in close contact. Therefore, in this embodiment, in order to achieve a substantially close contact state and maintain good thermal conductivity, several torr To
rr) gas is introduced. In the suction and exhaust pipe 6a,
A gas introducing device 61 and an evacuation device 62 are connected, and the evacuation device 62 has a gas pressure on the back surface of the substrate sample 2 that is equal to or less than the vacuum container 15.
This is for adjustment to maintain a level that does not affect the degree of vacuum inside.
【００１５】ところで、基板試料２面の上に形成される
イオンシース（Ａ）は、その基板試料２及び下部電極１
１の表面上高さＨに膜状に形成され、エッチングはその
イオンシース（Ａ）に対し垂直方向に向かって行われる
。また、ドライエッチングでは、前述のようにエッチン
グとデポ（堆積）による保護膜形成とが同時に行われる
が、その競合状況はイオンシース幅Ｈに関係することが
わかった。即ち、図３はイオンシース幅Ｈが５ｍｍの場
合のデータであるが、イオンシース（Ａ）面から約Ｈ／
２の距離の２．５ｍｍを境界として、これを越える領域
ではデポジションレートが零オングストローム／分とな
ることを示している。このデポジションレートが零とな
る領域は、イオンシース幅Ｈの値いかんに拘らず、常に
ほぼイオンシース幅Ｈの１／２を越える領域であること
がわかった。By the way, the ion sheath (A) formed on the surface of the substrate sample 2 and the lower electrode 1
The ion sheath (A) is etched in a direction perpendicular to the ion sheath (A). Furthermore, in dry etching, etching and formation of a protective film by deposition are performed simultaneously as described above, and it has been found that the competitive situation is related to the ion sheath width H. In other words, although FIG. 3 shows data when the ion sheath width H is 5 mm, the distance from the ion sheath (A) surface to approximately H/
It is shown that the deposition rate is 0 angstroms/min in a region beyond the boundary of 2.5 mm, which is the distance of 2. It has been found that the region where this deposition rate becomes zero is always a region exceeding approximately 1/2 of the ion sheath width H, regardless of the value of the ion sheath width H.
【００１６】そこで、この発明は、図４に拡大して示す
ように、基板試料２の周囲先端部近傍は、イオンシース
幅Ｈの１／２以内の範囲（半径Ｄ）内には他の構造物が
存在しないように、絶縁保護膜１９から夫々半径Ｄを越
える距離Ｌ′及びｈ′離隔させ空間領域を設けるように
構成し、基板試料２の周囲先端部に対向する領域のイオ
ンシース（Ａ）の傾斜角度が急峻になるようにしたが、
その結果、基板試料２の周縁端部の裏側にはエッチング
中にデポ（堆積）の形成は見られなかった。その理由は
、恐らく基板試料２の裏側、即ち、はみだした部分の裏
側までイオンシース（Ａ）が回り込むことがなくとも、
イオンシース（Ａ）の描く曲線が傾斜し、イオンによる
基板試料２へのエッチングが増加したためと、基板試料
２が静電チャック電極１２からはみでた部分の面積が増
大し、その部分の基板試料２の温度上昇によって、デポ
の吸着確率が低下したことによると考えられる。これら
の条件が重なり、実質上デポの速度よりエッチング速度
が勝り、基板試料２の裏側にデポが生じないものと考え
られる。Therefore, in the present invention, as shown in an enlarged view in FIG. 4, there is no other structure in the vicinity of the peripheral tip of the substrate sample 2 within a range (radius D) within 1/2 of the ion sheath width H. In order to prevent the presence of objects, space regions are provided at distances L' and h' that exceed the radius D from the insulating protective film 19, respectively, and the ion sheath (A ) was made to have a steeper inclination angle, but
As a result, no deposits were observed on the back side of the peripheral edge of substrate sample 2 during etching. The reason for this is probably that even if the ion sheath (A) does not go around to the back side of the substrate sample 2, that is, the back side of the protruding part,
This is because the curve drawn by the ion sheath (A) is inclined, and the etching of the substrate sample 2 by ions increases, and the area of the portion of the substrate sample 2 protruding from the electrostatic chuck electrode 12 increases, and the substrate sample 2 at that portion increases. This is thought to be due to a decrease in the adsorption probability of the deposit due to the rise in temperature. It is considered that these conditions overlap, the etching rate substantially exceeds the deposition rate, and no deposit is formed on the back side of the substrate sample 2.
【００１７】以上のように、この発明によるエッチング
装置は、基板試料２の周縁先端部からイオンシース幅Ｈ
の１／２の範囲内には、基板試料２を除いて他の構造物
が存在しないようにした結果、基板試料２の周縁裏側に
はデポが生ぜず、基板搬送時等において、クリーンルー
ム等を汚染するような不具合は解消される。As described above, the etching apparatus according to the present invention has a width H of the ion sheath from the tip of the peripheral edge of the substrate sample 2.
As a result of ensuring that there are no other structures other than substrate sample 2 within the range of 1/2 of Problems that cause contamination will be resolved.
【００１８】[0018]
【発明の効果】この発明によるドライエッチング装置は
、エッチング過程において、基板周縁の裏側にデポを生
成することがないので、汚染する要因は解消され、半導
体ウエハ等、基板の製造効率の向上等に寄与するところ
大である。[Effects of the Invention] The dry etching apparatus according to the present invention does not generate deposits on the back side of the periphery of the substrate during the etching process, so contamination factors are eliminated and the efficiency of manufacturing substrates such as semiconductor wafers is improved. This is a great contribution.
【図１】この発明によるドライエッチング装置の一実施
例を示す構成断面図である。FIG. 1 is a cross-sectional view showing the structure of an embodiment of a dry etching apparatus according to the present invention.
【図２】図１に示す装置の静電チャック電極部の拡大断
面図である。FIG. 2 is an enlarged cross-sectional view of the electrostatic chuck electrode portion of the device shown in FIG. 1;
【図３】図１に示す装置でイオンシース面からの距離と
デポ形成レートとの関係を示す特性図である。3 is a characteristic diagram showing the relationship between the distance from the ion sheath surface and the deposit formation rate in the apparatus shown in FIG. 1. FIG.
【図４】図１に示す装置の要部拡大断面図である。FIG. 4 is an enlarged sectional view of a main part of the device shown in FIG. 1;
【図５】従来のドライエッチング装置を示す構成図であ
る。FIG. 5 is a configuration diagram showing a conventional dry etching apparatus.
【図６】図５に示す装置の要部拡大断面図である。FIG. 6 is an enlarged sectional view of a main part of the device shown in FIG. 5;
１…反応室 １１…下部電極 １２…静電チャック電極 １９…絶縁保護膜 ２…基板試料 Ａ…イオンシース 1...Reaction chamber 11...Lower electrode 12...Electrostatic chuck electrode 19...Insulating protective film 2...Substrate sample A...Ion sheath
Claims (1)
向配置され、かつこの両電極間に放電電力が供給されて
プラズマを形成するドライエッチング装置において、前
記第１の電極上に載置されてエッチングされる基板試料
の周囲先端近傍は、その先端部から前記プラズマによっ
て基板試料表面上に誘起されるイオンシース幅の少なく
とも１／２の長さの範囲内には前記基板試料以外の構造
物が存在しないように構成したことを特徴とするドライ
エッチング装置。1. In a dry etching apparatus in which first and second electrodes are disposed facing each other in a vacuum container, and discharge power is supplied between the two electrodes to form plasma, a dry etching device is provided that is placed on the first electrode. In the vicinity of the peripheral tip of the substrate sample to be etched, there is no other material other than the substrate sample within a length range of at least 1/2 of the width of the ion sheath induced on the substrate sample surface by the plasma from the tip. A dry etching apparatus characterized in that it is configured so that no structure exists.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3047824A JPH0828349B2 (en) | 1991-02-20 | 1991-02-20 | Dry etching equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3047824A JPH0828349B2 (en) | 1991-02-20 | 1991-02-20 | Dry etching equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04271119A true JPH04271119A (en) | 1992-09-28 |
| JPH0828349B2 JPH0828349B2 (en) | 1996-03-21 |
Family
ID=12786101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3047824A Expired - Fee Related JPH0828349B2 (en) | 1991-02-20 | 1991-02-20 | Dry etching equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828349B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11317391A (en) * | 1998-02-18 | 1999-11-16 | Sez Semiconductor Equip Zubehoer Fuer Die Halbleiterfertigung Ag | Apparatus for dry etching wafer and method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01200625A (en) * | 1988-02-05 | 1989-08-11 | Toshiba Corp | Semiconductor wafer processing equipment |
| JPH01251735A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Electrostatic chuck apparatus |
| JPH01310554A (en) * | 1988-06-09 | 1989-12-14 | Fuji Electric Co Ltd | Wafer holding mechanism of semiconductor wafer treating device |
| JPH0269956A (en) * | 1988-09-05 | 1990-03-08 | Toshiba Corp | Method and apparatus for electrostatically chucking |
-
1991
- 1991-02-20 JP JP3047824A patent/JPH0828349B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01200625A (en) * | 1988-02-05 | 1989-08-11 | Toshiba Corp | Semiconductor wafer processing equipment |
| JPH01251735A (en) * | 1988-03-31 | 1989-10-06 | Toshiba Corp | Electrostatic chuck apparatus |
| JPH01310554A (en) * | 1988-06-09 | 1989-12-14 | Fuji Electric Co Ltd | Wafer holding mechanism of semiconductor wafer treating device |
| JPH0269956A (en) * | 1988-09-05 | 1990-03-08 | Toshiba Corp | Method and apparatus for electrostatically chucking |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11317391A (en) * | 1998-02-18 | 1999-11-16 | Sez Semiconductor Equip Zubehoer Fuer Die Halbleiterfertigung Ag | Apparatus for dry etching wafer and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0828349B2 (en) | 1996-03-21 |
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