JPH04264767A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04264767A JPH04264767A JP3026004A JP2600491A JPH04264767A JP H04264767 A JPH04264767 A JP H04264767A JP 3026004 A JP3026004 A JP 3026004A JP 2600491 A JP2600491 A JP 2600491A JP H04264767 A JPH04264767 A JP H04264767A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode film
- cylindrical electrode
- spacer
- cylindrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 25
- 125000006850 spacer group Chemical group 0.000 claims description 33
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体装置とその製造方
法に係り、特にダイナミックＭＯＳメモリセルのキャパ
シタの構造と形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to the structure and method of forming a capacitor of a dynamic MOS memory cell.
【０００２】ダイナミックＭＯＳメモリ（以下、ＭＯＳ
ＤＲＡＭと略称する）は１個のＭＯＳセルと１個のキ
ャパシタから構成されているが、半導体装置の高集積化
に伴いセルが微細化するのに対して、キャパシタの容量
を出来るだけ大きくすることが望まれている。Dynamic MOS memory (hereinafter referred to as MOS
A DRAM (abbreviated as DRAM) consists of one MOS cell and one capacitor, but as semiconductor devices become more highly integrated, the cells become smaller, so it is important to increase the capacitance of the capacitor as much as possible. is desired.
【０００３】以上のような状況から微小な領域内に大容
量のキャパシタを形成することが可能な半導体装置及び
その製造方法が要望されている。Under the above circumstances, there is a need for a semiconductor device and a method for manufacturing the same that can form a large capacitance capacitor in a minute area.
【０００４】0004
【従来の技術】従来の半導体装置について図７により、
半導体装置の製造方法について図８により詳細に説明す
る。[Prior Art] Regarding a conventional semiconductor device, as shown in FIG.
A method for manufacturing a semiconductor device will be explained in detail with reference to FIG.
【０００５】ＭＯＳ ＤＲＡＭにおいてはキャパシタの
容量を増加するため、図７に示すような側断面図を有す
るスタックドキャパシタセル構造が採られており、フィ
ールド酸化膜２２で画定された半導体基板２１の表面に
ゲ−ト酸化膜２３を介してゲート電極２４を設け、その
両側の半導体基板２１にソース２５とドレイン２６とを
設け、その表面を被覆する絶縁膜２７の表面に下部電極
膜２８を形成しており、この下部電極膜２８を被覆する
キャパシタ絶縁膜２９を介して上部電極膜３０を被着形
成してキャパシタを形成している。In order to increase the capacitance of a capacitor in a MOS DRAM, a stacked capacitor cell structure having a side cross-sectional view as shown in FIG. A gate electrode 24 is provided through a gate oxide film 23, a source 25 and a drain 26 are provided on the semiconductor substrate 21 on both sides, and a lower electrode film 28 is formed on the surface of an insulating film 27 covering the surface. An upper electrode film 30 is deposited via a capacitor insulating film 29 covering the lower electrode film 28 to form a capacitor.
【０００６】このようなポリシリコンからなる下部電極
膜２８と上部電極膜３０が、シリコン酸化膜からなるキ
ャパシタ絶縁膜２９を介して対向する構造のキャパシタ
を備えたメモリセルは、スタックドキャパシタセル（ｓ
ｔａｃｋｅｄ ｃａｐａｃｉｔｏｒ ｃｅｌｌ）と称せ
られており、図８に示すような工程順に製造している。A memory cell equipped with a capacitor having such a structure in which the lower electrode film 28 and the upper electrode film 30 made of polysilicon face each other with the capacitor insulating film 29 made of a silicon oxide film interposed therebetween is called a stacked capacitor cell ( s
It is called a tacked capacitor cell) and is manufactured in the order of steps shown in FIG.
【０００７】まず、図８（ａ） に示すように、ｐ型の
半導体基板２１上にＬＯＣＯＳ法によつて選択的にフィ
ールド酸化膜２２を形成し、化学気相成長 （ＣＶＤ）
法によってゲ−ト酸化膜２３を介して導電性のポリシリ
コン膜からなるゲ−ト電極２４を形成し、イオン注入に
よりｎ型のソ−ス領域２５及びドレイン領域２６を形成
し、これらの表面にシリコン酸化膜からなる膜厚３００
０Å程度の絶縁膜２７を被着形成し、コンタクトホール
２７ａ を開口する。First, as shown in FIG. 8A, a field oxide film 22 is selectively formed on a p-type semiconductor substrate 21 by the LOCOS method, and then chemical vapor deposition (CVD) is performed.
A gate electrode 24 made of a conductive polysilicon film is formed by a method using a gate oxide film 23, and an n-type source region 25 and a drain region 26 are formed by ion implantation. The thickness of the silicon oxide film is 300 mm.
An insulating film 27 of about 0 Å is deposited and a contact hole 27a is opened.
【０００８】つぎに図８（ｂ） に示すように、この絶
縁膜２７の表面に導電性のポリシリコン膜をＣＶＤ法に
より被着形成し、パタ−ンニングしてキャパシタの下部
電極膜２８を形成する。Next, as shown in FIG. 8(b), a conductive polysilicon film is deposited on the surface of this insulating film 27 by the CVD method and patterned to form a lower electrode film 28 of the capacitor. do.
【０００９】ついで図８（ｃ） に示すように、この下
部電極膜２８の表面に膜厚５０〜１００ Åのシリコン
窒化膜からなるキャパシタ絶縁膜２９を被着形成し、そ
の表面に導電性のポリシリコン膜からなる上部電極膜３
０を被着形成し、キャパシタ絶縁膜２９と上部電極膜３
０とを同時にパタ−ンニングしてキャパシタを形成する
。Next, as shown in FIG. 8(c), a capacitor insulating film 29 made of a silicon nitride film with a thickness of 50 to 100 Å is deposited on the surface of this lower electrode film 28, and a conductive film is formed on the surface. Upper electrode film 3 made of polysilicon film
0 is deposited, and the capacitor insulating film 29 and the upper electrode film 3 are formed.
A capacitor is formed by patterning 0 and 0 at the same time.
【００１０】0010
【発明が解決しようとする課題】以上説明した従来の半
導体装置及びその製造方法においては、ＭＯＳ ＤＲＡ
Ｍのメモリセルが１６ＭＢ，６４ＭＢ となり極めて高
集積化されるのに伴なってメモリセルを形成する領域は
益々小さくなり、それに応じてキャパシタを形成する領
域も小さくなるため対向する電極の面積が小さくなり、
キャパシタの容量が不足してメモリ動作の信頼性が低下
するという問題点があった。[Problems to be Solved by the Invention] In the conventional semiconductor device and its manufacturing method described above, MOS DRA
As M memory cells become 16 MB and 64 MB and become extremely highly integrated, the area where memory cells are formed becomes smaller and smaller, and the area where capacitors are formed becomes smaller accordingly, so the area of opposing electrodes becomes smaller. Become,
There is a problem in that the reliability of memory operation decreases due to insufficient capacity of the capacitor.
【００１１】本発明は以上のような状況から、ＭＯＳ
ＤＲＡＭのキャパシタの容量を増大させることが可能と
なる半導体装置及びその製造方法の提供を目的としたも
のである。[0011] The present invention is based on the above-mentioned circumstances.
The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which make it possible to increase the capacitance of a DRAM capacitor.
【００１２】0012
【課題を解決するための手段】本発明の半導体装置は、
キャパシタ絶縁膜を介して下部電極と上部電極とが対向
するキャパシタを具備する半導体装置であって、この下
部電極が、下部電極膜と接続する単一または複数の円筒
型電極膜とから構成され、この上部電極が、前記円筒型
電極膜の表面を被覆するキャパシタ絶縁膜を介してこの
円筒型電極膜に対向して設けられてなるように構成する
。[Means for Solving the Problems] A semiconductor device of the present invention includes:
A semiconductor device comprising a capacitor in which a lower electrode and an upper electrode face each other with a capacitor insulating film interposed therebetween, the lower electrode comprising a single or plural cylindrical electrode films connected to the lower electrode film, The upper electrode is arranged to face the cylindrical electrode film with a capacitor insulating film covering the surface of the cylindrical electrode film interposed therebetween.
【００１３】本発明の半導体装置の製造方法は、半導体
基板上の絶縁膜の表面に形成した下部電極膜の表面に円
柱状の第１のスペーサ膜を形成する工程と、この第１の
スペーサ膜及びこの下部電極膜の表面に第１の円筒型電
極膜を被着形成する工程と、この第１の円筒型電極膜の
全表面に第２のスペーサ膜を被着形成した後、この第２
のスペーサ膜の異方性のエッチングを行ってこの第１の
円筒型電極膜の垂直部の側壁にサイドウォールを形成す
る工程と、このサイドウオール及びこの第１の円筒型電
極膜の全表面に第２の円筒型電極膜を被着形成し、この
第２の円筒型電極膜の全表面に第３のスペーサ膜を被着
形成した後、この第３のスペーサ膜の異方性のエッチン
グを行い、この第２の円筒型電極膜の垂直部の側壁にサ
イドウォールを形成する工程と、このサイドウオール及
びこの第２の円筒型電極膜の全表面に第３の円筒型電極
膜を被着形成した後、この絶縁膜が露出するまでこの下
部電極膜、第１の円筒型電極膜、第２の円筒型電極膜、
第３の円筒型電極膜の異方性のエッチングを行う工程と
、この第１のスペーサ膜、二つのサイドウォールをエッ
チングして除去する工程と、この絶縁膜、第１の円筒型
電極膜、第２の円筒型電極膜、第３の円筒型電極膜の表
面にキャパシタ絶縁膜を被着形成し、このキャパシタ絶
縁膜の表面に上部電極膜を被着形成する工程とを含むよ
うに構成する。A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a columnar first spacer film on the surface of a lower electrode film formed on the surface of an insulating film on a semiconductor substrate; and a step of depositing and forming a first cylindrical electrode film on the surface of this lower electrode film, and a step of depositing and forming a second spacer film on the entire surface of this first cylindrical electrode film;
a step of anisotropically etching the spacer film to form a sidewall on the vertical sidewall of the first cylindrical electrode film; After depositing a second cylindrical electrode film and depositing a third spacer film on the entire surface of the second cylindrical electrode film, the third spacer film is anisotropically etched. forming a sidewall on the vertical side wall of this second cylindrical electrode film, and depositing a third cylindrical electrode film on the entire surface of this sidewall and this second cylindrical electrode film. After forming, the lower electrode film, the first cylindrical electrode film, the second cylindrical electrode film,
a step of anisotropically etching the third cylindrical electrode film; a step of etching and removing the first spacer film and the two sidewalls; forming a capacitor insulating film on the surfaces of the second cylindrical electrode film and the third cylindrical electrode film, and forming an upper electrode film on the surface of the capacitor insulating film. .
【００１４】[0014]
【作用】即ち本発明においては半導体装置の下部電極を
、下部電極膜と接続する単一の円筒状または同心円の複
数の円筒型電極膜とから構成し、この下部電極の表面に
キャパシタ絶縁膜を介して上部電極膜を設ける構造にし
ており、このような構造の半導体装置を製造するために
、円筒型電極膜の表面に形成したスペーサ膜の異方性エ
ッチング処理を行って、これらの円筒型電極膜の側壁に
サイドウオールを形成する工程を複数回行い、最後に異
方性エッチングによりこれらの円筒型電極膜の上部を除
去した後、このサイドウォールをエッチングにより除去
し、このサイドウォールの除去部分の下部電極の表面に
キャパシタ絶縁膜を介して上部電極膜を被着形成するの
で、対向面積が広く、容量の大きなキャパシタを具備す
るＭＯＳ ＤＲＡＭのメモリセルを製造することが可能
となる。[Operation] That is, in the present invention, the lower electrode of a semiconductor device is composed of a single cylindrical electrode film or a plurality of concentric cylindrical electrode films connected to a lower electrode film, and a capacitor insulating film is formed on the surface of this lower electrode. In order to manufacture a semiconductor device with such a structure, an anisotropic etching process is performed on the spacer film formed on the surface of the cylindrical electrode film. The process of forming sidewalls on the sidewalls of the electrode films is performed multiple times, and finally, after removing the upper part of these cylindrical electrode films by anisotropic etching, this sidewall is removed by etching. Since the upper electrode film is deposited on the surface of the lower electrode of the portion through the capacitor insulating film, it is possible to manufacture a MOS DRAM memory cell having a large opposing area and a capacitor with a large capacity.
【００１５】[0015]
【実施例】以下、本発明の同心円状の３つの円筒型電極
膜からなる下部電極を形成する一実施例について図１〜
図６により詳細に説明する。[Example] An example of forming a lower electrode consisting of three concentric cylindrical electrode films according to the present invention will be described below with reference to FIGS.
This will be explained in detail with reference to FIG.
【００１６】図１は本発明の半導体装置のメモリセルの
構造を示す側断面図、図２〜図６は本発明による半導体
装置の製造方法の一実施例を工程順に示す側断面図であ
る。図１に示すようにフィールド酸化膜２で画定された
半導体基板１の表面にゲ−ト酸化膜３を介してゲート電
極４を設け、その両側の半導体基板１にソース５とドレ
イン６とを設け、その表面を被覆する絶縁膜７の表面に
下部電極膜８を形成している。この下部電極膜８には複
数の円筒型電極膜、即ち第１の円筒型電極膜１０，第２
の円筒型電極膜１２，第３の円筒型電極膜１４が接続し
て形成されており、この表面を被覆するキャパシタ絶縁
膜１５を介して上部電極膜１６を被着形成してキャパシ
タを形成している。FIG. 1 is a side cross-sectional view showing the structure of a memory cell of a semiconductor device according to the present invention, and FIGS. 2 to 6 are side cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention in the order of steps. As shown in FIG. 1, a gate electrode 4 is provided on the surface of a semiconductor substrate 1 defined by a field oxide film 2 via a gate oxide film 3, and a source 5 and a drain 6 are provided on the semiconductor substrate 1 on both sides thereof. , a lower electrode film 8 is formed on the surface of an insulating film 7 covering the surface thereof. This lower electrode film 8 includes a plurality of cylindrical electrode films, that is, a first cylindrical electrode film 10, a second cylindrical electrode film 10, and a second cylindrical electrode film 10.
A cylindrical electrode film 12 and a third cylindrical electrode film 14 are connected to each other, and an upper electrode film 16 is deposited through a capacitor insulating film 15 covering the surface to form a capacitor. ing.
【００１７】以下、本実施例の半導体装置の製造方法を
工程順に図２〜図６を参照して詳細に説明する。まず図
２（ａ） に示すように従来法と同様に、ｐ型の半導体
基板１上にＬＯＣＯＳ法によつて選択的にフィールド酸
化膜２を形成し、化学気相成長 （ＣＶＤ）法によって
ゲ−ト酸化膜３を介して導電性のポリシリコン膜からな
るゲート電極４を形成し、イオン注入によりｎ型のソー
ス５及びドレイン６を形成し、これらの表面にシリコン
酸化膜からなる膜厚 ３，０００Å程度の絶縁膜７を被
着形成する。Hereinafter, the method for manufacturing the semiconductor device of this embodiment will be explained in detail in the order of steps with reference to FIGS. 2 to 6. First, as shown in FIG. 2(a), similarly to the conventional method, a field oxide film 2 is selectively formed on a p-type semiconductor substrate 1 by the LOCOS method, and then a field oxide film 2 is formed by the chemical vapor deposition (CVD) method. - A gate electrode 4 made of a conductive polysilicon film is formed via a silicon oxide film 3, an n-type source 5 and a drain 6 are formed by ion implantation, and a film thickness of 3 made of a silicon oxide film is formed on the surfaces of these. An insulating film 7 having a thickness of about ,000 Å is deposited.
【００１８】つぎに図２（ｂ） に示すように、絶縁膜
７に設けた開口窓７ａを含む表面に導電性のポリシリコ
ン膜からなる膜厚１，０００〜２，０００Åの下部電極
膜８をＣＶＤ法により被着する。この開口窓７ａはソー
ス５と下部電極膜８とを接続する窓である。Next, as shown in FIG. 2(b), a lower electrode film 8 made of a conductive polysilicon film with a thickness of 1,000 to 2,000 Å is formed on the surface including the opening window 7a provided in the insulating film 7. is deposited by CVD method. This opening window 7a is a window that connects the source 5 and the lower electrode film 8.
【００１９】ついで図２（ｃ） に示すように、この下
部電極膜８の上に膜厚 ５，０００〜１０，０００Åの
シリコン酸化膜をＣＶＤ法により被着し、このシリコン
酸化膜をリソグラフィ技術によってパターンニングして
円柱状の第１のスペーサ膜９を形成する。Next, as shown in FIG. 2C, a silicon oxide film with a thickness of 5,000 to 10,000 Å is deposited on the lower electrode film 8 by the CVD method, and this silicon oxide film is deposited using the lithography technique. A columnar first spacer film 9 is formed by patterning.
【００２０】ここで図３（ａ） に示すように、この第
１のスペーサ膜９を含む絶縁膜７上に、膜厚１，０００
〜２，０００Åの導電性のポリシリコン膜からなる第１
の円筒型電極膜１０をＣＶＤ法により被着する。この場
合、第１の円筒型電極膜１０は第１のスペーサ膜９の周
囲を被覆して図示のように凸型に形成される。As shown in FIG. 3(a), a film with a thickness of 1,000 mm is formed on the insulating film 7 including the first spacer film 9.
The first layer consists of a conductive polysilicon film of ~2,000 Å.
A cylindrical electrode film 10 is deposited by the CVD method. In this case, the first cylindrical electrode film 10 covers the first spacer film 9 and is formed into a convex shape as shown.
【００２１】ついで図３（ｂ） に示すように、この第
１の円筒型電極膜１０の表面に膜厚 １，０００〜２，
０００ Åのシリコン酸化膜からなる第２のスペーサ膜
１１をＣＶＤ法によって被着する。Next, as shown in FIG. 3(b), the surface of the first cylindrical electrode film 10 is coated with a film thickness of 1,000 to 2,000.
A second spacer film 11 made of a silicon oxide film with a thickness of 0.000 Å is deposited by CVD.
【００２２】そして図４（ａ） に示すように、ＲＩＥ
法によりこの第２のスペーサ膜１１の異方性エッチング
を行い、凸型の第１の円筒型電極膜１０の側壁にのみこ
の第２のスペーサ膜１１を円筒状のサイドウォール１１
ａ として残存させた後、このサイドウォール１１ａ
を含む第１の円筒型電極膜１０の表面に、膜厚１，００
０〜２，０００Åの導電性のポリシリコン膜からなる第
２の円筒型電極膜１２をＣＶＤ法により被着する。Then, as shown in FIG. 4(a), RIE
This second spacer film 11 is anisotropically etched by a method such that the second spacer film 11 is etched only on the side wall of the convex first cylindrical electrode film 10.
After leaving it as a, this side wall 11a
A film thickness of 1,000 mm is applied to the surface of the first cylindrical electrode film 10 containing
A second cylindrical electrode film 12 made of a conductive polysilicon film with a thickness of 0 to 2,000 Å is deposited by CVD.
【００２３】つぎに図４（ｂ） に示すように、この第
２の円筒型電極膜１２の表面に膜厚 １，０００〜２，
０００ Åのシリコン酸化膜からなる第３のスペーサ膜
１３をＣＶＤ法によって被着する。Next, as shown in FIG. 4(b), the surface of the second cylindrical electrode film 12 is coated with a film thickness of 1,000 to 2,000.
A third spacer film 13 made of a silicon oxide film with a thickness of 0.000 Å is deposited by CVD.
【００２４】そして図５（ａ） に示すように、ＲＩＥ
法によりこの第３のスペーサ膜１３の異方性エッチング
を行い、第２の円筒型電極膜１２の側壁にのみこの第３
のスペーサ膜１３を円筒状のサイドウォール１３ａ と
して残存させた後、このサイドウォール１３ａ を含む
第２の円筒型電極膜１２の表面に、膜厚１，０００〜２
，０００Åの導電性のポリシリコン膜からなる第３の円
筒型電極膜１４をＣＶＤ法により被着する。Then, as shown in FIG. 5(a), RIE
This third spacer film 13 is anisotropically etched by a method such that the third spacer film 13 is etched only on the side wall of the second cylindrical electrode film 12.
After leaving the spacer film 13 as a cylindrical sidewall 13a, a film with a thickness of 1,000 to 2
A third cylindrical electrode film 14 made of a conductive polysilicon film with a thickness of .000 Å is deposited by CVD.
【００２５】ついで図５（ｂ） に示すように、導電性
のポリシリコン膜からなる第１の円筒型電極膜１０、第
２の円筒型電極膜１２、第３の円筒型電極膜１４及び下
部電極膜８を同時に、ＲＩＥ法による異方性のエッチン
グを行い、円柱状の第１のスペーサ膜９、サイドウォー
ル１１ａ 、サイドウォール１３ａ の上部を露出させ
る。Next, as shown in FIG. 5(b), the first cylindrical electrode film 10, the second cylindrical electrode film 12, the third cylindrical electrode film 14, and the lower part are made of a conductive polysilicon film. At the same time, the electrode film 8 is anisotropically etched by RIE to expose the upper portions of the cylindrical first spacer film 9, sidewalls 11a, and sidewalls 13a.
【００２６】つぎに図６（ａ） に示すように、このシ
リコン酸化膜からなる第１のスペーサ膜９、サイドウォ
ール１１ａ 、サイドウォール１３ａ を同時に弗酸系
溶液を用いたウェットエッチングによって除去する。Next, as shown in FIG. 6(a), the first spacer film 9, sidewalls 11a, and sidewalls 13a made of this silicon oxide film are simultaneously removed by wet etching using a hydrofluoric acid solution.
【００２７】最後に図６（ｂ） に示すように、上記の
露出させた円筒状の第１の円筒型電極膜１０、第２の円
筒型電極膜１２及び第３の円筒型電極膜１４の全表面に
膜厚５０〜１００ Åのシリコン窒化膜からなるキャパ
シタ絶縁膜１５を形成し、このキャパシタ絶縁膜１５の
全表面に導電性のポリシリコン膜からなる上部電極膜１
６を被着し、このキャパシタ絶縁膜１５と上部電極膜１
６とを同時にパタ−ンニングしてキャパシタを完成する
。この際、キャパシタ絶縁膜１５及び上部電極膜１６は
ＣＶＤ法によって被着させるので被覆性が良く、狭い溝
状の部分まで確実に被覆させることができる。Finally, as shown in FIG. 6(b), the exposed cylindrical first cylindrical electrode film 10, second cylindrical electrode film 12, and third cylindrical electrode film 14 are removed. A capacitor insulating film 15 made of a silicon nitride film with a thickness of 50 to 100 Å is formed on the entire surface, and an upper electrode film 1 made of a conductive polysilicon film is formed on the entire surface of this capacitor insulating film 15.
6, and this capacitor insulating film 15 and upper electrode film 1
6 is patterned at the same time to complete the capacitor. At this time, since the capacitor insulating film 15 and the upper electrode film 16 are deposited by the CVD method, the covering properties are good and even the narrow groove-like portions can be reliably covered.
【００２８】上記のような製造方法によれば、導電性の
ポリシリコン膜からなる下部電極膜８と接続した第１の
円筒型電極膜１０、第２の円筒型電極膜１２、第３の円
筒型電極膜１４の表面積が極めて大きくなるので、キャ
パシタの容量を著しく増加させることが可能となる。従
って、本発明により製造したＭＯＳ ＤＲＡＭのＭＯＳ
メモリセルは微小な領域に集積度の高いメモリ素子を微
細に形成すると同時に、極めて大容量のキャパシタを形
成させることができる。According to the above manufacturing method, the first cylindrical electrode film 10, the second cylindrical electrode film 12, and the third cylindrical electrode film 10 are connected to the lower electrode film 8 made of a conductive polysilicon film. Since the surface area of the type electrode film 14 becomes extremely large, it becomes possible to significantly increase the capacitance of the capacitor. Therefore, the MOS of the MOS DRAM manufactured according to the present invention
In memory cells, highly integrated memory elements can be minutely formed in a minute area, and at the same time, extremely large capacitance capacitors can be formed.
【００２９】本実施例においては円筒型電極膜を３個用
いているが、円筒型電極膜の数は３個に限定されるもの
ではない。Although three cylindrical electrode films are used in this embodiment, the number of cylindrical electrode films is not limited to three.
【００３０】[0030]
【発明の効果】以上の説明から明らかなように、本発明
によりＭＯＳ ＤＲＡＭのＭＯＳメモリを製造すれば、
形成領域が微小化してメモリ素子が微細化しても、キャ
パシタの容量を増大させることが可能となるので、高速
化，高信頼化などの半導体装置の性能向上に顕著に寄与
する利点があり、著しい経済的及び、信頼性向上の効果
が期待できる半導体装置及びその製造方法の提供が可能
である。[Effects of the Invention] As is clear from the above explanation, if a MOS memory of MOS DRAM is manufactured according to the present invention,
Even if the formation area becomes smaller and the memory element becomes smaller, it is possible to increase the capacitance of the capacitor, which has the advantage of significantly contributing to improving the performance of semiconductor devices such as higher speed and higher reliability. It is possible to provide a semiconductor device and a method for manufacturing the same that can be expected to be economical and improve reliability.
【図１】 本発明の半導体装置のメモリセルの構造を
示す側断面図、FIG. 1 is a side sectional view showing the structure of a memory cell of a semiconductor device of the present invention;
【図２】 本発明による半導体装置の製造方法の一実
施例を工程順に示す側断面図（１） 、FIG. 2 is a side sectional view (1) showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps;
【図３】 本発明による半導体装置の製造方法の一実
施例を工程順に示す側断面図（２） 、FIG. 3 is a side sectional view (2) showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps;
【図４】 本発明による半導体装置の製造方法の一実
施例を工程順に示す側断面図（３） 、FIG. 4 is a side sectional view (3) showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps;
【図５】 本発明による半導体装置の製造方法の一実
施例を工程順に示す側断面図（４） 、FIG. 5 is a side sectional view (4) showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps;
【図６】 本発明による半導体装置の製造方法の一実
施例を工程順に示す側断面図（５） 、FIG. 6 is a side sectional view (5) showing an embodiment of the method for manufacturing a semiconductor device according to the present invention in the order of steps;
【図７】 従来の半導体装置のメモリセルの構造を示
す側断面図、[Fig. 7] A side cross-sectional view showing the structure of a memory cell of a conventional semiconductor device.
【図８】 従来の半導体装置の製造方法を工程順に示
す側断面図、FIG. 8 is a side sectional view showing a conventional semiconductor device manufacturing method in the order of steps;
１は半導体基板、 ２はフィールド酸化膜、 ３はゲ−ト酸化膜、 ４はゲート電極、 ５はソース、 ６はドレイン、 ７は絶縁膜、 ７ａは開口窓、 ８は下部電極膜、 ９は第１のスペーサ膜、 １０は第１の円筒型電極膜、 １１は第２のスペーサ膜、 １１ａ はサイドウォール、 １２は第２の円筒型電極膜、 １３は第３のスペーサ膜、 １３ａ はサイドウォール、 １４は第３の円筒型電極膜、 １５はキャパシタ絶縁膜、 １６は上部電極膜、 1 is a semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate electrode; 5 is the sauce, 6 is the drain, 7 is an insulating film, 7a is an opening window; 8 is a lower electrode film; 9 is a first spacer film; 10 is a first cylindrical electrode film; 11 is a second spacer film; 11a is the side wall, 12 is a second cylindrical electrode film; 13 is a third spacer film; 13a is the side wall, 14 is a third cylindrical electrode film; 15 is a capacitor insulating film; 16 is an upper electrode film;
Claims (3)
上部電極とが対向するキャパシタを具備する半導体装置
であって、前記下部電極が、下部電極膜（８） と接続
する単一または複数の円筒型電極膜（１０，１２，１４
）とから構成され、前記上部電極が、前記円筒型電極膜
（１０，１２，１４）の表面を被覆するキャパシタ絶縁
膜（１５）を介して前記円筒型電極膜（１０，１２，１
４）と対向して設けられてなることを特徴とする半導体
装置。1. A semiconductor device comprising a capacitor in which a lower electrode and an upper electrode face each other with a capacitor insulating film interposed therebetween, the lower electrode comprising a single or plural cylinders connected to a lower electrode film (8). Type electrode film (10, 12, 14
), and the upper electrode connects to the cylindrical electrode film (10, 12, 1) via a capacitor insulating film (15) that covers the surface of the cylindrical electrode film (10, 12,
4) A semiconductor device, characterized in that it is provided opposite to.
の表面に形成した下部電極膜（８） の表面に円柱状
の第１のスペーサ膜（９） を形成する工程と、該第１
のスペーサ膜（９） 及び前記下部電極膜（８） の表
面に第１の円筒型電極膜（１０）を被着形成する工程と
、該第１の円筒型電極膜（１０）の全表面に第２のスペ
ーサ膜（１１）を被着形成した後、該第２のスペーサ膜
（１１）の異方性のエッチングを行って前記第１の円筒
型電極膜（１０）の垂直部の側壁にサイドウォール（１
１ａ） を形成する工程と、該サイドウオール（１１ａ
） 及び前記第１の円筒型電極膜（１０）の全表面に第
２の円筒型電極膜（１２）を被着し、該第２の円筒型電
極膜（１２）の全表面に第３のスペーサ膜（１３）を被
着形成した後、該第３のスペーサ膜（１３）の異方性の
エッチングを行い、前記第２の円筒型電極膜（１２）の
垂直部の側壁にサイドウォール（１３ａ） を形成する
工程と、該サイドウオール（１３ａ） 及び前記第２の
円筒型電極膜（１２）の全表面に第３の円筒型電極膜（
１４）を被着形成した後、前記絶縁膜（７） が露出す
るまで前記下部電極膜（８） 、第１の円筒型電極膜（
１０）、第２の円筒型電極膜（１２）、第３の円筒型電
極膜（１４）の異方性のエッチングを行う工程と、前記
第１のスペーサ膜（９） 、サイドウォール（１１ａ）
、サイドウォール（１３ａ） をエッチングして除去
する工程と、前記絶縁膜（７） 、第１の円筒型電極膜
（１０）、第２の円筒型電極膜（１２）、第３の円筒型
電極膜（１４）の表面にキャパシタ絶縁膜（１５）を被
着形成し、該キャパシタ絶縁膜（１５）の表面に上部電
極膜（１６）を被着形成する工程と、を含むことを特徴
とする半導体装置の製造方法。[Claim 2] Insulating film (7) on semiconductor substrate (1)
forming a cylindrical first spacer film (9) on the surface of the lower electrode film (8) formed on the surface of the first spacer film;
a step of depositing a first cylindrical electrode film (10) on the surfaces of the spacer film (9) and the lower electrode film (8), and covering the entire surface of the first cylindrical electrode film (10). After depositing and forming the second spacer film (11), the second spacer film (11) is anisotropically etched to form a side wall of the vertical portion of the first cylindrical electrode film (10). side wall (1
1a) and the step of forming the sidewall (11a).
) and a second cylindrical electrode film (12) is deposited on the entire surface of the first cylindrical electrode film (10), and a third cylindrical electrode film (12) is deposited on the entire surface of the second cylindrical electrode film (12). After depositing and forming the spacer film (13), the third spacer film (13) is anisotropically etched, and sidewalls ( 13a) and forming a third cylindrical electrode film (12) on the entire surface of the sidewall (13a) and the second cylindrical electrode film (12).
14), the lower electrode film (8) and the first cylindrical electrode film (14) are deposited until the insulating film (7) is exposed.
10), a step of anisotropically etching the second cylindrical electrode film (12) and the third cylindrical electrode film (14), and the first spacer film (9) and the sidewall (11a).
, a step of etching and removing the sidewall (13a), the insulating film (7), the first cylindrical electrode film (10), the second cylindrical electrode film (12), and the third cylindrical electrode. It is characterized by comprising the steps of depositing a capacitor insulating film (15) on the surface of the film (14) and depositing an upper electrode film (16) on the surface of the capacitor insulating film (15). A method for manufacturing a semiconductor device.
において、前記第１のスペーサ膜（９） を角柱状とし
、前記の第１の円筒型電極膜（１０）、第２のスペーサ
膜（１１）、第２の円筒型電極膜（１２）、第３のスペ
ーサ膜（１３）、第３の円筒型電極膜（１４）を角筒型
とすることを特徴とする半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the first spacer film (9) has a prismatic shape, and the first cylindrical electrode film (10) and the second spacer film ( 11) A method for manufacturing a semiconductor device, characterized in that the second cylindrical electrode film (12), the third spacer film (13), and the third cylindrical electrode film (14) have a rectangular tube shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3026004A JPH04264767A (en) | 1991-02-20 | 1991-02-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3026004A JPH04264767A (en) | 1991-02-20 | 1991-02-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04264767A true JPH04264767A (en) | 1992-09-21 |
Family
ID=12181557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3026004A Withdrawn JPH04264767A (en) | 1991-02-20 | 1991-02-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04264767A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04350965A (en) * | 1991-05-23 | 1992-12-04 | Samsung Electron Co Ltd | Manufacture of capacitor used for memory cell of semiconductor memory device and structure thereof |
| EP0595360A1 (en) * | 1992-10-30 | 1994-05-04 | Nec Corporation | Method of manufacturing a semiconductor device having a cylindrical electrode |
| JPH06188382A (en) * | 1991-12-31 | 1994-07-08 | Hyundai Electron Ind Co Ltd | Preparation of electric charge storage of electrode semiconductor memory |
| US5508222A (en) * | 1993-12-13 | 1996-04-16 | Nec Corporation | Fabrication process for semiconductor device |
| US5753949A (en) * | 1995-09-29 | 1998-05-19 | Nec Corporation | Semiconductor device wherein one of capacitor electrodes comprises a conductor pole and conductor layer |
| US5835337A (en) * | 1995-09-29 | 1998-11-10 | Nec Corporation | Stacked capacitor having a corrugated electrode |
| US5939747A (en) * | 1996-11-13 | 1999-08-17 | Oki Electric Industry Co., Ltd. | Capacitor produced in a semiconductor device |
| US6054360A (en) * | 1996-06-04 | 2000-04-25 | Nec Corporation | Method of manufacturing a semiconductor memory device with a stacked capacitor wherein an electrode of the capacitor is shaped using a high melting point metal film |
| US6104055A (en) * | 1997-03-27 | 2000-08-15 | Nec Corporation | Semiconductor device with memory cell having a storage capacitor with a plurality of concentric storage electrodes formed in an insulating layer and fabrication method thereof |
-
1991
- 1991-02-20 JP JP3026004A patent/JPH04264767A/en not_active Withdrawn
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04350965A (en) * | 1991-05-23 | 1992-12-04 | Samsung Electron Co Ltd | Manufacture of capacitor used for memory cell of semiconductor memory device and structure thereof |
| JPH06188382A (en) * | 1991-12-31 | 1994-07-08 | Hyundai Electron Ind Co Ltd | Preparation of electric charge storage of electrode semiconductor memory |
| EP0595360A1 (en) * | 1992-10-30 | 1994-05-04 | Nec Corporation | Method of manufacturing a semiconductor device having a cylindrical electrode |
| US5508222A (en) * | 1993-12-13 | 1996-04-16 | Nec Corporation | Fabrication process for semiconductor device |
| US5753949A (en) * | 1995-09-29 | 1998-05-19 | Nec Corporation | Semiconductor device wherein one of capacitor electrodes comprises a conductor pole and conductor layer |
| US5835337A (en) * | 1995-09-29 | 1998-11-10 | Nec Corporation | Stacked capacitor having a corrugated electrode |
| US5837594A (en) * | 1995-09-29 | 1998-11-17 | Nec Corporation | Method of manufacturing a semiconductor device wherein one of capacitor electrodes comprises a conductor pole and a tray-shaped conductor layer |
| US6022772A (en) * | 1995-09-29 | 2000-02-08 | Nec Corporation | Stacked capacitor having a corrugated electrode |
| US6054360A (en) * | 1996-06-04 | 2000-04-25 | Nec Corporation | Method of manufacturing a semiconductor memory device with a stacked capacitor wherein an electrode of the capacitor is shaped using a high melting point metal film |
| US5939747A (en) * | 1996-11-13 | 1999-08-17 | Oki Electric Industry Co., Ltd. | Capacitor produced in a semiconductor device |
| US6104055A (en) * | 1997-03-27 | 2000-08-15 | Nec Corporation | Semiconductor device with memory cell having a storage capacitor with a plurality of concentric storage electrodes formed in an insulating layer and fabrication method thereof |
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