JPH0425706B2 - - Google Patents
Info
- Publication number
- JPH0425706B2 JPH0425706B2 JP58068534A JP6853483A JPH0425706B2 JP H0425706 B2 JPH0425706 B2 JP H0425706B2 JP 58068534 A JP58068534 A JP 58068534A JP 6853483 A JP6853483 A JP 6853483A JP H0425706 B2 JPH0425706 B2 JP H0425706B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- forming
- collector
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000002955 isolation Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000605 extraction Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 description 32
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000000926 separation method Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
技術分野
本発明は少なくともNPN型トランジスタと
PNP型トランジスタとを含む半導体集積回路の
製造方法に関するものである。[Detailed Description of the Invention] Technical Field The present invention relates to at least an NPN type transistor.
The present invention relates to a method of manufacturing a semiconductor integrated circuit including a PNP transistor.
従来技術
第１図に示す従来のPNP型トランジスタと
NPN型トランジスタとを含むコンプリメンタリ
な半導体集積回路の製造方法は、P-型基板１に
PNP型トランジスタを分離するためのＮ型埋込
拡散層２を形成する工程と、NPN型トランジス
タのコレクタ低抵抗領域となるN+型埋込拡散層
３を形成する工程と、分離領域を形成するための
P+型埋込拡散層４ａ及びPNP型トランジスタの
コレクタ領域となるP+型埋込拡散層４ｂを形成
する工程と、基板１上にN-型エピタキシヤル層
５を形成する工程と、P+型分離用拡散層６ａ及
びコレクタ引き出し用P+型拡散層６ｂを形成す
る工程と、コレクタ引き出し用N+型拡散層７を
形成する工程と、ベース領域となるP+型拡散層
８ａ及びエミツタ領域となるP+型拡散層８ｂを
形成する工程と、エミツタ領域となるN+型拡散
層９ａ及びベース引き出し領域となるN+型拡散
層９ｂを形成する工程とを有する。Conventional technology The conventional PNP transistor shown in Figure 1 and
The manufacturing method of a complementary semiconductor integrated circuit including an NPN type transistor is based on a P - type substrate 1.
A step of forming an N-type buried diffusion layer 2 for isolating the PNP transistor, a step of forming an N + type buried diffusion layer 3 which becomes a collector low resistance region of the NPN transistor, and a step of forming an isolation region. for
A step of forming a P + type buried diffusion layer 4a and a P + type buried diffusion layer 4b which will become a collector region of a PNP transistor, a step of forming an N - type epitaxial layer 5 on the substrate 1, A step of forming a type separation diffusion layer 6a and a P + type diffusion layer 6b for extracting the collector, a step of forming an N + type diffusion layer 7 for extracting the collector, a P + type diffusion layer 8a serving as a base region, and an emitter region. The process includes a step of forming a P + type diffusion layer 8b, which becomes the emitter region, and a step of forming an N + type diffusion layer 9a, which becomes the emitter region, and an N + type diffusion layer 9b, which becomes the base extraction region.
従つて、従来の方法では分離領域としてP+型
埋込拡散層４ａ及びP+型拡散層６ａを設ける工
程、更にＮ型埋込拡散層２を設ける工程が必要に
なる。このため、製造工程が多く、且つチツプ面
積が必然的に大になつた。 Therefore, the conventional method requires a step of providing the P + type buried diffusion layer 4a and the P + type diffusion layer 6a as isolation regions, and a further step of providing the N type buried diffusion layer 2. For this reason, there are many manufacturing steps and the chip area inevitably becomes large.
発明の目的
そこで、本発明の目的は、製造工程の簡略化及
びチツプ面積の低減が可能な半導体集積回路の製
造方法を提供することにある。OBJECTS OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can simplify the manufacturing process and reduce the chip area.
発明の構成
上記目的を達成するための本発明は、実施例を
示す図面の符号を参照して説明すると、Ｎ型半導
体基板１１の中にその表面側を除いて前記Ｎ型半
導体基板１１に包囲されるようにNPN型トラン
ジスタのためのＰ型分離領域１２ａ及びPNP型
トランジスタのためのＰ型コレクタ領域１２ｂを
形成する工程と、前記Ｐ型分離領域１２ａの中に
その表面側を除いて前記Ｐ型分離領域１２ａに包
囲されるように前記NPN型トランジスタのＮ型
低抵抗コレクタ領域１３を形成する工程と、前記
Ｐ型分離領域１２ａと前記Ｐ型コレクタ領域１２
ｂと前記Ｎ型低抵抗コレクタ領域１３とを含む前
記基板１１上に前記Ｎ型低抵抗コレクタ領域１３
よりも高い抵抗値を有するＮ型エピタキシヤル層
１４を形成する工程と、この工程又は後の工程で
前記Ｎ型エピタキシヤル層１４の表面から前記Ｐ
型分離領域１２ａに達するようにＰ型環状分離領
域１５ａを前記Ｎ型エピタキシヤル層１４の中に
形成し、同時にこの工程又は後の工程で前記Ｎ型
エピタキシヤル層１４の表面から前記Ｐ型コレク
タ領域１２ｂに達するようにＰ型環状コレクタ引
き出し領域１５ｂを前記Ｎ型エピタキシヤル層１
４の中に形成し、互いに独立している前記Ｐ型環
状分離領域１５ａと前記Ｐ型コレクタ引き出し領
域１５ｂとによつて第１及び第２のＮ型島状領域
１４ａ，１４ｂを生じさせる工程と、前記第１の
Ｎ型島状領域１４ａに前記NPN型トランジスタ
のＰ型ベース領域１８ａとＮ型エミツタ領域１９
とを夫々形成し、前記第２のＮ型島状領域１４ｂ
の中に前記PNP型トランジスタのＰ型エミツタ
領域１８ｂを形成する工程とを含んだ半導体集積
回路の製造方法に係わるものである。Structure of the Invention To achieve the above object, the present invention will be described with reference to the reference numerals in the drawings showing the embodiments. A step of forming a P-type isolation region 12a for an NPN-type transistor and a P-type collector region 12b for a PNP-type transistor as shown in FIG. forming the N-type low resistance collector region 13 of the NPN transistor so as to be surrounded by the type isolation region 12a, and forming the P-type isolation region 12a and the P-type collector region 12;
b and the N-type low-resistance collector region 13 on the substrate 11 including the N-type low-resistance collector region 13.
A step of forming an N-type epitaxial layer 14 having a resistance value higher than that of the N-type epitaxial layer 14;
A P-type annular isolation region 15a is formed in the N-type epitaxial layer 14 so as to reach the type isolation region 12a, and at the same time, in this step or a later step, a P-type annular isolation region 15a is formed from the surface of the N-type epitaxial layer 14 to the P-type collector. The P-type annular collector extraction region 15b is connected to the N-type epitaxial layer 1 so as to reach the region 12b.
forming first and second N-type island regions 14a and 14b by the P-type annular separation region 15a and the P-type collector extraction region 15b, which are formed in the P-type annular isolation region 15a and the P-type collector extraction region 15b, which are formed in the P-type annular isolation region 15a and the P-type collector extraction region 15b, which are formed in the P-type , a P-type base region 18a and an N-type emitter region 19 of the NPN transistor are provided in the first N-type island region 14a.
and the second N-type island region 14b.
The present invention relates to a method of manufacturing a semiconductor integrated circuit, which includes a step of forming a P-type emitter region 18b of the PNP-type transistor.
発明の作用効果 本発明は次の作用効果を有する。Effects of invention The present invention has the following effects.
(イ) PNP型トランジスタのＰ型コレクタ領域１
２ｂとＰ型環状コレクタ引き出し領域１５ｂを
Ｎ型基板１１とＮ型エピタキシヤル層１４で囲
むことによつてPNP型トランジスタの分離が
達成されるので、分離のための特別な不純物拡
散が不要になり、製造工程が簡略化される。(a) P-type collector region 1 of PNP-type transistor
2b and the P-type annular collector extraction region 15b are surrounded by the N-type substrate 11 and the N-type epitaxial layer 14 to achieve separation of the PNP-type transistors, so special impurity diffusion for separation is not required. , the manufacturing process is simplified.
(ロ) PNP型トランジスタにおいて分離のための
特別な不純物拡散領域を有さないので、チツプ
面積を小さくすることができる。(b) Since the PNP transistor does not have a special impurity diffusion region for isolation, the chip area can be reduced.
実施例
次に、第２図〜第１１図を参照して本発明の実
施例に係わる集積回路及びその製造について述べ
る。本実施例の集積回路は、第１１図に示すモー
タ制御回路の一部、即ち、NPN型の第１のトラ
ンジスタQ1とPNP型の第２のトランジスタQ2と
を含む回路、又はNPN型の第３のトランジスタ
Q3とPNP型の第４のトランジスタQ4とを含む回
路から成る。Embodiment Next, an integrated circuit and its manufacture according to an embodiment of the present invention will be described with reference to FIGS. 2 to 11. The integrated circuit of this embodiment is a part of the motor control circuit shown in FIG. 11, that is, a circuit including a first NPN transistor Q1 and a second PNP transistor Q2 , or third transistor
It consists of a circuit including Q 3 and a fourth transistor Q 4 of PNP type.
第１１図の回路で要求するNPN型Siトランジ
スタとPNP型Siトランジスタとを同一の基板に
形成するために、まず、第２図に示す如く、５〜
10Ω・cmの比抵抗を有するN-型Si基板１１に、
シート抵抗ρs＝50Ω／□、拡散深さxj＝15μｍの
P+型分離領域１２ａ及びP+型コレクタ領域１２
ｂを硼素の選択拡散法により形成する。なお、第
２図〜第９図では選択拡散のマスクとなるSiO2
膜が夫々省略されている。また、NPN型トラン
ジスタを高耐圧化する時は、まず、P+型コレク
タ領域１２ｂのためのプレデポジツト拡散を行
い、次いでP+型分離領域１２ａのためのプレデ
ポジツト拡散を行い、その後同時にドライブ拡散
を行う方法によつてP+型分離領域１２をρs＝500
Ω／□、xj＝10μｍとし、P+型コレクタ領域１２
ｂをρs＝50Ω／□、xj＝15μｍとしてもよい。 In order to form the NPN type Si transistor and the PNP type Si transistor required in the circuit of FIG. 11 on the same substrate, first, as shown in FIG.
On the N - type Si substrate 11 having a specific resistance of 10Ω・cm,
Sheet resistance ρ s = 50Ω/□, diffusion depth x j = 15 μm
P + type isolation region 12a and P + type collector region 12
b is formed by a boron selective diffusion method. In addition, in Figures 2 to 9, SiO 2 is used as a mask for selective diffusion.
Each membrane is omitted. Furthermore, when increasing the withstand voltage of an NPN transistor, first perform pre-deposit diffusion for the P + type collector region 12b, then perform pre-deposit diffusion for the P + type isolation region 12a, and then perform drive diffusion at the same time. P + type isolation region 12 by ρ s = 500
Ω/□, x j = 10 μm, P + type collector region 12
b may be set to ρ s =50Ω/□ and x j =15 μm.
次に、第３図に示す如く、砒素（あるいはアン
チモン）を選択拡散することによつてρs＝15Ω／
□、xj＝3μｍのN+型低抵抗コレクタ領域１３を
P+型分離領域１２ａの中に形成する。 Next, as shown in Figure 3, by selectively diffusing arsenic (or antimony), ρ s =15Ω/
□, x j = 3 μm N + type low resistance collector region 13
It is formed in the P + type isolation region 12a.
次に、第４図に示す如く、基板１１上に燐をド
ープしたN-型シリコンを成長させることによつ
て比抵抗１〜２Ω・cm、厚さ約16μｍのN-型エピ
タキシヤル層１４を形成する。この時、領域１２
ａ，１２ｂ，１３は上に延びる。 Next, as shown in FIG. 4, by growing phosphorous-doped N - type silicon on the substrate 11, an N - type epitaxial layer 14 having a resistivity of 1 to 2 Ω·cm and a thickness of about 16 μm is formed. Form. At this time, area 12
a, 12b, 13 extend upward.
次に、第５図に示す如く、硼素を選択拡散する
ことによつて、第１のN-型島状領域１４ａが生
じるようにP+型環状分離領域１５ａを形成し、
同時に第２のN-型島状領域１４ｂが生じるよう
にP+型コレクタ引き出し領域１５ｂを環状に形
成する。この時、領域１５ａ，１５ｂのρsは10
Ω／□であり、xjは12μｍである。なお、領域１
５ａ，１５ｂは互いに独立し且つエピタキシヤル
層１４の残存領域１４ｃによつて囲まれている。
また。領域１５ａ，１５ｂはP+型分離領域１２
ａとP+型コレクタ領域１２ｂとに夫々達してい
る。しかし、この工程で領域１５ａ，１５ｂと領
域１２ａ，１２ｂとを接続させずに、以後の加熱
工程において接続させてもよい。 Next, as shown in FIG. 5, by selectively diffusing boron, a P + type annular isolation region 15a is formed so that a first N - type island region 14a is generated, and
At the same time, a P + -type collector extraction region 15b is formed in an annular shape so that a second N - -type island region 14b is generated. At this time, ρ s in regions 15a and 15b is 10
Ω/□, and x j is 12 μm. In addition, area 1
5a, 15b are independent from each other and surrounded by a remaining region 14c of epitaxial layer 14.
Also. Regions 15a and 15b are P + type isolation regions 12
a and the P + type collector region 12b, respectively. However, the regions 15a, 15b and the regions 12a, 12b may not be connected in this step, but may be connected in a subsequent heating step.
次に、第６図に示す如く、第１の島状領域１４
ａの中に燐の選択拡散法によつてρs＝15Ω／□、
xj＝10μｍのN+型コレクタ電極形成領域１６を環
状に形成する。この実施例ではこの工程で領域１
６が領域１３に達しているが、後の加熱工程で領
域１３に達するようにしてもよい、また、NPN
型トランジスタの飽和電圧があまり問題にならな
いときは、最終工程においても、領域１６が領域
１３から分離されていてもよい。 Next, as shown in FIG.
By the selective diffusion method of phosphorus into a, ρ s =15Ω/□,
An N + type collector electrode forming region 16 with x j =10 μm is formed in an annular shape. In this example, in this step, area 1
6 has reached region 13, but it may be possible to reach region 13 in a later heating process.Also, NPN
When the saturation voltage of the type transistor is not so important, region 16 may be separated from region 13 even in the final step.
次に、第７図に示す如く、第２の島状領域１４
ｂに燐の選択拡散法によつてρs＝60Ω／□、xj＝
7μｍのN-型島状領域１４ｂよりも低抵抗のＮ型
低抵抗ベース領域１７を形成する。第７図では領
域１７と領域１２ｂとの間にN-型島状領域１４
ｂの一部が残存するように領域１７が形成されて
いるが、領域１７が領域１２ｂに達するように拡
散してもよい。領域１７とP+型コレクタ引き出
し領域１５ｂとの間に、PNP型トランジスタの
耐圧向上のためにN-型島状領域１４ｂの一部を
を残存させる。 Next, as shown in FIG.
By the selective diffusion method of phosphorus in b, ρ s = 60Ω/□, x j =
An N type low resistance base region 17 having a resistance lower than that of the N - type island region 14b of 7 μm is formed. In FIG. 7, an N - type island region 14 is shown between region 17 and region 12b.
Although the region 17 is formed so that part of b remains, it may be diffused so that the region 17 reaches the region 12b. A part of the N - type island region 14b is left between the region 17 and the P + type collector lead-out region 15b in order to improve the withstand voltage of the PNP transistor.
次に、第８図に示す如く、硼素の選択拡散法に
よつてρs＝30Ω／□、xj＝4μｍのP+型ベース領域
１８ａ及びP+型エミツタ領域１８ｂを同時に形
成する。この際、一方の領域１８ａはN-型の第
１の島状領域１４ａのほぼ中央に形成するが、他
方の領域１８ｂはＮ型低抵抗ベース領域１７の右
側に片寄つた状態に形成する。領域１８ｂと領域
１７との関係を更に詳しく説明すると、P+型エ
ミツタ領域１８ｂの右側面とＮ型低抵抗ベース領
域１７の右側面とが重なるように、領域１８ｂを
形成する。このように、領域１８ｂを片寄つた状
態に形成すると、チツプ面積を減少させることが
出来る。実施例では、領域１８ｂの右側面と領域
１７の右側面とがほぼ重なつているが、領域１８
ｂの右側面と領域１４ｂとの間に領域１７の一部
が少し露出する場合に於いてもチツプ面積の低減
の効果が得られる。この場合には、領域１７の露
出面の距離が領域１８ｂの下部の領域１７の厚さ
Ｌよりも小であることが望ましい。また、実施例
のように領域１７，１８ｂの右側面が重なる場合
には、領域１８ｂの深さxjの2/3以下の深さで領
域１８ｂの拡散層と領域１７の拡散層とが交差す
るように選択拡散することが望ましい。上述の如
く、領域１８ｂを領域１７の中に片寄つた状態に
配置しても、領域１７，１８ｂをN-型の領域１
４ｂが囲んでいるので、PNP型トランジスタを
得ることが出来る。 Next, as shown in FIG. 8, a P + type base region 18a and a P + type emitter region 18b with ρ s =30Ω/□ and x j =4 μm are simultaneously formed by a selective boron diffusion method. At this time, one region 18a is formed approximately at the center of the N - type first island region 14a, while the other region 18b is formed offset to the right side of the N-type low resistance base region 17. To explain the relationship between region 18b and region 17 in more detail, region 18b is formed so that the right side surface of P + type emitter region 18b and the right side surface of N type low resistance base region 17 overlap. By forming the region 18b in an offset state in this manner, the chip area can be reduced. In the embodiment, the right side of area 18b and the right side of area 17 almost overlap;
Even if a portion of region 17 is slightly exposed between the right side surface of portion b and region 14b, the effect of reducing the chip area can be obtained. In this case, it is desirable that the distance between the exposed surfaces of the region 17 is smaller than the thickness L of the region 17 below the region 18b. In addition, when the right side surfaces of regions 17 and 18b overlap as in the example, the diffusion layer of region 18b and the diffusion layer of region 17 intersect at a depth of 2/3 or less of the depth x j of region 18b. It is desirable to perform selective diffusion so as to As described above, even if the region 18b is arranged offset in the region 17, the regions 17 and 18b can be arranged as an N - type region 1.
Since it is surrounded by 4b, a PNP type transistor can be obtained.
次に、第９図に示す如く、燐の選択拡散によつ
てρs＝５Ω／□、xj＝2μｍのN+型エミツタ領域
１９をP+型ベース領域１８ａの中に形成する。
なお、この工程で領域１７にN+型のベース電極
接続領域を同時に形成してもよい。 Next, as shown in FIG. 9, an N + type emitter region 19 with ρ s =5Ω/□ and x j =2 μm is formed in the P + type base region 18a by selective diffusion of phosphorus.
Note that an N + type base electrode connection region may be formed in the region 17 at the same time in this step.
次に、第１０図に示す如く、アルミニウムの蒸
着によつて、NPN型トランジスタのコレクタ電
極２０ａ、ベース電極２１ａ、及びエミツタ電極
２２ａを形成すると共にPNP型トランジスタの
コレクタ電極２０ｂ、ベース電極２１ｂ、及びエ
ミツタ電極２２ｂを形成し、更にN-型エピタキ
シヤル層１４の残存領域１４ａに電源電圧＋Vcc
（最高電圧）を印加する電極２３を形成し、更に
P+型分離領域１２ａ，１５ａをグランド（最低
電位ライン）に接続するための電極２４を形成す
る。なお、第１０図の２５はSiO2膜である。ま
た、図示されていない領域の半導体素子も、図示
のトランジスタと同様に形成する。 Next, as shown in FIG. 10, the collector electrode 20a, base electrode 21a, and emitter electrode 22a of the NPN transistor are formed by vapor deposition of aluminum, and the collector electrode 20b, base electrode 21b, and The emitter electrode 22b is formed, and the remaining region 14a of the N - type epitaxial layer 14 is connected to the power supply voltage +V cc.
(highest voltage) is formed, and further
An electrode 24 is formed to connect the P + type isolation regions 12a and 15a to the ground (lowest potential line). Note that 25 in FIG. 10 is a SiO 2 film. Further, semiconductor elements in regions not shown are also formed in the same manner as the transistors shown.
本実施例の集積回路には次の作用効果がある。 The integrated circuit of this embodiment has the following effects.
(A) N-型エピタキシヤル層１４の残存領域１４
ｃにP+型コレクタ領域１２ｂよりも高い電圧
＋Vccを加えることによつて、領域１１，１４
ｃと領域１２ｂ，１５ｂとの間が逆バイアス状
態となり、PNP型トランジスタの分離が達成
される。従つて、分離領域を形成するための特
別な工程を設けないで、分離が達成される。即
ち、第１図に示す従来の集積回路の領域２を設
ける工程が不要になる。この結果、製造工程が
１工程分簡略化される。(A) Remaining region 14 of N - type epitaxial layer 14
By applying a voltage +V cc higher than that of the P + type collector region 12b to c, the regions 11 and 14
A reverse bias state is established between C and regions 12b and 15b, and isolation of the PNP transistor is achieved. Therefore, separation is achieved without providing a special process for forming separation regions. That is, the step of providing region 2 of the conventional integrated circuit shown in FIG. 1 becomes unnecessary. As a result, the manufacturing process is simplified by one step.
(B) 第１図の領域２、及び領域４ａ，６ａのうち
右側の部分に相当する部分が不要になるので、
分離のための面積が減少し、チツプ面積の低減
が可能になる。(B) Area 2 and areas 4a and 6a in Figure 1, which correspond to the right side, are no longer needed, so
The area for separation is reduced, allowing for a reduction in chip area.
(C) 領域１７の中に領域１８ｂを片寄つて配置す
ることにより、領域１７の面積を低減させるこ
とが可能になり、チツプ面積を低減することが
出来る。(C) By arranging the region 18b in the region 17 in a biased manner, the area of the region 17 can be reduced, and the chip area can be reduced.
(D) 領域１４ｂの中に低抵抗ベース領域１７ｂを
設けているので、ベース拡散型トランジスタに
近い構成あるいはベース拡散型トランジスタと
することが可能になり、耐圧、電流増幅率、電
流増幅率の電流依存性、飽和電圧等の電気的特
性を、左側のベース拡散型のNPNトランジス
タに近づけることが可能になる。従つて、第１
１図に示す回路を構成する際には好都合にな
る。(D) Since the low-resistance base region 17b is provided in the region 14b, it is possible to have a structure similar to that of a base diffusion type transistor or a base diffusion type transistor, and the breakdown voltage, current amplification factor, and current of the current amplification factor are This makes it possible to make electrical characteristics such as dependence and saturation voltage close to those of the base diffusion type NPN transistor on the left. Therefore, the first
This is convenient when configuring the circuit shown in FIG.
第１図は従来の集積回路を示す断面図、第２
図、第３図、第４図、第５図、第６図、第７図、
第８図、第９図及び第１０図は本発明の実施例に
係わる集積回路を工程順に示す断面図、第１１図
は第１０図の集積回路を使用したモータ制御回路
を示す回路図である。
１１……N-型半導体基板、１２ａ……P+型分
離領域、１２ｂ……P+型コレクタ領域、１３…
…N+型低抵抗コレクタ領域、１４……N-型エピ
タキシヤル層、１４ａ……第１の島状領域、１４
ｂ……第２の島状領域、１４ｃ……残存領域、１
５ａ……P+型環状分離領域、１５ｂ……P+型コ
レクタ引き出し領域、１６……N+型コレクタ電
極形成領域、１７……Ｎ型低抵抗ベース領域、１
８ａ……P+型ベース領域、１８ｂ……P+型エミ
ツタ領域、１９……N+型エミツタ領域。
Figure 1 is a cross-sectional view of a conventional integrated circuit;
Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7,
8, 9, and 10 are cross-sectional views showing integrated circuits according to embodiments of the present invention in order of process, and FIG. 11 is a circuit diagram showing a motor control circuit using the integrated circuit shown in FIG. 10. . 11...N - type semiconductor substrate, 12a...P + type isolation region, 12b...P + type collector region, 13...
... N + type low resistance collector region, 14 ... N - type epitaxial layer, 14a ... first island region, 14
b...Second island-like area, 14c...Remaining area, 1
5a...P + type annular separation region, 15b...P + type collector extraction region, 16...N + type collector electrode formation region, 17...N type low resistance base region, 1
8a...P + type base region, 18b...P + type emitter region, 19...N + type emitter region.
Claims (1)
て前記Ｎ型半導体基板１１に包囲されるように
NPN型トランジスタのためのＰ型分離領域１２
ａ及びPNP型トランジスタのためのＰ型コレク
タ領域１２ｂを形成する工程と、 前記Ｐ型分離領域１２ａの中にその表面側を除
いて前記Ｐ型分離領域１２ａに包囲されるように
前記NPN型トランジスタのＮ型低抵抗コレクタ
領域１３を形成する工程と、 前記Ｐ型分離領域１２ａと前記Ｐ型コレクタ領
域１２ｂと前記Ｎ型低抵抗コレクタ領域１３とを
含む前記基板１１上に前記Ｎ型低抵抗コレクタ領
域１３よりも高い抵抗値を有するＮ型エピタキシ
ヤル層１４を形成する工程と、 この工程又は後の工程で前記Ｎ型エピタキシヤ
ル層１４の表面から前記Ｐ型分離領域１２ａに達
するようにＰ型環状分離領域１５ａを前記Ｎ型エ
ピタキシヤル層１４の中に形成し、同時にこの工
程又は後の工程で前記Ｎ型エピタキシヤル層１４
の表面から前記Ｐ型コレクタ領域１２ｂに達する
ようにＰ型環状コレクタ引き出し領域１５ｂを前
記Ｎ型エピタキシヤル層１４の中に形成し、互い
に独立している前記Ｐ型環状分離領域１５ａと前
記Ｐ型コレクタ引き出し領域１５ｂとによつて第
１及び第２のＮ型島状領域１４ａ，１４ｂを生じ
させる工程と、 前記第１のＮ型島状領域１４ａに前記NPN型
トランジスタのＰ型ベース領域１８ａとＮ型エミ
ツタ領域１９とを夫々形成し、前記第２のＮ型島
状領域１４ｂの中に前記PNP型トランジスタの
Ｐ型エミツタ領域１８ｂを形成する工程と、 を含んだ半導体集積回路の製造方法。[Claims] 1. In the N-type semiconductor substrate 11, so as to be surrounded by the N-type semiconductor substrate 11 except for the surface side thereof.
P-type isolation region 12 for NPN-type transistor
forming a P-type collector region 12b for a P-type transistor and a PNP-type transistor; forming an N-type low-resistance collector region 13 on the substrate 11 including the P-type isolation region 12a, the P-type collector region 12b, and the N-type low-resistance collector region 13; A step of forming an N-type epitaxial layer 14 having a higher resistance value than the region 13, and a step of forming a P-type epitaxial layer 14 from the surface of the N-type epitaxial layer 14 to reach the P-type isolation region 12a in this step or a subsequent step. An annular isolation region 15a is formed in the N-type epitaxial layer 14, and at the same time, in this step or in a later step, the N-type epitaxial layer 14 is
A P-type annular collector extraction region 15b is formed in the N-type epitaxial layer 14 so as to reach the P-type collector region 12b from the surface of the P-type annular isolation region 15a and the P-type collector region 15b, which are independent of each other. a step of forming first and second N-type island regions 14a, 14b by forming a collector lead-out region 15b; and forming a P-type base region 18a of the NPN transistor in the first N-type island region 14a; forming N-type emitter regions 19, respectively, and forming a P-type emitter region 18b of the PNP transistor in the second N-type island region 14b.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58068534A JPS59194465A (en) | 1983-04-19 | 1983-04-19 | Manufacture of semiconductor integrated circuit |
| JP2417705A JPH03245562A (en) | 1983-04-19 | 1990-12-14 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58068534A JPS59194465A (en) | 1983-04-19 | 1983-04-19 | Manufacture of semiconductor integrated circuit |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2417705A Division JPH03245562A (en) | 1983-04-19 | 1990-12-14 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59194465A JPS59194465A (en) | 1984-11-05 |
| JPH0425706B2 true JPH0425706B2 (en) | 1992-05-01 |
Family
ID=13376494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58068534A Granted JPS59194465A (en) | 1983-04-19 | 1983-04-19 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59194465A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0618203B2 (en) * | 1986-03-14 | 1994-03-09 | 三洋電機株式会社 | Method for manufacturing vertical PNP transistor |
| IT1218230B (en) * | 1988-04-28 | 1990-04-12 | Sgs Thomson Microelectronics | PROCEDURE FOR THE FORMATION OF AN INTEGRATED CIRCUIT ON A TYPE N SUBSTRATE, INCLUDING VERTICAL PNP AND NPN TRANSISTORS AND ISOLATED BETWEEN THEM |
| JPH0276843U (en) * | 1988-12-01 | 1990-06-13 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5252374A (en) * | 1976-06-21 | 1977-04-27 | Sony Corp | Semiconductor device |
-
1983
- 1983-04-19 JP JP58068534A patent/JPS59194465A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5252374A (en) * | 1976-06-21 | 1977-04-27 | Sony Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59194465A (en) | 1984-11-05 |
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