JPH04249421A - Output simultaneous operation attenuating circuit - Google Patents
Output simultaneous operation attenuating circuitInfo
- Publication number
- JPH04249421A JPH04249421A JP3015066A JP1506691A JPH04249421A JP H04249421 A JPH04249421 A JP H04249421A JP 3015066 A JP3015066 A JP 3015066A JP 1506691 A JP1506691 A JP 1506691A JP H04249421 A JPH04249421 A JP H04249421A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- waveform
- circuits
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
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- Logic Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は回路の出力同時動作を低
減する回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for reducing simultaneous output operations of a circuit.
【０００２】0002
【従来の技術】一般に、複数個の出力端子を持った集積
回路においては、内部回路のタイミングにより出力端子
の信号が同時に変化する場合がある。この場合は、個々
の信号変化で発生するノイズが同じタイミングで重なり
合うため、ノイズの波高値が高くなり、このノイズ波高
値が内部回路のしきい値を超える場合には、内部回路の
誤動作をひき起こすことになる。2. Description of the Related Art Generally, in an integrated circuit having a plurality of output terminals, signals at the output terminals may change simultaneously depending on internal circuit timing. In this case, the noise generated by individual signal changes overlaps at the same timing, so the peak value of the noise increases, and if this noise peak value exceeds the threshold of the internal circuit, it may cause malfunction of the internal circuit. I'll wake you up.
【０００３】0003
【発明が解決しようとする課題】従来では、図６に示す
ように、入力端子Ｇ，Ｈにランダムな入力信号が入った
場合には、第１の内部回路１６の出力端子Ｇ１と第２の
内部回路１７の出力端子Ｈ１とに出力される信号が同時
動作を起こす場合があり、出力信号変化時のノイズ波高
値が大きくなる欠点を有していた。Conventionally, as shown in FIG. 6, when random input signals are input to the input terminals G and H, the output terminal G1 of the first internal circuit 16 and the second This has the disadvantage that the signal output to the output terminal H1 of the internal circuit 17 may operate simultaneously, and the noise peak value increases when the output signal changes.
【０００４】即ち、このような従来の回路では、入力端
子ＧとＨに入力されるべき入力信号がランダムであった
場合には、出力端子Ｇ１とＨ１に出力される信号が同時
動作を起こす場合がある。これは、内部回路にてノイズ
発生の原因となり、内部回路のしきい値に影響を与え、
ひいては誤動作を起こす危険性がある。That is, in such a conventional circuit, if the input signals to be input to the input terminals G and H are random, the signals output to the output terminals G1 and H1 may operate simultaneously. There is. This causes noise generation in the internal circuit and affects the threshold of the internal circuit.
Furthermore, there is a risk of malfunction.
【０００５】本発明の目的は、前記欠点を解決し、出力
信号変化時のノイズ波高値を小さくした出力同時動作低
減回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an output simultaneous operation reduction circuit which solves the above-mentioned drawbacks and reduces the noise peak value when the output signal changes.
【０００６】[0006]
【課題を解決するための手段】本発明の出力同時動作低
減回路の構成は、Ｎ個の入力端子と前記入力端子にそれ
ぞれ対応して設けられたＮ個の出力端子との間のＮ本の
パスのうち、Ｋ本（Ｎ＞Ｋ）のパスにそれぞれラッチ回
路を設け、（Ｎ−Ｋ）本のパスにそれぞれ遅延回路を設
け、前記遅延回路の入力と出力とを論理構成して前記ラ
ッチ回路の制御入力に接続したことを特徴とする。[Means for Solving the Problems] The configuration of the output simultaneous operation reduction circuit of the present invention is such that N input terminals and N output terminals respectively provided corresponding to the input terminals are connected. Of the paths, a latch circuit is provided for each of K (N>K) paths, a delay circuit is provided for each of (N-K) paths, and the input and output of the delay circuit are logically configured to operate the latch. It is characterized by being connected to the control input of the circuit.
【０００７】[0007]
【実施例】図１は本発明の一実施例の出力同時動作低減
回路を示す回路図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an output simultaneous operation reduction circuit according to an embodiment of the present invention.
【０００８】図１において、本実施例は、パスＡ−Ａ１
（入力端子Ａ−出力端子Ａ１）の間にラッチ回路６のＤ
入力−Ｑ出力を設け、パスＢ−Ｂ１間に遅延回路２を設
け、さらにそのラッチ回路６の制御（Ｇ）を入力端子Ｂ
からの波形と遅延回路２，３とインバータ４とが直列接
続されている回路の出力波形との排他的論理和を回路５
でとることにより、出力同時動作低減回路１を構成して
いる。In FIG. 1, this embodiment has a path A-A1.
D of the latch circuit 6 between (input terminal A - output terminal A1)
An input-Q output is provided, a delay circuit 2 is provided between the path B-B1, and the control (G) of the latch circuit 6 is connected to the input terminal B.
The circuit 5 calculates the exclusive OR of the waveform from the output waveform and the output waveform of the circuit in which the delay circuits 2 and 3 and the inverter 4 are connected in series.
By taking these steps, the output simultaneous operation reduction circuit 1 is configured.
【０００９】次に本実施例について、図２乃至図４も参
照して説明する。Next, this embodiment will be explained with reference to FIGS. 2 to 4.
【００１０】図１乃至図４において、今、遅延回路２，
３の各々の遅延時間Ｔはインバータ４，排他的論理和回
路５，及びラッチ回路６がアクティブ時の遅延時間より
もきわめて大きい値に設定する。In FIGS. 1 to 4, the delay circuits 2,
The delay time T of each of the circuits 3 and 3 is set to a value much larger than the delay time when the inverter 4, the exclusive OR circuit 5, and the latch circuit 6 are active.
【００１１】入力端子Ａ，Ｂに図２に示す様に、ｔ＝０
にて同時に高（Ｈｉｇｈ）レベル（以後“Ｈ”と表す）
から低（Ｌｏｗ）レベル（以後“Ｌ”と表す）に変化す
る波形を入力する時、出力端子Ｂ１の波形は遅延回路２
によりｔ＝Ｔ時間経過後に、“Ｈ”から“Ｌ”に変化す
る。As shown in FIG. 2, at input terminals A and B, t=0.
At the same time, the high level (hereinafter referred to as “H”)
When inputting a waveform that changes from low level to low level (hereinafter referred to as "L"), the waveform of output terminal B1 is output from delay circuit 2.
Therefore, after t=T time elapses, it changes from "H" to "L".
【００１２】また、ラッチ回路６の制御端子Ｇに入力さ
れる信号は、遅延回路２，遅延回路３とインバータ４が
直列接続されている回路の出力と、入力端子Ｂの波形と
の排他的論理和を回路５でとることにより、２Ｔ時間だ
け“Ｌ”のパルス幅を持つ信号となる。出力波形（Ａ１
）は、ｔ＝０ではＧ入力が“Ｈ”にある為、入力波形（
Ａ）が“Ｈ”から“Ｌ”に変化すると同時に、出力波形
（Ａ１）へと出力される。Furthermore, the signal input to the control terminal G of the latch circuit 6 is an exclusive logic of the output of the circuit in which the delay circuit 2, the delay circuit 3, and the inverter 4 are connected in series, and the waveform of the input terminal B. By calculating the sum in circuit 5, a signal having an "L" pulse width for 2T time is obtained. Output waveform (A1
) is the input waveform (
At the same time that A) changes from "H" to "L", the output waveform (A1) is output.
【００１３】よって、出力端子Ａ１，Ｂ１の波形は、遅
延時間Ｔ以上遅れて変化することになる。Therefore, the waveforms of the output terminals A1 and B1 change with a delay of more than the delay time T.
【００１４】次に入力端子Ａの入力信号が入力端子Ｂの
入力信号よりも少し遅れた場合は、図３に示す様に、入
力端子Ａの入力信号はＧ入力が“Ｌ”の期間内に変化す
る。この時の出力端子Ａ１の波形は、ラッチ回路６にて
ラッチされている為、“Ｈ”の状態を維持しており、Ｇ
入力が“Ｌ”から“Ｈ”に立ち上がるｔ＝ｔ′時間経過
後初めて“Ｈ”から“Ｌ”へと変化する。よって出力端
子Ａ１，Ｂ１の波形は遅延時間Ｔ以上遅れて変化するこ
とになる。Next, when the input signal at input terminal A is slightly delayed from the input signal at input terminal B, as shown in FIG. Change. At this time, the waveform of the output terminal A1 is latched by the latch circuit 6, so it maintains the "H" state, and the G
The input changes from "H" to "L" only after the time t=t' has elapsed since the input rises from "L" to "H". Therefore, the waveforms of the output terminals A1 and B1 change with a delay of more than the delay time T.
【００１５】さらに、入力端子Ａの入力信号が入力端子
Ｂの入力信号よりも少し早い場合を、図４に示す。この
場合は、出力端子Ａ１の波形はｔ＝０以前で“Ｈ”から
“Ｌ”に変化し、出力波形Ｂ１の波形はｔ＝Ｔ時間にて
“Ｈ”から“Ｌ”に変化する為に、出力端子Ａ１とＢ１
の波形は遅延時間Ｔ以上遅れて変化することになる。Further, FIG. 4 shows a case where the input signal at input terminal A is a little earlier than the input signal at input terminal B. In this case, the waveform of output terminal A1 changes from "H" to "L" before t = 0, and the waveform of output waveform B1 changes from "H" to "L" at time t = T. , output terminals A1 and B1
The waveform changes with a delay of more than the delay time T.
【００１６】さらに、パスが多数あった場合、本発明の
他の実施例として、図５に示す。Furthermore, another embodiment of the present invention in which there are many paths is shown in FIG.
【００１７】図５において、図１との回路上の相違点は
、インバータ４と排他的論理和回路５とがそれと等価な
回路である一致回路１１，１２に置き換っている点であ
り、さらにラッチ回路１５，ＡＮＤ回路１３を追加した
点である。The difference in circuit between FIG. 5 and FIG. 1 is that the inverter 4 and the exclusive OR circuit 5 are replaced with matching circuits 11 and 12, which are equivalent circuits. Furthermore, a latch circuit 15 and an AND circuit 13 are added.
【００１８】即ち、本実施例の同時動作低減回路１ａの
構成は、遅延回路７，８，９，１０と、一致回路１１，
１２と、ＡＮＤ回路１３と、ラッチ回路１４，１５とを
備えている。That is, the configuration of the simultaneous operation reduction circuit 1a of this embodiment includes delay circuits 7, 8, 9, and 10, and a coincidence circuit 11,
12, an AND circuit 13, and latch circuits 14 and 15.
【００１９】この様な回路構成をとることにより、パス
Ｃ−Ｃ１，Ｄ−Ｄ１と、パスＥ−Ｅ１，Ｆ−Ｆ１との双
方の同時動作を回避できることができ、２端子以上の任
意のパス間の出力同時動作についても、低減することが
できる。By adopting such a circuit configuration, simultaneous operation of both paths C-C1 and D-D1 and paths E-E1 and F-F1 can be avoided, and any path with two or more terminals can be It is also possible to reduce simultaneous output operations between the two.
【００２０】[0020]
【発明の効果】以上説明したように、本発明は、入力信
号がランダムあるいは同時に入力された時にも出力信号
の動作タイミングを変化させることができる為、出力同
時動作数を減らし、ノイズの発生を低減するという効果
を有する。[Effects of the Invention] As explained above, the present invention can change the operation timing of the output signal even when input signals are input randomly or simultaneously, thereby reducing the number of simultaneous output operations and suppressing noise generation. It has the effect of reducing
【図１】本発明の一実施例の出力同時動作低減回路を示
す回路図である。FIG. 1 is a circuit diagram showing an output simultaneous operation reduction circuit according to an embodiment of the present invention.
【図２】図１の一つの動作状態を示すタイミング図であ
る。FIG. 2 is a timing diagram showing one operating state of FIG. 1;
【図３】図１の他の動作状態を示すタイミング図である
。FIG. 3 is a timing diagram showing another operating state of FIG. 1;
【図４】図１のもう一つの動作状態を示すタイミング図
である。FIG. 4 is a timing diagram showing another operating state of FIG. 1;
【図５】本発明の他の実施例の出力同時動作低減回路を
示す回路図である。FIG. 5 is a circuit diagram showing an output simultaneous operation reduction circuit according to another embodiment of the present invention.
【図６】従来の回路を示す回路図である。FIG. 6 is a circuit diagram showing a conventional circuit.
１，１ａ 出力同時動作低減回路部２，３，７，
８，９，１０ 遅延回路６，１４，１５
ラッチ回路
４ インバータ
１３ ＡＮＤ回路
５ 排他的論理和回路
１１，１２ 一致回路
１６，１７ 内部回路
Ａ，Ｂ，Ｃ，Ｄ，Ｅ，Ｆ，Ｇ，Ｈ 入力端子Ａ１
，Ｂ１，Ｃ１，Ｄ１，Ｅ１，Ｆ１，Ｇ１，Ｈ１
出力端子1, 1a Output simultaneous operation reduction circuit section 2, 3, 7,
8, 9, 10 Delay circuit 6, 14, 15
Latch circuit 4 Inverter 13 AND circuit 5 Exclusive OR circuits 11, 12 Match circuits 16, 17 Internal circuits A, B, C, D, E, F, G, H Input terminal A1
, B1, C1, D1, E1, F1, G1, H1
Output terminal
Claims (1)
ぞれ対応して設けられたＮ個の出力端子との間のＮ本の
パスのうち、Ｋ本（Ｎ＞Ｋ）のパスにそれぞれラッチ回
路を設け、（Ｎ−Ｋ）本のパスにそれぞれ遅延回路を設
け、前記遅延回路の入力と出力とを論理構成して前記ラ
ッチ回路の制御入力に接続したことを特徴とする出力同
時位動作低減回路。1. Of the N paths between the N input terminals and the N output terminals provided corresponding to the input terminals, each of the K (N>K) paths is latched. A simultaneous output operation characterized in that a circuit is provided, a delay circuit is provided for each of (N-K) paths, and the input and output of the delay circuit are logically configured and connected to the control input of the latch circuit. reduction circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3015066A JP2901355B2 (en) | 1991-02-06 | 1991-02-06 | Output simultaneous operation reduction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3015066A JP2901355B2 (en) | 1991-02-06 | 1991-02-06 | Output simultaneous operation reduction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04249421A true JPH04249421A (en) | 1992-09-04 |
| JP2901355B2 JP2901355B2 (en) | 1999-06-07 |
Family
ID=11878473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3015066A Expired - Lifetime JP2901355B2 (en) | 1991-02-06 | 1991-02-06 | Output simultaneous operation reduction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2901355B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246026A (en) * | 1987-03-31 | 1988-10-13 | Nec Corp | Cmos buffer circuit |
-
1991
- 1991-02-06 JP JP3015066A patent/JP2901355B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246026A (en) * | 1987-03-31 | 1988-10-13 | Nec Corp | Cmos buffer circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2901355B2 (en) | 1999-06-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990209 |