JPH04249379A - Photovoltaic device and manufacture thereof - Google Patents
Photovoltaic device and manufacture thereofInfo
- Publication number
- JPH04249379A JPH04249379A JP3035423A JP3542391A JPH04249379A JP H04249379 A JPH04249379 A JP H04249379A JP 3035423 A JP3035423 A JP 3035423A JP 3542391 A JP3542391 A JP 3542391A JP H04249379 A JPH04249379 A JP H04249379A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor
- amorphous semiconductor
- photovoltaic device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims description 58
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 35
- 229910052751 metal Inorganic materials 0.000 abstract description 14
- 239000002184 metal Substances 0.000 abstract description 14
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 5
- 238000007738 vacuum evaporation Methods 0.000 abstract description 4
- 229910001220 stainless steel Inorganic materials 0.000 abstract description 3
- 239000010935 stainless steel Substances 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Landscapes
- Photovoltaic Devices (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、絶縁基板上に複数の光
起電力素子が規則的に配置形成されてなる光起電力装置
およびその製法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photovoltaic device in which a plurality of photovoltaic elements are regularly arranged on an insulating substrate, and a method for manufacturing the same.
【0002】0002
【従来の技術】基板上に複数の光起電力素子が規則的に
配置されてなる光起電力装置が知られている。該装置の
各光起電力素子は、基板表面に接して形成された第1の
導電体単位層と、該第1の導電体単位層上その主要部に
形成された非晶質半導体単位層と、該非晶質半導体単位
層上に第1の導電体単位層に対向するように形成された
第2の導電体単位層からなり、基板および各層はそれぞ
れ下記のような物質から構成されている。すなわち、ま
ず基板は、ガラスなどの透光性絶縁基板、あるいは金属
などの不透光性基板上に必要に応じ絶縁膜が形成された
ものからなる。通常透光性絶縁基板が使用され、基板上
に形成される第1の導電体単位層としては、酸化インジ
ウムスズ(ITO)等の透明導電膜が用いられる。第1
の導電体単位層上に形成される非晶質半導体単位層は、
例えばp層、i層およびn層からなるアモルファスシリ
コン(以下a−Siと記す)を積層したものである。非
晶質半導体単位層上に第1の導電体単位層に対向するよ
うに形成された第2の導電体単位層は、Cr、Al、C
u等の導電性金属からなり、通常、第2の導電体単位層
は隣接する光起電力素子の第1の導電体単位層と接続さ
れるように構成されており、それぞれの光起電力素子が
直列に接続されている。なお、必要に応じて保護膜が形
成される。2. Description of the Related Art A photovoltaic device is known in which a plurality of photovoltaic elements are regularly arranged on a substrate. Each photovoltaic element of the device includes a first conductive unit layer formed in contact with the substrate surface, and an amorphous semiconductor unit layer formed on the first conductive unit layer in a main part thereof. , a second conductor unit layer is formed on the amorphous semiconductor unit layer so as to face the first conductor unit layer, and the substrate and each layer are each made of the following materials. That is, first, the substrate is made of a light-transmitting insulating substrate such as glass, or a non-light-transmitting substrate such as metal, on which an insulating film is formed as necessary. Usually, a light-transmitting insulating substrate is used, and a transparent conductive film such as indium tin oxide (ITO) is used as the first conductive unit layer formed on the substrate. 1st
The amorphous semiconductor unit layer formed on the conductor unit layer is
For example, it is a stack of amorphous silicon (hereinafter referred to as a-Si) consisting of a p layer, an i layer, and an n layer. The second conductor unit layer formed on the amorphous semiconductor unit layer to face the first conductor unit layer is composed of Cr, Al, C
The second conductor unit layer is usually configured to be connected to the first conductor unit layer of an adjacent photovoltaic element, and each photovoltaic element are connected in series. Note that a protective film is formed if necessary.
【0003】このような光起電力装置を得るための製造
工程において、各光起電力素子の第2の導電体単位層(
たとえば背面電極)と隣接する光起電力素子の第1の導
電体単位層(たとえば入射電極)とを接続するための方
法としては、(1) a−Si層をメタルマスクにより
、成膜時にパターニングする方法、(2) a−Si層
をレジストパターニングによるエッチングによりパター
ニングする方法、(3) レーザ光によりa−Si層を
カッティングする方法の3つが挙げられる。これらの詳
細は以下に説明する通りである。In the manufacturing process for obtaining such a photovoltaic device, the second conductive unit layer (
The method for connecting the first conductor unit layer (for example, the back electrode) of the adjacent photovoltaic element (for example, the incident electrode) is as follows: (1) patterning the a-Si layer using a metal mask during film formation; (2) a method of patterning the a-Si layer by etching using resist patterning; and (3) a method of cutting the a-Si layer with a laser beam. These details are as explained below.
【0004】従来の光起電力装置の製造方法 (1)
図2は上記 (1)の方法による光起電力装置の断面
図である。この方法では、ガラス基板1を用意し、該基
板表面の全面に真空蒸着法により、一様な厚さのITO
膜を形成する。次いで、所定のパターンが得られるよう
にレジストを塗布した後、塩酸等でITO膜の不要部分
をエッチングして取り去る。次に、塗布したレジストを
除去して所定のパターンのITO膜からなる第1の導電
体パターン、すなわち入射電極2a、2b、2cを得る
。Conventional method for manufacturing a photovoltaic device (1)
FIG. 2 is a sectional view of a photovoltaic device according to the method (1) above. In this method, a glass substrate 1 is prepared, and a uniform thickness of ITO is deposited on the entire surface of the substrate by vacuum evaporation.
Forms a film. Next, after applying a resist to obtain a predetermined pattern, unnecessary portions of the ITO film are removed by etching with hydrochloric acid or the like. Next, the applied resist is removed to obtain a first conductor pattern made of an ITO film in a predetermined pattern, that is, incident electrodes 2a, 2b, and 2c.
【0005】次に、所定パターンに開口が設けられたa
−Si層形成用のメタルマスクを上記基板の表面上第1
の導電体パターンの上に配置し、プラズマCVD法によ
り、p層、i層およびn層からなるa−Si層を所定の
厚みに形成した後、メタルマスクを取り外し、所定パタ
ーンのa−Si層からなる非晶質半導体層4a、4bを
得る。Next, a is provided with openings in a predetermined pattern.
- Place a metal mask for forming the Si layer on the first surface of the substrate.
After forming an a-Si layer consisting of a p layer, an i layer and an n layer to a predetermined thickness by plasma CVD method, the metal mask is removed and the a-Si layer with a predetermined pattern is placed on top of the conductor pattern. Amorphous semiconductor layers 4a and 4b are obtained.
【0006】次に、第2の導電体層形成用のメタルマス
クを上記同様に基板上のa−Siパターンの上に配置し
、真空蒸着法により、例えばCr層を所定の厚みに形成
した後、メタルマスクを取り外し、所定パターンの第2
の導電体として背面電極5a、5b、5cを得る。さら
に、必要に応じ、樹脂等を用い、スクリーン印刷法等に
より保護膜9を形成する。Next, a metal mask for forming a second conductive layer is placed on the a-Si pattern on the substrate in the same manner as above, and a Cr layer, for example, is formed to a predetermined thickness by vacuum evaporation. , remove the metal mask, and remove the second mask of the predetermined pattern.
Back electrodes 5a, 5b, and 5c are obtained as conductors. Furthermore, if necessary, a protective film 9 is formed using a resin or the like by a screen printing method or the like.
【0007】従来の光起電力装置の製造方法 (2)
図3は上記 (2)の方法による光起電力装置の断面
図である。この方法における非晶質半導体パターンの形
成は以下の通りであり、その他は第1の方法と同様であ
る。
すなわち、プラズマCVD法により、p層、i層および
n層からなるa−Si層を第1の導電体パターンの上面
全体に、一様な所定の厚みに形成した後、所定パターン
にレジストを塗布してエッチングを行うことにより不要
部分のa−Siを取り去り、次いでレジストを除去する
ことにより所定パターンのa−Siからなる非晶質半導
体層4a、4bを得る。[0007] Conventional method for manufacturing a photovoltaic device (2)
FIG. 3 is a sectional view of a photovoltaic device according to method (2) above. The formation of an amorphous semiconductor pattern in this method is as follows, and the rest is the same as in the first method. That is, after forming an a-Si layer consisting of a p layer, an i layer, and an n layer to a uniform predetermined thickness over the entire upper surface of the first conductor pattern by plasma CVD method, a resist is applied in a predetermined pattern. By performing etching to remove unnecessary portions of a-Si, and then removing the resist, amorphous semiconductor layers 4a and 4b made of a-Si having a predetermined pattern are obtained.
【0008】従来の光起電力装置の製造方法 (3)
図4は上記 (3)の方法による光起電力装置の断面
図である。この方法における非晶質半導体パターンの形
成は以下の通りであり、その他は第1の方法と同様であ
る。
すなわち、プラズマCVD法により、第1の導電体パタ
ーンの上から該パターンの全面にわたりp層、i層およ
びn層からなるa−Si層を所定の一様な厚みに形成し
た後、またはさらにそのa−Si層の上に所定パターン
の第2の導電体層を形成した後レーザ光を所定個所に照
射することにより、a−Siの一部またはa−Siと第
2の導電体層の各一部を除去し、除去した部分に導電体
を封入し、所定パターンのa−Siからなる非晶質半導
体層4を得る。同図のCはレーザパターニングの穴もし
くは変質部を示している。Conventional method for manufacturing a photovoltaic device (3)
FIG. 4 is a sectional view of a photovoltaic device according to method (3) above. The formation of an amorphous semiconductor pattern in this method is as follows, and the rest is the same as in the first method. That is, after forming an a-Si layer consisting of a p layer, an i layer, and an n layer to a predetermined uniform thickness over the entire surface of the first conductor pattern by plasma CVD, or after forming the a-Si layer to a predetermined uniform thickness, After forming a second conductor layer in a predetermined pattern on the a-Si layer, a part of the a-Si or each of the a-Si and the second conductor layer is irradiated with laser light at a predetermined location. A portion is removed and a conductor is encapsulated in the removed portion to obtain an amorphous semiconductor layer 4 made of a-Si having a predetermined pattern. C in the same figure shows a hole or altered part formed by laser patterning.
【0009】[0009]
【発明が解決しようとする課題】しかしながら、上記従
来技術においては下記のような問題点がある。However, the above prior art has the following problems.
【0010】前記製造方法(1) においては、非晶質
半導体を成膜する際、高温にしなければならないために
、メタルマスクの熱膨張等の要因によってパターンのズ
レやぼけが発生しパターン精度が悪くなり、例えば、図
2に見られるように、a−Siが横に広がり、入射電極
2bと背面電極5bの接続部Aが狭くなって、電気特性
が悪くなってしまう。また、メタルマスクの強度を一定
に保たなければならないために、パターン間隔を狭めて
光起電力素子間の間隔を狭めることや複数の光起電力素
子からなる大型の光起電力装置を得ることが困難になる
。[0010] In the above manufacturing method (1), when forming an amorphous semiconductor film, the temperature must be high, so the pattern may be misaligned or blurred due to factors such as thermal expansion of the metal mask, resulting in poor pattern accuracy. For example, as shown in FIG. 2, the a-Si spreads laterally, the connection part A between the incident electrode 2b and the back electrode 5b becomes narrow, and the electrical characteristics deteriorate. In addition, because the strength of the metal mask must be kept constant, it is necessary to narrow the spacing between the photovoltaic elements by narrowing the pattern spacing, and to obtain a large photovoltaic device consisting of multiple photovoltaic elements. becomes difficult.
【0011】前記製造方法(2) においては、図3に
見られるように、a−Si層のパターニングに用いたレ
ジストを除去する際、a−Si層4a、4bの表面や背
面電極5a、5b、5cを形成する面、および入射電極
2bと背面電極5bとの接続部に異物、例えばレジスト
インキなどの残渣Bが存在し易く、電気特性を悪くする
ので、それを取り除くため洗浄するというような工程が
必要となり、工程が複雑になってしまう。In the manufacturing method (2), as shown in FIG. 3, when removing the resist used for patterning the a-Si layer, the surfaces of the a-Si layers 4a and 4b and the back electrodes 5a and 5b are removed. , 5c, and the connection between the incident electrode 2b and the back electrode 5b, foreign matter, such as residue B of resist ink, is likely to exist and deteriorate the electrical characteristics, so cleaning is required to remove it. This requires additional steps and makes the process complicated.
【0012】前記製造方法(3) においては、レーザ
を用いるため、図4に見られるように、例えば背面電極
5bと入射電極2bとの接続は、レーザによりa−Si
がなくなった部分もしくはレーザで変質させた部分Cに
よりなされることになり、製造に要するコストが高価に
なり、またレーザ強度の調節が困難であるため、大型の
光起電力装置を製造するには不向きである。また、上記
C部に導電体を封入するために接続抵抗が大きくなる。[0012] In the manufacturing method (3), since a laser is used, as shown in FIG.
It is difficult to manufacture a large photovoltaic device because the manufacturing cost is high and it is difficult to adjust the laser intensity. Not suitable. Furthermore, since the conductor is enclosed in the C section, the connection resistance increases.
【0013】したがって、本発明の目的は、非晶質半導
体層のパターニングを容易かつ精密に行うことができる
光起電力装置の製法、並びにこれによって得られるVI
特性の良好な光起電力装置を提供することにある。Therefore, an object of the present invention is to provide a method for manufacturing a photovoltaic device in which patterning of an amorphous semiconductor layer can be carried out easily and precisely, and a VI obtained by the method.
An object of the present invention is to provide a photovoltaic device with good characteristics.
【0014】[0014]
【課題を解決するための手段】本発明者らは、上記目的
を達成すべく、前記従来の製造方法における問題点を子
細に研究した結果、非晶質半導体層、例えばa−Si層
の上に成膜する第2の導電体である背面電極または入射
電極をa−Si層をエッチングするマスクとして用い、
各光起電力素子の第2の導電体(背面電極または入射電
極)とこれに隣接する光起電力素子の第1の導電体(入
射電極または背面電極)との接続は別の工程で第2の電
極上面の第1の電極と対向する部分を覆わない接続電極
を形成して行うようにすれば、従来の光起電力装置にお
ける前記課題が解決でき、しかも従来の光起電力装置よ
りもVI特性が向上した光起電力装置が得られることを
見出し、本発明に到達した。[Means for Solving the Problems] In order to achieve the above object, the present inventors have carefully studied the problems in the conventional manufacturing method and have found that Using the back electrode or the incident electrode, which is the second conductor formed as a film, as a mask for etching the a-Si layer,
The connection between the second conductor (back electrode or incident electrode) of each photovoltaic element and the first conductor (incident electrode or back electrode) of the adjacent photovoltaic element is performed in a separate process. By forming a connection electrode that does not cover the part of the upper surface of the electrode facing the first electrode, the above-mentioned problems in conventional photovoltaic devices can be solved, and the VI is lower than that of conventional photovoltaic devices. The inventors have discovered that a photovoltaic device with improved characteristics can be obtained, and have arrived at the present invention.
【0015】すなわち本発明は、第1に、基板上に複数
の光起電力素子が所定パターンで形成されている光起電
力装置であって、各光起電力素子は、基板に接して形成
された第1の導電体層と、該第1の導電体層の上面主要
部を覆い一端が基板と接するように形成された非晶質半
導体層と、該非晶質半導体層上面の前記第1の導電体層
に対向している部分全体を覆うように形成された第2の
導電体層からなる3層構造を有しており、各光起電力素
子の第2の導電体層と、これに隣接する光起電力素子の
第1の導電体層とは、該第2の導電体層上面の前記第1
の導電体層と対向しない部分を覆いかつ該光起電力素子
の一方の側面を覆って隣接する光起電力素子の第1の導
電体層の非晶質半導体層がその上面に形成されていない
部分の上に重なるように形成された層状の導電性物質か
らなる接続電極によって導電接続されていることを特徴
とする光起電力装置;第2に、前記基板が透光性絶縁基
板であり、前記第1の導電体層が透光性の入射電極であ
り、前記第2の導電体層が不透光性の反射電極である、
上記の光起電力装置;第3に、前記基板が不透光性絶縁
基板であり、前記第1の導電体層が不透光性の反射電極
であり、前記第2の導電体層が透光性の入射電極である
、上記の光起電力装置;第4に、基板上に第1の導電体
単位層群を所定パターンで形成した後、該パターンの上
面全体に一様な厚さの連続層として非晶質半導体層を形
成し、該半導体層の上に第2の導電体単位層群を、その
各単位層が前記第1の導電体パターンを構成する各単位
層と対向する態様となるパターンで形成し、形成された
第2の導電体パターンをレジストとして用いることによ
り非晶質半導体層をエッチングしてパターニングした後
、各第2の導電体単位層上面の前記第1の導電体単位層
と対向しない部分を覆い、この部分を隣接位置の第1の
導電体単位層と接続するための接続電極を形成すること
からなる光起電力装置の製法を提供するものである。That is, the present invention firstly provides a photovoltaic device in which a plurality of photovoltaic elements are formed on a substrate in a predetermined pattern, each photovoltaic element being formed in contact with the substrate. an amorphous semiconductor layer formed to cover the main part of the upper surface of the first conductor layer and have one end in contact with the substrate; It has a three-layer structure consisting of a second conductor layer formed to cover the entire portion facing the conductor layer, and the second conductor layer of each photovoltaic element and the second conductor layer formed to cover the entire portion facing the conductor layer. The first conductor layer of an adjacent photovoltaic element refers to the first conductor layer on the upper surface of the second conductor layer.
The amorphous semiconductor layer of the first conductor layer of the adjacent photovoltaic element is not formed on the upper surface of the photovoltaic element, covering the portion not facing the conductor layer and covering one side of the photovoltaic element. A photovoltaic device characterized in that the photovoltaic device is conductively connected by a connection electrode made of a layered conductive material formed so as to overlap the portion; secondly, the substrate is a translucent insulating substrate; The first conductor layer is a light-transmitting incident electrode, and the second conductor layer is a light-impermeable reflective electrode.
The above photovoltaic device; thirdly, the substrate is a non-transparent insulating substrate, the first conductive layer is a non-transparent reflective electrode, and the second conductive layer is transparent. The above-mentioned photovoltaic device is a light incident electrode; Fourth, after forming the first conductor unit layer group in a predetermined pattern on the substrate, a uniform thickness is formed over the entire upper surface of the pattern. An embodiment in which an amorphous semiconductor layer is formed as a continuous layer, and a second conductor unit layer group is provided on the semiconductor layer, each unit layer of which faces each unit layer constituting the first conductor pattern. After etching and patterning the amorphous semiconductor layer by using the formed second conductor pattern as a resist, the first conductor on the upper surface of each second conductor unit layer is A method for manufacturing a photovoltaic device is provided, which comprises forming a connecting electrode for covering a portion not facing a body unit layer and connecting this portion to a first conductive unit layer at an adjacent position.
【0016】[0016]
【作用】本発明の製造方法では、非晶質半導体層、例え
ばa−Si層の上に成膜される第2の導電体層(背面電
極または入射電極)をa−Si層をエッチングによりパ
ターニングするためのマスクとして用いるので、パター
ンのズレやぼけの発生がなく精密なパターニングができ
る。a−Si層と背面電極層(または入射電極)との間
に異物が混入しない。またエッチングによる低温プロセ
スのパターニングであるため、素子間の間隔を狭めるこ
とができるので複数の素子による大型化が可能となる。
さらに、背面電極(または入射電極)の入射電極(また
は背面電極)と対向しない部分に接続電極を設けるため
、基板から最も遠い位置に配置された導電体層を透明電
極(すなわち入射電極)とする光起電力装置をつくるこ
ともできる。接続電極の形成は銅ペーストや銀ペースト
等を用いて印刷法により行うことができる。また、印刷
法に限らず、スパッタ法、蒸着法等により、クロム、ア
ルミニウム、ニッケル、ITO等を成膜するものでも良
い。接続電極の材質は第2の導電体と同じであっても異
なるものであってもよい。[Operation] In the manufacturing method of the present invention, the second conductor layer (back electrode or incident electrode) formed on the amorphous semiconductor layer, for example, the a-Si layer, is patterned by etching the a-Si layer. Since it is used as a mask for patterning, precise patterning can be performed without pattern shift or blurring. Foreign matter does not get mixed in between the a-Si layer and the back electrode layer (or the incident electrode). Furthermore, since the patterning is performed by a low-temperature process using etching, the spacing between elements can be narrowed, making it possible to increase the size by using a plurality of elements. Furthermore, in order to provide a connection electrode in a portion of the back electrode (or incident electrode) that does not face the incident electrode (or back electrode), the conductive layer placed farthest from the substrate is made a transparent electrode (i.e., incident electrode). It is also possible to create photovoltaic devices. The connection electrode can be formed by a printing method using copper paste, silver paste, or the like. Furthermore, the method is not limited to the printing method, and a film of chromium, aluminum, nickel, ITO, etc. may be formed by a sputtering method, a vapor deposition method, or the like. The material of the connection electrode may be the same as or different from that of the second conductor.
【0017】以下実施例により本発明をさらに説明する
。本発明の光起電力装置は基板と反対側に入射電極をも
つタイプのものの製造に特に好都合であるため、同タイ
プのものを実施例として示す。The present invention will be further explained below with reference to Examples. Since the photovoltaic device of the present invention is particularly suitable for manufacturing a type having an input electrode on the side opposite to the substrate, a similar type is shown as an example.
【0018】[0018]
【実施例1】図1は本発明の一実施例による光起電力装
置の断面図であって、この図を参照して以下説明する。
ステンレス基板1a上にスプレー法によりSiO2 を
10μmの厚みで形成して絶縁膜1bとした。その上に
真空蒸着法によりCrをメタルマスクを用いて1200
A(オングストローム)の厚みで成膜し、第1の導電体
層(背面電極)5a、5b、5cとした。この上に、a
−Si層をプラズマCVD法により、p層 200A、
i層6,000 A、n層 200A堆積させた。得ら
れたa−Si層の上に第2の導電体層(入射電極)とa
−Siエッチング用のマスクとを兼ねるITO膜を室温
にて真空蒸着法によりメタルマスクを用いながら 90
0Aの厚みに形成して、第2の導電体層(入射電極)と
し、これを60℃、10wt%のNaOH溶液中に5分
間浸漬し、ITO膜が形成されていない部分のa−Si
層をエッチングしてa−Si層を4aと4bに分割した
後、水洗、乾燥した。次いでCuペーストを所定個所に
印刷し、 150℃で10分間焼成して、前記第2の導
電体層と、隣接する素子の第1の導電体層とを接続する
ための接続電極7a、7b、7cを形成した。さらに、
保護膜9aとして、透明樹脂を印刷して 150℃で1
0分間焼成した。Embodiment 1 FIG. 1 is a sectional view of a photovoltaic device according to an embodiment of the present invention, and the following description will be made with reference to this figure. An insulating film 1b was formed by forming SiO2 to a thickness of 10 μm on a stainless steel substrate 1a by a spray method. On top of that, 1200% Cr was applied using a metal mask using a vacuum evaporation method.
A film was formed to a thickness of A (angstrom) to form the first conductor layers (back electrodes) 5a, 5b, and 5c. On top of this, a
-Si layer is formed by plasma CVD method, p layer 200A,
The i layer was deposited at 6,000 amps, and the n layer was deposited at 200 amps. On the obtained a-Si layer, a second conductive layer (incident electrode) and a
- An ITO film that also serves as a mask for Si etching is deposited at room temperature using a metal mask using a vacuum evaporation method 90
The second conductor layer (incidence electrode) was formed to a thickness of 0A, and was immersed in a 10wt% NaOH solution at 60°C for 5 minutes to remove the a-Si in the part where the ITO film was not formed.
After etching the layer and dividing the a-Si layer into 4a and 4b, it was washed with water and dried. Next, Cu paste is printed on a predetermined location and baked at 150° C. for 10 minutes to form connection electrodes 7a, 7b for connecting the second conductor layer and the first conductor layer of an adjacent element. 7c was formed. moreover,
As the protective film 9a, a transparent resin was printed and heated at 150°C.
Baked for 0 minutes.
【0019】上記の方法で作製した光起電力装置にソー
ラーシュミレータによる疑似太陽光を照射させ、VI特
性を測定した結果、図5の実線で示すような特性曲線が
得られた。なお、比較のために、メタルマスクを用いて
a−Si層の形成とパターニングを同時に行う従来の方
法での光起電力装置も作製し、上記と同様の条件で測定
を行ったところ、同図の点線で示す曲線が得られた。The photovoltaic device produced by the above method was irradiated with simulated sunlight using a solar simulator, and the VI characteristics were measured. As a result, a characteristic curve as shown by the solid line in FIG. 5 was obtained. For comparison, we also fabricated a photovoltaic device using the conventional method of simultaneously forming and patterning an a-Si layer using a metal mask, and measured it under the same conditions as above. A curve shown by the dotted line was obtained.
【0020】図5からわかるように、本発明の光起電力
装置は、従来法で得た光起電力装置と比較して、同数の
同じ大きさの光起電力素子からなる光起電力装置であっ
ても、VI特性が向上している。なお上記の測定は、A
M(エアマス)1.0 、疑似太陽光の入射強度 10
0mW(ミリワット)/cm2 の場合に、セル面積1
cm2 、セルギャップ 1.6mm、セル幅5mm、
セル数4セルの光起電力装置に対して行った測定値であ
る。As can be seen from FIG. 5, the photovoltaic device of the present invention is a photovoltaic device consisting of the same number of photovoltaic elements of the same size, compared to the photovoltaic device obtained by the conventional method. Even if there is, the VI characteristics are improved. In addition, the above measurement is
M (air mass) 1.0, incident intensity of simulated sunlight 10
In the case of 0 mW (milliwatt)/cm2, the cell area 1
cm2, cell gap 1.6mm, cell width 5mm,
These are measurement values performed on a photovoltaic device having 4 cells.
【0021】[0021]
【実施例2】接続電極として、真空蒸着によりAlをメ
タルマスク法でパターン形成させながら 1,200A
の厚さに成膜したこと以外は実施例1と同様にして光起
電力装置を製造した。実施例1のものと同様に良好な特
性を持つ光起電力装置が得られた。[Example 2] As a connection electrode, 1,200A was formed by patterning Al using a metal mask method using vacuum evaporation.
A photovoltaic device was manufactured in the same manner as in Example 1 except that the film was formed to a thickness of . A photovoltaic device having good characteristics similar to those of Example 1 was obtained.
【0022】[0022]
【発明の効果】以上説明したように、本発明の光起電力
装置は、その非晶質半導体層が、高温環境下でパターニ
ングされるものではないために、その製造に際しては非
晶質半導体層のパターニングを容易かつ精密に行うこと
ができ、また光起電力素子の間隔を狭めて、多数の光起
電力素子を直列に接続した大型の光起電力装置の製造も
可能である。また第2の導電体単位層の第1の導電体単
位層と対向しない部分に接続電極を設けることにより、
基板表面から遠い位置に設けた導電体層を入射電極とす
ることができる。上記のパターニングの効果とともに、
従来例よりもVI特性が向上した光起電力装置とするこ
とができる。As explained above, in the photovoltaic device of the present invention, the amorphous semiconductor layer is not patterned in a high-temperature environment. patterning can be performed easily and precisely, and it is also possible to manufacture a large-sized photovoltaic device in which a large number of photovoltaic elements are connected in series by narrowing the spacing between the photovoltaic elements. Furthermore, by providing a connection electrode in a portion of the second conductor unit layer that does not face the first conductor unit layer,
A conductor layer provided at a position far from the substrate surface can be used as an incident electrode. Along with the above patterning effect,
A photovoltaic device with improved VI characteristics than the conventional example can be obtained.
【図1】本発明の1実施例における光起電力装置の断面
図である。FIG. 1 is a cross-sectional view of a photovoltaic device in one embodiment of the present invention.
【図2】a−Si層をメタルマスクによりパターニング
した従来の光起電力装置の断面図である。FIG. 2 is a cross-sectional view of a conventional photovoltaic device in which an a-Si layer is patterned using a metal mask.
【図3】a−Si層をレジストによりパターニングした
従来の光起電力装置の断面図である。FIG. 3 is a cross-sectional view of a conventional photovoltaic device in which an a-Si layer is patterned with a resist.
【図4】a−Si層をレーザ光によりパターニングした
従来の光起電力装置の断面図である。FIG. 4 is a cross-sectional view of a conventional photovoltaic device in which an a-Si layer is patterned by laser light.
【図5】本発明の光起電力装置および従来の光起電力装
置のVI特性を測定したグラフであり、実線は本発明、
点線は従来例の特性曲線である。FIG. 5 is a graph showing measured VI characteristics of the photovoltaic device of the present invention and the conventional photovoltaic device, with solid lines indicating the present invention and the conventional photovoltaic device.
The dotted line is the characteristic curve of the conventional example.
1 ガラス基板1
a、 ステンレス基板1b
絶縁膜2a、2b、
2c 入射電極
3a、3b a−Si層のパターニ
ング用マスクを兼ねる入射電極
4、4a、4b 非晶質半導体層5a、5b
、5c 背面電極
7a、7b、7c 接続電極
9、9a 保護膜A
接続部B
レジストインキなどの残渣C
レーザパターニング
の穴もしくは変質部1 Glass substrate 1
a. Stainless steel substrate 1b
Insulating films 2a, 2b,
2c Input electrodes 3a, 3b Input electrodes 4, 4a, 4b which also serve as masks for patterning the a-Si layer Amorphous semiconductor layers 5a, 5b
, 5c Back electrodes 7a, 7b, 7c Connection electrodes 9, 9a Protective film A
Connection part B
Residues such as resist ink C
Holes or altered parts of laser patterning
Claims (3)
ターンで形成されている光起電力装置であって、各光起
電力素子は、基板に接して形成された第1の導電体層と
、該第1の導電体層の上面主要部を覆い一端が基板と接
するように形成された非晶質半導体層と、該非晶質半導
体層上面の前記第1の導電体層に対向している部分全体
を覆うように形成された第2の導電体層からなる3層構
造を有しており、各光起電力素子の第2の導電体層と、
これに隣接する光起電力素子の第1の導電体層とは、該
第2の導電体層上面の前記第1の導電体層と対向しない
部分を覆いかつ該光起電力素子の一方の側面を覆って隣
接する光起電力素子の第1の導電体層の非晶質半導体層
がその上面に形成されていない部分の上に重なるように
形成された層状の導電性物質からなる接続電極によって
導電接続されていることを特徴とする光起電力装置。1. A photovoltaic device in which a plurality of photovoltaic elements are formed in a predetermined pattern on a substrate, wherein each photovoltaic element has a first conductive layer formed in contact with the substrate. an amorphous semiconductor layer formed to cover the main part of the upper surface of the first conductor layer and have one end in contact with the substrate; and an amorphous semiconductor layer that faces the first conductor layer on the upper surface of the amorphous semiconductor layer. It has a three-layer structure consisting of a second conductor layer formed to cover the entire part of the photovoltaic element, and the second conductor layer of each photovoltaic element;
The first conductive layer of the photovoltaic element adjacent to this is defined as covering the upper surface of the second conductive layer that does not face the first conductive layer and covering one side surface of the photovoltaic element. By means of a connecting electrode made of a layered conductive material, which is formed so as to cover the part of the first conductive layer of the adjacent photovoltaic element that is not formed on the top surface of the amorphous semiconductor layer. A photovoltaic device characterized in that it is electrically conductively connected.
前記第1の導電体層が不透光性の反射電極であり、前記
第2の導電体層が透光性の入射電極である、請求項1記
載の光起電力装置。2. The substrate is a non-transparent insulating substrate,
2. The photovoltaic device according to claim 1, wherein the first conductive layer is a non-transparent reflective electrode and the second conductive layer is a transparent incident electrode.
パターンで形成した後、該パターンの上面全体に一様な
厚さの連続層として非晶質半導体層を形成し、該半導体
層の上に第2の導電体単位層群を、その各単位層が前記
第1の導電体パターンを構成する各単位層と対向する態
様となるパターンで形成し、形成された第2の導電体パ
ターンをレジストとして用いることにより非晶質半導体
層をエッチングしてパターニングした後、各第2の導電
体単位層上面の前記第1の導電体単位層と対向しない部
分を覆い、この部分を隣接位置の第1の導電体単位層と
接続するための接続電極を形成することからなる光起電
力装置の製法。3. After forming a first conductor unit layer group in a predetermined pattern on a substrate, an amorphous semiconductor layer is formed as a continuous layer with a uniform thickness over the entire upper surface of the pattern, and A second conductor unit layer group formed on the layer is formed in a pattern in which each unit layer faces each unit layer constituting the first conductor pattern. After etching and patterning the amorphous semiconductor layer by using the body pattern as a resist, a portion of the upper surface of each second conductive unit layer that does not face the first conductive unit layer is covered, and this portion is made adjacent to the top surface of the second conductive unit layer. A method for manufacturing a photovoltaic device comprising forming a connecting electrode for connecting with a first conductor unit layer at a position.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3035423A JPH04249379A (en) | 1991-02-05 | 1991-02-05 | Photovoltaic device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3035423A JPH04249379A (en) | 1991-02-05 | 1991-02-05 | Photovoltaic device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04249379A true JPH04249379A (en) | 1992-09-04 |
Family
ID=12441465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3035423A Pending JPH04249379A (en) | 1991-02-05 | 1991-02-05 | Photovoltaic device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04249379A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008083641A (en) * | 2006-09-29 | 2008-04-10 | Furukawa Electric Co Ltd:The | Linear condensing lens, solar battery element using the same, and solar battery module |
DE102016002213A1 (en) | 2015-02-26 | 2016-11-03 | Dynamic Solar Systems Ag | PV layer sequence obtained by a room temperature method and room temperature method for producing a PV layer sequence |
US10892160B2 (en) | 2015-02-26 | 2021-01-12 | Dynamic Solar Systems Ag | Method for producing electrotechnical thin layers at room temperature, and electrotechnical thin layer |
-
1991
- 1991-02-05 JP JP3035423A patent/JPH04249379A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008083641A (en) * | 2006-09-29 | 2008-04-10 | Furukawa Electric Co Ltd:The | Linear condensing lens, solar battery element using the same, and solar battery module |
DE102016002213A1 (en) | 2015-02-26 | 2016-11-03 | Dynamic Solar Systems Ag | PV layer sequence obtained by a room temperature method and room temperature method for producing a PV layer sequence |
US10892160B2 (en) | 2015-02-26 | 2021-01-12 | Dynamic Solar Systems Ag | Method for producing electrotechnical thin layers at room temperature, and electrotechnical thin layer |
US11935976B2 (en) | 2015-02-26 | 2024-03-19 | Dynamic Solar Systems Ag | Room temperature method for the production of electrotechnical thin layers, and a thin layer sequence obtained following said method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0195148B1 (en) | Photovoltaic device and method of manufacture | |
JP5270658B2 (en) | Photovoltaic device having discontinuous heterojunction structure meshing with each other | |
CN101904014B (en) | Thin film type solar cell and method for manufacturing the same | |
KR100614456B1 (en) | Display substrate electrodes with auxiliary metal layers for enhanced conductivity | |
US4623751A (en) | Photovoltaic device and its manufacturing method | |
US10236398B2 (en) | Method for manufacturing transparent electrode | |
US4824488A (en) | Photovoltaic device | |
US4542578A (en) | Method of manufacturing photovoltaic device | |
TWI478368B (en) | A method for manufacturing a thin film type solar cell | |
US5147468A (en) | Photovoltaic semiconductor device and method for manufacturing the same | |
JPH0851229A (en) | Integrated solar battery and its manufacture | |
JPH04249379A (en) | Photovoltaic device and manufacture thereof | |
JPS61116883A (en) | Transparent electrode with metal wiring | |
JPH04249378A (en) | Photovoltaic device and manufacture thereof | |
US8273597B2 (en) | Process for making solar panel and the solar panel made thereof | |
JPS639755B2 (en) | ||
KR101789295B1 (en) | Method for manufacturing transparent electrode | |
JPS6095978A (en) | Photoelectric conversion semiconductor device | |
JPH0558585B2 (en) | ||
JPH04320380A (en) | Manufacture of solar cell | |
JPS6085577A (en) | Manufacture of thin film photoelectric conversion element | |
JPS62137873A (en) | Manufacture of photoelectric conversion device | |
JPH067598B2 (en) | Solar cell manufacturing method | |
JPH0382169A (en) | Manufacture of amorphous solar cell | |
JPH09321328A (en) | Manufacture of photoelectric converter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19990629 |