JPH04217323A - Manufacture of bump electrode for semiconductor device - Google Patents
Manufacture of bump electrode for semiconductor deviceInfo
- Publication number
- JPH04217323A JPH04217323A JP2403400A JP40340090A JPH04217323A JP H04217323 A JPH04217323 A JP H04217323A JP 2403400 A JP2403400 A JP 2403400A JP 40340090 A JP40340090 A JP 40340090A JP H04217323 A JPH04217323 A JP H04217323A
- Authority
- JP
- Japan
- Prior art keywords
- base film
- bump electrode
- metal
- film
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 58
- 239000002184 metal Substances 0.000 claims abstract description 58
- 238000007747 plating Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000009713 electroplating Methods 0.000 claims abstract description 19
- 238000003486 chemical etching Methods 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 239000002131 composite material Substances 0.000 claims abstract description 5
- 150000002739 metals Chemical class 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 47
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims 1
- 238000005260 corrosion Methods 0.000 abstract description 15
- 230000007797 corrosion Effects 0.000 abstract description 15
- 239000010408 film Substances 0.000 description 128
- 239000000758 substrate Substances 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002905 metal composite material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- -1 solder Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は集積回路装置等の半導体
装置のチップを外部と接続するためのバンプ電極の製造
方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing bump electrodes for connecting chips of semiconductor devices such as integrated circuit devices to the outside.
【０００２】0002
【従来の技術】よく知られているように、集積回路装置
等の半導体装置を種々の配線基板等に実装するための手
段ないし構造として、そのチップを一旦パッケージに収
納した上で実装する場合と、バンプ電極を備えるフリッ
プチップの形で実装する場合とがあり、量産される電子
回路や電子装置には後者の方が実装スペースを縮小して
全体のサイズを小形化でき、かつ実装の手間を省ける点
で優れている。フリップチップのバンプ電極にははんだ
，Ｃｕ，Ａｕ等の金属が用いられ、そのサイズも色々で
あるが、いずれの場合もバンプ電極用の金属はフリップ
チップに単離する前のウエハの状態で電解めっき法によ
り成長される。本発明はＣｕやＡｕを用いる場合に適す
るバンプ電極に関し、以下にその従来の代表的な製造方
法を図２を参照して簡単に説明する。2. Description of the Related Art As is well known, as a means or structure for mounting semiconductor devices such as integrated circuit devices on various wiring boards, etc., there are two methods for mounting semiconductor devices such as integrated circuit devices on various wiring boards, etc. In some cases, it is mounted in the form of a flip chip with bump electrodes, and for mass-produced electronic circuits and electronic devices, the latter can reduce the mounting space, reduce the overall size, and reduce the mounting effort. It's great because it saves money. Metals such as solder, Cu, and Au are used for the bump electrodes of flip chips, and their sizes vary, but in all cases, the metal for the bump electrodes is electrolyzed in the wafer state before it is isolated into flip chips. Grown by plating method. The present invention relates to a bump electrode suitable for using Cu or Au, and a typical conventional manufacturing method thereof will be briefly explained below with reference to FIG. 2.
【０００３】図２は半導体ウエハないし基板１内のごく
一部のバンプ電極が設けられる部分の主な工程ごとの状
態を断面で示すものである。同図（ａ） に示す状態で
は基板１の表面が燐シリケートガラス等の酸化膜２で覆
われ、その上に接続ないしは配線用のアルミ等の金属膜
３が所定のパターンで配設され、さらにその上を覆う窒
化シリコン等のいわゆる保護膜である絶縁膜４に小さな
窓５が明けられ、この窓５を介して金属膜３に接続され
るバンプ電極を設けるために薄い下地膜１０がウエハの
全面に被着されている。この下地膜１０はもちろん金属
膜であり、バンプ電極をその上に電解めっき法で成長さ
せる都合上からＴｉ等の下側下地膜１１とＣｕやＰｄ等
の上側下地膜１２からなる複合膜とされる。FIG. 2 is a cross-sectional view showing the state of a small portion of a semiconductor wafer or substrate 1 where bump electrodes are provided at each major step. In the state shown in FIG. 1(a), the surface of the substrate 1 is covered with an oxide film 2 such as phosphorus silicate glass, on which a metal film 3 such as aluminum for connection or wiring is disposed in a predetermined pattern. A small window 5 is formed in the insulating film 4, which is a so-called protective film such as silicon nitride, covering the insulating film 4, and a thin base film 10 is formed on the wafer in order to provide a bump electrode connected to the metal film 3 through this window 5. Covered all over. This base film 10 is of course a metal film, and in order to grow bump electrodes thereon by electrolytic plating, it is made into a composite film consisting of a lower base film 11 such as Ti and an upper base film 12 such as Cu or Pd. Ru.
【０００４】同図（ｂ） の工程では、この内の上側下
地膜１２がフォトレジスト膜１３をマスクとしてバンプ
電極用の方形や円形のパターンにエッチングされる。次
の同図（ｃ） がバンプ電極の成長工程であって、上の
ようにパターンニングされた上側下地膜１２のみを露出
させるよう別のフォトレジスト膜２１をフォトプロセス
で形成し、これをマスクとする電解めっき法によってバ
ンプ電極用のＣｕやＡｕ等の金属２０を例えば数十μｍ
程度の高さに成長させる。この際、下側下地膜１１をウ
エハ全面に対するめっき電極に用い、これをめっき電源
の陰極に接続した状態で電解めっきを施すことによりウ
エハ内の多数個所にバンプ電極用金属２０を同時成長さ
せる。In the step shown in FIG. 2B, the upper base film 12 is etched into a rectangular or circular pattern for a bump electrode using the photoresist film 13 as a mask. The next figure (c) shows the growth process of the bump electrode, in which another photoresist film 21 is formed by a photo process so as to expose only the upper base film 12 patterned as above, and this is covered with a mask. The metal 20, such as Cu or Au, for bump electrodes is coated with a thickness of several tens of μm, for example, by electrolytic plating.
grow to a certain height. At this time, the lower base film 11 is used as a plating electrode for the entire surface of the wafer, and electrolytic plating is performed while it is connected to the cathode of a plating power source, thereby simultaneously growing bump electrode metal 20 at multiple locations within the wafer.
【０００５】最後の同図（ｄ） の工程では、フォトレ
ジスト膜２１を除去した後にバンプ電極用金属２０をマ
スクとする化学エッチング法によって下側下地膜１１を
除去して図示の完成状態とする。なお、下地膜１０中の
下側下地膜１１は上述のめっき電極膜として利用される
ほか、金属膜３のアルミ等がバンプ電極の方に拡散する
のを防止するバリア膜の役目を兼ね、上側下地膜１２は
バンプ電極用金属２０をこの下側下地膜１１に対してバ
ンプ電極の比較的細い付け根の個所で低い抵抗値および
高い機械強度で接続する役目を果たす。In the final step shown in FIG. 4(d), after removing the photoresist film 21, the lower base film 11 is removed by chemical etching using the bump electrode metal 20 as a mask, resulting in the completed state shown in the figure. . Note that the lower base film 11 in the base film 10 is used as the above-mentioned plating electrode film, and also serves as a barrier film to prevent aluminum, etc. of the metal film 3 from diffusing toward the bump electrodes. The base film 12 serves to connect the bump electrode metal 20 to the lower base film 11 at a relatively narrow base of the bump electrode with a low resistance value and high mechanical strength.
【０００６】[0006]
【発明が解決しようとする課題】周知のように、半導体
装置の製造コストはウエハに対するフォトプロセス回数
により大きく左右されるが、図２の従来のバンプ電極の
製造方法では同図（ｂ） の上側下地膜１２のエッチン
グ用と同図（ｃ） の電解めっきのマスク用のパターン
形成のため計２回のフォトプロセスが必要なので、フリ
ップチップの製造合理化にはこの回数をできるだけ１回
に減らしたい要求がある。従来技術がもつもう一つの問
題点はバンプ電極の付け根の個所でトラブルが発生しや
すいことであり、これを図２（ｄ） の完成状態の一部
拡大断面図である図３を参照して説明する。[Problems to be Solved by the Invention] As is well known, the manufacturing cost of semiconductor devices is largely influenced by the number of photoprocesses performed on the wafer, but in the conventional bump electrode manufacturing method shown in FIG. Since a total of two photo processes are required, one for etching the base film 12 and the other for forming the pattern for the electrolytic plating mask shown in FIG. There is. Another problem with the conventional technology is that troubles tend to occur at the base of the bump electrode. explain.
【０００７】図３（ａ） に示すように、トラブルの一
つは上側下地膜１２がとくにＣｕの場合その周面が露出
しているため高温多湿条件下で腐食を生じやすいことで
あって、図のＣ１のように腐食のため膨れて脱落しやす
くなったり、Ｃ２のように腐食個所が欠落してバンプ電
極の付け根の機械強度が低下したりする問題点がある。
もう一つのトラブルは同図（ｂ） に示すように下側下
地膜１１にオーバエッチングＥが発生してバンプ電極の
付け根の機械強度が低下し、あるいは金属膜３との接続
抵抗が増加することがある点であって、図のように金属
膜３を介し基板１に接続されているバンプ電極でこのオ
ーバエッチングＥが発生しやすい。これは、化学エッチ
ングの際にエッチング液が基板１に当然触れるので、下
側下地膜１２と基板１との間の抵抗の大小により電気化
学的な条件が異なり、この抵抗が小さな下側下地膜１２
に対するエッチングが促進されるものと考えられる。換
言すれば、下側下地膜１２に対するエッチング速度には
ウエハ面内でばらつきが出るため、エッチング速度の遅
い個所の下側下地膜１２を取り切ろうとすると、早い個
所ではオーバエッチングが発生してしまうのである。As shown in FIG. 3(a), one of the problems is that, especially when the upper base film 12 is made of Cu, its peripheral surface is exposed, so corrosion is likely to occur under high temperature and high humidity conditions. As shown in C1 in the figure, the bump electrode swells and easily falls off due to corrosion, and as shown in C2, the corroded area is missing and the mechanical strength of the base of the bump electrode decreases. Another problem is that over-etching E occurs in the lower base film 11, as shown in FIG. 2(b), which reduces the mechanical strength of the base of the bump electrode or increases the connection resistance with the metal film 3. At a certain point, this over-etching E tends to occur at the bump electrode connected to the substrate 1 via the metal film 3 as shown in the figure. This is because the etching solution naturally comes into contact with the substrate 1 during chemical etching, so the electrochemical conditions differ depending on the resistance between the lower base film 12 and the substrate 1, and the lower base film has a lower resistance. 12
It is thought that etching is promoted. In other words, the etching rate for the lower base film 12 varies within the wafer surface, so if an attempt is made to remove the lower base film 12 at a location where the etching rate is slow, over-etching will occur at a location where the etching rate is fast. It is.
【０００８】本発明の主な目的はかかる問題点を解決し
て、フリップチップの製造コストを低減でき、かつバン
プ電極の付け根個所における下側下地膜のオーバエッチ
ングを防止できる半導体装置用バンプ電極の製造方法を
提供することにある。また、本発明の従たる目的はバン
プ電極の付け根個所における上側下地膜の腐食を防止す
ることにある。The main object of the present invention is to solve these problems and provide a bump electrode for a semiconductor device that can reduce the manufacturing cost of a flip chip and prevent over-etching of the lower base film at the root of the bump electrode. The purpose is to provide a manufacturing method. A further object of the present invention is to prevent corrosion of the upper base film at the base of the bump electrode.
【０００９】[0009]
【課題を解決するための手段】本発明方法によればこの
目的は、バンプ電極を接続すべき金属膜部分が絶縁膜に
明けられた窓内に露出されたウエハに対して、少なくと
も２種の金属の複合膜としてなる下地膜を全面被着する
工程と、下地膜をめっき電極としてバンプ電極用金属を
電解めっきにより絶縁膜の窓部上に選択的に成長させる
工程と、バンプ電極用金属をマスクとするエッチングに
より上側下地膜を除去する工程と、下側下地膜をドライ
エッチング法により除去する工程とを順次経由してバン
プ電極を設けることにより達成される。[Means for Solving the Problems] According to the method of the present invention, the object is to provide at least two types of A process of depositing a base film as a metal composite film on the entire surface, a process of selectively growing the metal for the bump electrode on the window part of the insulating film by electrolytic plating using the base film as a plating electrode, and a process of selectively growing the metal for the bump electrode on the window part of the insulating film using the base film as a plating electrode. This is achieved by providing the bump electrode through sequential steps of removing the upper base film by etching using a mask and removing the lower base film by dry etching.
【００１０】なお、本発明方法によるバンプ電極用金属
には前述のようにＡｕとＣｕのいずれかを用いるのが好
適である。As mentioned above, it is preferable to use either Au or Cu as the metal for the bump electrode according to the method of the present invention.
【００１１】また、上側下地膜の除去工程には化学エッ
チング法を用いるのが好適であり、バンプ電極用金属が
Ｃｕ等の腐食されやすい金属の場合はこの化学エッチン
グ時の腐食を防止するため、それを電解めっきにより成
長させた表面にＡｕ等の耐食性の高い金属のめっき膜に
より２μｍ程度以上の膜厚で覆って置くのが望ましい。[0011] Furthermore, it is preferable to use a chemical etching method in the step of removing the upper base film, and if the metal for the bump electrode is a metal that is easily corroded such as Cu, in order to prevent corrosion during this chemical etching, It is desirable that the surface grown by electrolytic plating be covered with a plating film of a highly corrosion-resistant metal such as Au with a film thickness of approximately 2 μm or more.
【００１２】さらに、バンプ電極の付け根個所における
上側下地膜の腐食を防止するには、上側下地膜の除去工
程の後に残る下側下地膜をめっき電極としてＡｕ等の耐
食性の高い金属をバンプ電極用金属と上側下地膜の被エ
ッチング面とに電解めっきする工程を挿入するのが非常
に有効であり、このＡｕめっきの厚みは２μｍ以上とす
るのが望ましい。Furthermore, in order to prevent corrosion of the upper base film at the base of the bump electrode, the lower base film remaining after the removal process of the upper base film is used as a plating electrode, and a highly corrosion-resistant metal such as Au is used for the bump electrode. It is very effective to insert an electrolytic plating process between the metal and the surface to be etched of the upper base film, and it is desirable that the thickness of this Au plating is 2 μm or more.
【００１３】なお、下側下地膜用金属にはＴｉとＣｒの
いずれかを用い、上側下地膜用金属にはＣｕ， Ｐｄ，
ＮｉおよびＡｕのいずれかを単独にないしはそれらを
組み合わせて用いるのがよく、場合によっては両側下地
膜の相互間にＷ等からなる中間膜を介在させるのが望ま
しい。[0013] The metal for the lower base film is either Ti or Cr, and the metal for the upper base film is Cu, Pd,
It is preferable to use either Ni or Au alone or in combination, and in some cases it is desirable to interpose an intermediate film made of W or the like between the base films on both sides.
【００１４】[0014]
【作用】従来方法では、前述のように下地膜中の上側下
地膜に対するエッチング工程後に電解めっきによるバン
プ電極の成長工程に入れていたので、両工程にそれぞれ
フォトプロセスが必要であったが、本発明方法は前項の
構成にいうように下地膜を被着した後すぐバンプ電極を
成長させ、上側下地膜をこのバンプ電極をマスクとする
エッチングにより除去することによって、フォトプロセ
スをバンプ電極の電解めっき用マスクをパターンニング
するための１回だけで済ませることに成功したものであ
る。さらに、従来方法では下側下地膜をバンプ電極をマ
スクとする化学エッチング法で除去していたが、本発明
方法はバンプ電極をマスクとする点は同じであるがそれ
をドライエッチング法で除去することにより、従来のバ
ンプ電極によるエッチング速度のばらつきをなくしてオ
ーバエッチングの発生を防止するものである。[Operation] In the conventional method, as mentioned above, the bump electrode growth process by electrolytic plating was performed after the etching process for the upper base film in the base film, so a photo process was required for both processes. The method of the invention is to grow the bump electrode immediately after depositing the base film as described in the previous section, and remove the upper base film by etching using the bump electrode as a mask, thereby converting the photo process into electrolytic plating of the bump electrode. We succeeded in patterning the mask only once. Furthermore, in the conventional method, the lower base film was removed using a chemical etching method using the bump electrode as a mask, but the method of the present invention uses the bump electrode as a mask, but removes it using a dry etching method. This eliminates variations in etching rate caused by conventional bump electrodes and prevents over-etching.
【００１５】さらには、本発明では上側下地膜の除去工
程の次の工程として、その時にまだ残っている下側下地
膜をめっき電極として上側下地膜の被エッチング面に例
えばＡｕを電解めっきする工程を挿入することにより、
使用中に上側下地膜が腐食するおそれを大幅に減少させ
ることができる。Furthermore, in the present invention, as the next step after the step of removing the upper base film, there is a step of electrolytically plating, for example, Au on the surface to be etched of the upper base film, using the lower base film still remaining at that time as a plating electrode. By inserting
The risk of corrosion of the upper base film during use can be significantly reduced.
【００１６】[0016]
【実施例】以下、図１を参照しながら本発明によるバン
プ電極の製造方法の実施例を説明する。図１は前に説明
した図２と同じ要領で主な工程ごとの状態を一部拡大断
面で示すもので、同じ部分には同じ符号が付けられてい
る。図１（ａ） はバンプ電極を作り込む前のウエハの
状態を示し、前述のようにウエハの主体であるシリコン
の基板１を覆う酸化膜２ないし燐シリケートガラス膜の
上に配設されたふつうは若干の珪素を含むアルミからな
る１〜１．５ μｍの厚みの金属膜３の一部が１〜２μ
ｍの膜厚の窒化シリコン等の絶縁膜４に所定の方形ない
し円形パターンで開口された窓５内に露出している。[Embodiment] An embodiment of the method for manufacturing a bump electrode according to the present invention will be described below with reference to FIG. FIG. 1 is a partially enlarged cross-sectional view showing the state of each main process in the same way as FIG. 2 described above, and the same parts are given the same reference numerals. FIG. 1(a) shows the state of the wafer before bump electrodes are formed, and as mentioned above, the normal bump electrodes are formed on the oxide film 2 or phosphorus silicate glass film covering the silicon substrate 1, which is the main body of the wafer. A part of the metal film 3 with a thickness of 1 to 1.5 μm made of aluminum containing some silicon is 1 to 2 μm thick.
It is exposed in a window 5 opened in a predetermined rectangular or circular pattern in an insulating film 4 made of silicon nitride or the like having a film thickness of m.
【００１７】図１（ｂ） からがバンプ電極の製造工程
であり、この図１（ｂ） の下地膜被着工程ではウエハ
の表面上に絶縁膜４の窓５内で金属膜３に導電接触する
下側下地膜１１と上側下地膜１２との複合膜としてなる
下地膜１０が例えばスパッタ法により全面に被着される
。この内の下側下地膜１１の金属には金属膜３のアルミ
の拡散に対してバリア効果をもつＴｉやＣｒが用いられ
、上側下地膜１２の金属にはこの下側下地膜１１用およ
びバンプ電極用金属となじみのよいＣｕ， Ｐｄ， Ｎ
ｉ， Ａｕ等のいずれかが単独にないしはＮｉとＡｕ，
ＰｄとＡｕ， ＷとＣｕ等のそれらを組み合わせた形
で用いられるが、この実施例では下側下地膜１１にＴｉ
が， 上側下地膜１２にＣｕがそれぞれ用いられるもの
とする。なお、下側下地膜１１の膜厚はふつう ０．１
〜０．３ μｍ， 上側下地膜１２の膜厚は ０．２〜
０．６ μｍ程度とされる。From FIG. 1(b) onwards, the bump electrode is manufactured. In the base film deposition step shown in FIG. 1(b), conductive contact is made with the metal film 3 within the window 5 of the insulating film 4 on the surface of the wafer. A base film 10, which is a composite film of a lower base film 11 and an upper base film 12, is deposited over the entire surface by, for example, sputtering. The metal of the lower base film 11 is Ti or Cr, which has a barrier effect against the diffusion of aluminum in the metal film 3, and the metal of the upper base film 12 is used for the lower base film 11 and bumps. Cu, Pd, N, which are compatible with electrode metals
i, Au, etc. alone or Ni and Au,
Pd and Au, W and Cu, etc. are used in combination, but in this embodiment, Ti is used as the lower base film 11.
However, it is assumed that Cu is used for the upper base film 12. Note that the thickness of the lower base film 11 is usually 0.1
~0.3 μm, the thickness of the upper base film 12 is ~0.2 μm
It is estimated to be about 0.6 μm.
【００１８】図１（ｃ） は電解めっきによるバンプ電
極の成長工程であって、このためにまずフォトレジスト
膜２１を全面にスピンコートし、フォトプロセスによっ
て絶縁膜５の窓５よりは大きいめのパターンでめっき用
の窓を明け、これをマスクとしかつ下地膜１０をめっき
電極としてバンプ電極用金属２０を電解めっき法によっ
て例えば３０〜５０μｍの厚みに成長させる。この金属
２０としては前述のようにＣｕやＡｕが用いられるが、
この実施例ではＡｕを用いるものとする。なお、バンプ
電極用金属２０にＣｕを用いる場合には、その上に例え
ばＡｕを電解めっきによって薄くただし２μｍ以上の膜
厚で付けて置くのが望ましい。FIG. 1(c) shows the process of growing bump electrodes by electrolytic plating. For this purpose, a photoresist film 21 is first spin-coated on the entire surface, and a layer larger than the window 5 of the insulating film 5 is formed by a photo process. A plating window is opened in the pattern, and using this as a mask and the base film 10 as a plating electrode, bump electrode metal 20 is grown to a thickness of, for example, 30 to 50 μm by electrolytic plating. As mentioned above, Cu or Au is used as the metal 20.
In this embodiment, Au is used. In addition, when Cu is used for the bump electrode metal 20, it is desirable to apply, for example, Au to a thin film thickness of 2 μm or more by electrolytic plating thereon.
【００１９】次の図１（ｄ） は上側下地膜の除去工程
である。このため、まず図１（ｃ） の状態からフォト
レジスト膜２１を取り除いた上で、バンプ電極用金属２
０をマスクとして上側下地膜１２をこの実施例では化学
エッチング法により除去する。この際のエッチング液に
は上側下地膜１２を溶解して下側下地膜１１を溶解しな
い選択性を有するものを用い、この実施例のように下側
下地膜１１がＴｉで上側下地膜１２がＣｕの場合は薄い
王水を用いることにより短時間内に上側下地膜１２を選
択的にエッチングして下側下地膜１１を残すことができ
る。The next step shown in FIG. 1(d) is the step of removing the upper base film. For this reason, first remove the photoresist film 21 from the state shown in FIG. 1(c), and then remove the bump electrode metal 21.
In this embodiment, the upper base film 12 is removed by chemical etching using 0 as a mask. The etching solution at this time is one that has the selectivity to dissolve the upper base film 12 but not the lower base film 11, and as in this example, the lower base film 11 is Ti and the upper base film 12 is In the case of Cu, by using a thin aqua regia, the upper base film 12 can be selectively etched within a short time, leaving the lower base film 11.
【００２０】この実施例では上側下地膜１２にＣｕが用
いられて使用中に腐食が発生するおそれがあるので、図
１（ｅ） に示すＡｕめっき工程が挿入される。この工
程では残っている下側下地膜１１をめっき電極としてＡ
ｕ等の高耐食性の金属を電解めっきすることにより上側
下地膜１２の前工程でエッチングされた周面にＡｕめっ
き３０を２μｍ以上の例えば２〜５μｍの膜厚で施す。
このＡｕめっき３０はこの例ではＡｕのバンプ電極用金
属２０の表面にも図のようにもちろん付くが、めっき電
圧の選定によりＡｕとはイオン化傾向がかなり異なるＴ
ｉの下側下地膜１１にほとんど付かない良好なめっき選
択性を持たせることができる。In this embodiment, since Cu is used for the upper base film 12, there is a risk that corrosion may occur during use, so an Au plating process shown in FIG. 1(e) is inserted. In this step, the remaining lower base film 11 is used as a plating electrode.
Au plating 30 is applied to the peripheral surface etched in the previous step of the upper base film 12 to a thickness of 2 μm or more, for example, 2 to 5 μm, by electrolytically plating a highly corrosion-resistant metal such as U or the like. In this example, this Au plating 30 is also attached to the surface of the Au bump electrode metal 20 as shown in the figure, but due to the selection of the plating voltage, the ionization tendency is quite different from that of Au.
It is possible to provide good plating selectivity with almost no adhesion to the lower base film 11 of i.
【００２１】最後の図１（ｆ） の下側下地膜の除去工
程では、バンプ電極用金属２０ないしは前の工程で付け
られたＡｕめっきをマスクとして残存している下側下地
膜１１をドライエッチング法によって除去して図示の完
成状態とする。このドライエッチングは例えば４％程度
の酸素を含む４ふっ化炭素や４塩化炭素を反応ガスとし
て２Ｔｏｒｒ程度のふん囲気圧力下で行なうことでよく
、この条件でＡｕやＣｕをエッチングすることなく下側
下地膜１１のＴｉを高速でエッチングできる良好な選択
性が得られる。また、このドライエッチングの速度は化
学エッチングの場合とは異なり基板１と金属膜５の間の
接続抵抗と実質上無関係なので、ウエハ内のすべてのバ
ンプ電極付近の下側下地膜１１を均一な速度でエッチン
グでき、オーバエッチングの発生をほぼ完全に防止する
ことができる。In the final lower base film removal step shown in FIG. 1(f), the remaining lower base film 11 is dry-etched using the bump electrode metal 20 or the Au plating applied in the previous process as a mask. The completed state shown in the figure is obtained by removing the material using a method. This dry etching can be carried out under an ambient pressure of about 2 Torr using, for example, carbon tetrafluoride or carbon tetrachloride containing about 4% oxygen as a reaction gas. Good selectivity for etching Ti of the base film 11 at high speed is obtained. Moreover, unlike chemical etching, the speed of this dry etching is virtually unrelated to the connection resistance between the substrate 1 and the metal film 5, so the lower base film 11 near all bump electrodes in the wafer is etched at a uniform rate. It is possible to completely prevent over-etching.
【００２２】この実施例によるバンプ電極を備えるフリ
ップチップは、いわゆるＣＯＧ方式（Ｃｈｉｐ Ｏｎ
Ｇｌａｓｓ）の実装用にとくに適し、セラミックの配線
基板上に導電性樹脂等を用いてその配線導体にバンプ電
極を接続することにより実装される。ＣＯＧ方式の実装
用フリップチップではバンプ電極のサイズは例えば １
００μｍ角ないし径程度とされ、その高さは５０μｍ程
度とされる。The flip chip equipped with bump electrodes according to this embodiment uses the so-called COG method (Chip On
It is particularly suitable for mounting on a ceramic wiring board using a conductive resin or the like and connecting bump electrodes to the wiring conductors of the ceramic wiring board. For example, the size of the bump electrode in a flip chip for mounting using the COG method is 1.
It is approximately 00 μm square or in diameter, and its height is approximately 50 μm.
【００２３】本発明方法により製造されたバンプ電極は
その付け根の機械強度のばらつきが従来より格段に減少
し、実装前のフリップチップの保管期間および実装後の
使用期間を通じて上側下地膜に腐食のトラブル発生がな
いことが確認されている。Bump electrodes manufactured by the method of the present invention have significantly reduced variations in mechanical strength at their bases than conventional ones, and there is no problem of corrosion of the upper base film throughout the storage period of the flip chip before mounting and the period of use after mounting. It has been confirmed that no outbreak has occurred.
【００２４】[0024]
【発明の効果】以上のとおり本発明方法では、ウエハの
表面に少なくとも２種の金属の複合膜としてなる下地膜
を全面被着する工程と、下地膜をめっき電極としてバン
プ電極用金属を電解めっきにより絶縁膜の窓部上に選択
的に成長させる工程と、バンプ電極用金属をマスクとす
るエッチングにより上側下地膜を除去する工程と、残る
下側下地膜をドライエッチング法により除去する工程と
を経てバンプ電極を製造するようにしたので、次の効果
を得ることができる。[Effects of the Invention] As described above, the method of the present invention includes the steps of fully depositing a base film as a composite film of at least two types of metals on the surface of a wafer, and electrolytically plating metal for bump electrodes using the base film as a plating electrode. a step of selectively growing the insulating film on the window portion by using a method, a step of removing the upper base film by etching using the bump electrode metal as a mask, and a step of removing the remaining lower base film by dry etching. Since the bump electrode is manufactured after the process, the following effects can be obtained.
【００２５】
（ａ） 下側下地膜と上側下地膜の被着に引き続いてバ
ンプ電極を電解めっき法で成長させ、バンプ電極をマス
クとするエッチングで上側下地膜を除去することによっ
て、上側下地膜のパターンニングのために従来必要であ
ったフォトプロセスを省略し、バンプ電極の電解めっき
用マスクをパターンニングするための１回のフォトプロ
セスだけで済ませて、フリップチップの製造コストを低
減することができる。(a) Following the deposition of the lower base film and the upper base film, a bump electrode is grown by electrolytic plating, and the upper base film is removed by etching using the bump electrode as a mask. It is possible to reduce the manufacturing cost of flip chips by omitting the photo process that was conventionally required for patterning the bump electrodes and requiring only one photo process to pattern the electrolytic plating mask for the bump electrodes. can.
【００２６】
（ｂ） 下側下地膜をバンプ電極をマスクとするドライ
エッチング法によって除去するので、そのエッチング速
度がウエハ内のすべてのバンプ電極について均一になり
、従来のように特定のバンプ電極下の下側下地膜がオー
バエッチングされるおそれが格段に減少し、バンプ電極
の付け根の機械強度の低下や接続抵抗の増大のトラブル
をほぼ皆無にしてフリップチップの製造歩留まりを向上
できる。(b) Since the lower base film is removed by a dry etching method using the bump electrodes as a mask, the etching rate becomes uniform for all bump electrodes within the wafer, and unlike the conventional method, the etching rate is uniform for all bump electrodes on the wafer. The risk of over-etching of the lower base film is significantly reduced, and the manufacturing yield of flip chips can be improved by virtually eliminating problems such as a decrease in mechanical strength at the base of the bump electrode and an increase in connection resistance.
【００２７】
（ｃ） バンプ電極用金属の電解めっきを下側下地膜と
上側下地膜とをめっき電極として行なうので、従来の下
側下地膜だけをめっき電極として電解めっきをしていた
場合と比べてめっき電極の電気抵抗が数分の１に減少し
、これによりバンプ電極の成長高さのウエハ内のばらつ
きを減少させてフリップチップの歩留まりを上げ、その
配線基板等への実装を容易にし、かつ配線導体との接続
を確実にすることができる。(c) Since the electrolytic plating of the bump electrode metal is performed using the lower base film and the upper base film as the plating electrodes, compared to the conventional case where electrolytic plating was performed using only the lower base film as the plating electrode. The electrical resistance of the plated electrode is reduced to a fraction of a fraction, which reduces the variation in the growth height of bump electrodes within the wafer, increases the yield of flip chips, and facilitates their mounting on wiring boards, etc. Moreover, the connection with the wiring conductor can be ensured.
【００２８】
（ｄ） Ｃｕ等の腐食されやすい金属を上側下地膜に用
いる場合、その側面に対するＡｕめっき工程を挿入する
ことにより、その耐腐食性を向上してフリップチップの
保管中や実装後の上側下地膜の腐食のトラブルを防止す
ることができる。(d) When a metal that is easily corroded, such as Cu, is used for the upper base film, by inserting an Au plating process on the side surface, its corrosion resistance can be improved and the flip chip can be easily removed during storage or after mounting. Troubles caused by corrosion of the upper base film can be prevented.
【図１】本発明による半導体装置用バンプ電極の製造方
法の実施例を同図（ａ） 〜（ｆ） により主な工程ご
との状態で示すウエハ中のバンプ電極を設ける要部の拡
大断面図である。FIG. 1 is an enlarged cross-sectional view of a main part of a wafer in which bump electrodes are provided, showing an embodiment of the method for manufacturing bump electrodes for semiconductor devices according to the present invention, showing the state of each main process in FIGS. It is.
【図２】従来技術によるバンプ電極の製造方法を図１に
対応する要領で同図（ａ） 〜（ｄ）に示すウエハの要
部拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a main part of a wafer shown in FIGS. 1A to 1D, in a manner corresponding to FIG. 1, showing a conventional method for manufacturing bump electrodes.
【図３】従来方法によるバンプ電極の問題点を同図（ａ
） と（ｂ） により示すウエハの要部拡大断面図であ
る。[Fig. 3] The problem of the bump electrode according to the conventional method is shown in the same figure (a
) and (b) are enlarged cross-sectional views of essential parts of the wafer.
１ ウエハの基板
３ 金属膜
４ 絶縁膜
５ 窓
１０ 下地膜
１１ 下側下地膜
１２ 上側下地膜
２０ バンプ電極ないしバンプ電極用金属３０
Ａｕめっき1 Wafer substrate 3 Metal film 4 Insulating film 5 Window 10 Base film 11 Lower base film 12 Upper base film 20 Bump electrode or bump electrode metal 30
Au plating
Claims (7)
膜に明けられた窓内に露出されたウエハの表面に少なく
とも２種の金属の複合膜としてなる下地膜を全面被着す
る工程と、下地膜をめっき電極としてバンプ電極用金属
を電解めっきにより絶縁膜の窓部上に選択的に成長させ
る工程と、バンプ電極用金属をマスクとするエッチング
により上側下地膜を除去する工程と、残る下側下地膜を
ドライエッチング法により除去する工程とを含むことを
特徴とする半導体装置用バンプ電極の製造方法。1. A step of fully depositing a base film, which is a composite film of at least two types of metals, on the surface of the wafer where the metal film portion to which the bump electrode is to be connected is exposed within the window formed in the insulating film. , a step of selectively growing bump electrode metal on the window portion of the insulating film by electrolytic plating using the base film as a plating electrode, a step of removing the upper base film by etching using the bump electrode metal as a mask, and a step of removing the upper base film by etching using the bump electrode metal as a mask. 1. A method for manufacturing a bump electrode for a semiconductor device, comprising the step of removing a lower base film by dry etching.
極用金属にＡｕとＣｕのいずれかが用いられることを特
徴とする半導体装置用バンプ電極の製造方法。2. The method of manufacturing a bump electrode for a semiconductor device according to claim 1, wherein either Au or Cu is used as the metal for the bump electrode.
膜をバンプ電極用金属をマスクとする化学エッチング法
により除去することを特徴とする半導体装置用バンプ電
極の製造方法。3. The method of manufacturing a bump electrode for a semiconductor device according to claim 1, wherein the upper base film is removed by a chemical etching method using a bump electrode metal as a mask.
極用金属としてＣｕが用いられ、その電解めっき後の表
面にＡｕがめっきされることを特徴とする半導体装置用
バンプ電極の製造方法。4. The method of manufacturing a bump electrode for a semiconductor device according to claim 3, wherein Cu is used as the metal for the bump electrode, and the surface of the bump electrode is plated with Au after electrolytic plating.
膜の除去工程の後に残る下側下地膜をめっき電極として
Ａｕをバンプ電極用金属と上側下地膜の被エッチング面
に電解めっきする工程を挿入することを特徴とする半導
体装置用バンプ電極の製造方法。5. The method according to claim 1, in which the lower base film remaining after the removal step of the upper base film is used as a plating electrode, and Au is electrolytically plated on the bump electrode metal and the surface to be etched of the upper base film. 1. A method for manufacturing a bump electrode for a semiconductor device, the method comprising: inserting a bump electrode for a semiconductor device.
下地膜用金属としてＴｉとＣｒのいずれかが用いられる
ことを特徴とする半導体装置用バンプ電極の製造方法。6. The method of manufacturing a bump electrode for a semiconductor device according to claim 1, wherein either Ti or Cr is used as the metal for the lower base film.
下地膜用金属としてＣｕ， Ｐｄ， Ｎｉ， Ａｕおよ
びＷの少なくとも１種が用いられることを特徴とする半
導体装置用バンプ電極の製造方法。7. The method of manufacturing a bump electrode for a semiconductor device according to claim 1, wherein at least one of Cu, Pd, Ni, Au and W is used as the metal for the upper base film. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2403400A JPH04217323A (en) | 1990-12-19 | 1990-12-19 | Manufacture of bump electrode for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2403400A JPH04217323A (en) | 1990-12-19 | 1990-12-19 | Manufacture of bump electrode for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04217323A true JPH04217323A (en) | 1992-08-07 |
Family
ID=18513138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2403400A Pending JPH04217323A (en) | 1990-12-19 | 1990-12-19 | Manufacture of bump electrode for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04217323A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| KR100429515B1 (en) * | 2001-12-27 | 2004-05-03 | 삼성전자주식회사 | Fabrication method for optical communication elements with mushroom type plating layer |
| CN100418239C (en) * | 1997-01-31 | 2008-09-10 | 松下电器产业株式会社 | Manufacturing method of light-emitting device |
| DE102022130964A1 (en) | 2021-12-24 | 2023-06-29 | Nichia Corporation | Light emitting module and method for manufacturing the light emitting module |
-
1990
- 1990-12-19 JP JP2403400A patent/JPH04217323A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| CN100418239C (en) * | 1997-01-31 | 2008-09-10 | 松下电器产业株式会社 | Manufacturing method of light-emitting device |
| KR100429515B1 (en) * | 2001-12-27 | 2004-05-03 | 삼성전자주식회사 | Fabrication method for optical communication elements with mushroom type plating layer |
| DE102022130964A1 (en) | 2021-12-24 | 2023-06-29 | Nichia Corporation | Light emitting module and method for manufacturing the light emitting module |
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