JPH04196263A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH04196263A
JPH04196263A JP2326896A JP32689690A JPH04196263A JP H04196263 A JPH04196263 A JP H04196263A JP 2326896 A JP2326896 A JP 2326896A JP 32689690 A JP32689690 A JP 32689690A JP H04196263 A JPH04196263 A JP H04196263A
Authority
JP
Japan
Prior art keywords
chip
memory
semiconductor integrated
pads
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2326896A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hamano
博之 浜野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2326896A priority Critical patent/JPH04196263A/en
Publication of JPH04196263A publication Critical patent/JPH04196263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

Landscapes

  • Dram (AREA)

Abstract

PURPOSE:To make possible the realization of a chip size, which does not depend on a memory capacity, and to make it possible to obtain a large-scale semiconductor integrated circuit by a method wherein a memory circuit and a peripheral circuit for memory circuit use or a memory circuit and one part of a peripheral circuit for memory circuit use are respectively formed into the constitution of a separate chip. CONSTITUTION:The mutual chips of a parent chip 1 and a memory function chip 2 are respectively connected to the upper part of the chip 1 and the upper part of the chip 2 and pads 4 for bonding use are provided for feeding necessary signal or power supply from the chip 1 to the chip 2. A material 5 for ohmic contact use and a metal bonding material 6 are placed on these pads, the pads are made to face each other and the chips 1 and 2 are bonded together in a such a way that the signals or power pads of chips 1 and 2 are made to oppose to each other. Thereby, a memory circuit constituted on one chip constituted as a separate chip and a large-scale semiconductor integrated circuit can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体集積回路に関し、特に大規模半導体集
積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to large-scale semiconductor integrated circuits.

〔従来の技術〕[Conventional technology]

第２図は従来の半導体集積回路を示す平面図である。図
において、（１）はチップ、（２ａ）はメモリ部（ＲＡ
Ｍ）、（２ｂ）はメモリ部（ＲＡＭデユーダ）、（２ｃ
）はメモリ部（ＲＯＭ）、（２ｄ）はメモリ部（ＲＯＭ
デユーダ）、＋８１は周辺パッド、（７）はＣＰＵ部で
ある。FIG. 2 is a plan view showing a conventional semiconductor integrated circuit. In the figure, (1) is the chip, (2a) is the memory section (RA
M), (2b) is a memory section (RAM duder), (2c
) is the memory part (ROM), (2d) is the memory part (ROM
+81 is a peripheral pad, and (7) is a CPU section.

次に作用について説明する。Next, the effect will be explained.

従来の半導体集積回路は上記のように構成され、チップ
（１）の上にメモリ部（２ａ）〜（２ａ）　、周辺バラ
Ｆ（８１，及びＣＰＵ部（８）が混在して形成されてい
る。A conventional semiconductor integrated circuit is constructed as described above, with memory parts (2a) to (2a), peripheral parts F (81), and CPU part (8) being formed in a mixed manner on a chip (1). .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体集積回路は以上のように構成されているの
で、メモリ容量が増大すると、チップサイズも大きくな
るとともに、チップサイズの制限から、メモリ容量を制
限しなければならないなどの問題点があった。Conventional semiconductor integrated circuits are configured as described above, so as the memory capacity increases, the chip size also increases, and due to chip size limitations, there are problems such as the need to limit the memory capacity. .

この発明は上記のような問題点を解消するためになされ
たもので、１チツプ上に構成されているメモリ回路を別
チップとして構成し、大規模牛導体集積回路を得ること
を目的とする。The present invention has been made to solve the above-mentioned problems, and its object is to construct a memory circuit configured on one chip as a separate chip to obtain a large-scale conductor integrated circuit.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体集積回路は親チップとメモリ機能
チップとを接続するパッドの上にオーミックコンタクト
用金属材料と金属接合材料を載せ、互いのチップを向か
い合せに、各信号あるいは電源パッドを相対させて金属
接合したものである。In the semiconductor integrated circuit according to the present invention, a metal material for ohmic contact and a metal bonding material are placed on the pads connecting the parent chip and the memory function chip, and the chips are placed facing each other, and each signal or power supply pad is placed facing each other. It is metal-bonded.

〔作用〕[Effect]

この発明における接合方法はチップから分離でせたメモ
リ回路及びメモリ回路用周辺回路、又はメモリ回路及び
メモリ回路用周辺回路の一部をチップ化し、親チップと
メモリ機能チップ上のパッドの上に載せた金属接合材料
により各信号あるいは電源パッドを相対させて接合する
。The bonding method in this invention is to form a memory circuit and a memory circuit peripheral circuit separated from a chip, or a part of a memory circuit and a memory circuit peripheral circuit into a chip, and place it on a parent chip and pads on a memory function chip. Each signal or power supply pad is bonded to each other using a metal bonding material.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例による半導体集積回路を示す図
で、第１図（ａｌＵ平面図、第１図（ｂｌは断面図であ
る。図において、（１）は半導体集積回路本体からなる
親チップ、（２）はメモリ機能チップ、（８）は親チッ
プ（１〉上に設けられた周辺パッド、（４）は親チップ
（１）、メモリ機能チップ（２）上に設けられ、互いを
接続するための接合用パッド、（５）は接合用パッド＋
４）上に積層し、接合用パッド＋４１と下記金属接合材
料（６）とのオーミックコンタクトをとり、親チップ（
１）、メモリ機能チップ（２）の面間のスペースを保ち
、接触をさけるためのオーミックコンタクト用金属材料
、（６）ｆ″ｉ親チップ（１）とメモリ機能チップ（２
）を接合するためのはんだ等の金属接合材料である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figures show a semiconductor integrated circuit according to an embodiment of the present invention. chip, (2) is a memory function chip, (8) is a peripheral pad provided on the parent chip (1), (4) is provided on the parent chip (1) and memory function chip (2), and they are connected to each other. Bonding pad for connection, (5) is bonding pad +
4) Stack it on top, make ohmic contact between the bonding pad +41 and the following metal bonding material (6),
1) Metal material for ohmic contact to maintain space between the surfaces of the memory function chip (2) and avoid contact; (6) f″i parent chip (1) and memory function chip (2);
) is a metal bonding material such as solder for bonding.

次に動作について説明する、 上記のように構成された半導体集積回路においては、親
チップ（１）及びメモリ機能チップ（２）上に、互いの
チップを接続し、メモリ機能チップ（２）に必要な信号
あるいは電源を親チップより供給するために接合用パッ
ドＣ４）を設け、この上にオーミックコンタクト用金属
材料（５）と金属接合材料（６）を載せ、向かい合せに
、互いの各信号あるいは電源パッド相対すせて接合する
。なお、メモリ機能チップ内にはメモリに必要なデコー
ダも含まれる。Next, the operation will be explained. In the semiconductor integrated circuit configured as described above, the chips are connected to each other on the parent chip (1) and the memory function chip (2), and the memory function chip (2) A bonding pad C4) is provided in order to supply signals or power from the parent chip, and a metal material (5) for ohmic contact and a metal bonding material (6) are placed on this pad, facing each other for each signal or power. Connect the power supply pads so that they are flush against each other. Note that the memory function chip also includes a decoder necessary for the memory.

なお上記実施例ではメモリ回路を別チップ構成にするこ
とを示したが、タイマ回路等の周辺回路を別チップ構成
にしても良く、同様の効果を奏する。In the above embodiment, the memory circuit is configured as a separate chip, but peripheral circuits such as a timer circuit may be configured as separate chips, and the same effect can be obtained.

し発明の効果〕 以上のように、この発明によればメモリ回路及びメモリ
回路用周辺回路、又はメモリ回路及びメモリ回路用周辺
回路の一部を別チップ構成にしたので、メモリ容量に依
存しないチップサイズが実現でき、大規模半導体集積回
路を得られる効果がある。[Effects of the Invention] As described above, according to the present invention, the memory circuit and the peripheral circuit for the memory circuit, or a part of the memory circuit and the peripheral circuit for the memory circuit are formed into separate chips, so that the chip does not depend on the memory capacity. The size can be realized and there is an effect that a large-scale semiconductor integrated circuit can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例による半導体集積回路を示
す図で、第１図（ａ＋は平面図、第１図（ｂｌは断面図
、第２図は従来の半導体集積回路を示す平面図である。 図において、（１）は親チップ、（２）はメモリ機能チ
ップ、（８）は周辺パッド、Ｃ４）は接合用パッド、（
５Ｉはオーミックコンタクト用金属材料、（６）は金属
接合材料である。 なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, in which FIG. 1 (a+ is a plan view, FIG. In the figure, (1) is the parent chip, (2) is the memory function chip, (8) is the peripheral pad, C4) is the bonding pad, (
5I is a metal material for ohmic contact, and (6) is a metal bonding material. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 　半導体集積回路本体からなる親チップ、メモリ回路お
よびデコーダ等のメモリ周辺回路からなるメモリ機能チ
ップ、上記親チップとメモリ機能チップとのそれぞれに
互いを接続するに必要な信号パッドあるいは電源パッド
を設け、上記信号パッドあるいは電源パッド上にオーミ
ックコンタクト可能な金属材料をそれぞれ積層し、上記
金属材料上に金属接合材料を載せて上記親チップおよび
メモリ機能チップを向かい合わせにし、上記親チップと
機能メモリチップの互いの各信号あるいは各電源パッド
を相対させて金属接合したことを特徴とする半導体集積
回路。A parent chip consisting of a semiconductor integrated circuit main body, a memory function chip consisting of a memory circuit and memory peripheral circuits such as a decoder, and signal pads or power supply pads necessary for connecting each other to each of the parent chip and memory function chip are provided, A metal material capable of ohmic contact is laminated on each of the signal pads or power supply pads, a metal bonding material is placed on the metal material, and the parent chip and memory function chip are placed facing each other. A semiconductor integrated circuit characterized in that each signal or each power supply pad is metal-bonded so as to face each other.
JP2326896A 1990-11-27 1990-11-27 Semiconductor integrated circuit Pending JPH04196263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2326896A JPH04196263A (en) 1990-11-27 1990-11-27 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2326896A JPH04196263A (en) 1990-11-27 1990-11-27 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04196263A true JPH04196263A (en) 1992-07-16

Family

ID=18192959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2326896A Pending JPH04196263A (en) 1990-11-27 1990-11-27 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04196263A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1233444A3 (en) * 1992-04-08 2002-12-11 LEEDY, Glenn J. Membrane dielectric isolation ic fabrication
DE10142119A1 (en) * 2001-08-30 2003-03-27 Infineon Technologies Ag Electronic component and method for its production
JP2006012358A (en) * 2004-06-29 2006-01-12 Nec Corp Stacked semiconductor memory device
US7221614B2 (en) 2004-06-28 2007-05-22 Nec Corporation Stacked semiconductor memory device
US7330368B2 (en) 2004-06-29 2008-02-12 Nec Corporation Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections
US7352067B2 (en) 2004-06-30 2008-04-01 Nec Corporation Stacked semiconductor device
US7764564B2 (en) 2006-12-04 2010-07-27 Nec Corporation Semiconductor device
US8315331B2 (en) 2008-02-28 2012-11-20 Nec Corporation Transmission method, transmission circuit and transmission system
US8477855B2 (en) 2006-01-30 2013-07-02 Nec Corporation Signal transmission system and semiconductor integrated circuit device
US8588681B2 (en) 2007-02-23 2013-11-19 Nec Corporation Semiconductor device performing signal transmission by using inductor coupling
US8928119B2 (en) 1997-04-04 2015-01-06 Glenn J. Leedy Three dimensional structure memory

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6682981B2 (en) 1992-04-08 2004-01-27 Elm Technology Corporation Stress controlled dielectric integrated circuit fabrication
US6713327B2 (en) 1992-04-08 2004-03-30 Elm Technology Corporation Stress controlled dielectric integrated circuit fabrication
US6765279B2 (en) 1992-04-08 2004-07-20 Elm Technology Corporation Membrane 3D IC fabrication
EP1233444A3 (en) * 1992-04-08 2002-12-11 LEEDY, Glenn J. Membrane dielectric isolation ic fabrication
US8928119B2 (en) 1997-04-04 2015-01-06 Glenn J. Leedy Three dimensional structure memory
US9401183B2 (en) 1997-04-04 2016-07-26 Glenn J. Leedy Stacked integrated memory device
US8933570B2 (en) 1997-04-04 2015-01-13 Elm Technology Corp. Three dimensional structure memory
DE10142119A1 (en) * 2001-08-30 2003-03-27 Infineon Technologies Ag Electronic component and method for its production
US6683374B2 (en) 2001-08-30 2004-01-27 Infineon Technologies Ag Electronic component and process for producing the electronic component
DE10142119B4 (en) * 2001-08-30 2007-07-26 Infineon Technologies Ag Electronic component and method for its production
US7221614B2 (en) 2004-06-28 2007-05-22 Nec Corporation Stacked semiconductor memory device
US7330368B2 (en) 2004-06-29 2008-02-12 Nec Corporation Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections
JP4534132B2 (en) * 2004-06-29 2010-09-01 エルピーダメモリ株式会社 Stacked semiconductor memory device
US7209376B2 (en) 2004-06-29 2007-04-24 Nec Corporation Stacked semiconductor memory device
JP2006012358A (en) * 2004-06-29 2006-01-12 Nec Corp Stacked semiconductor memory device
US7352067B2 (en) 2004-06-30 2008-04-01 Nec Corporation Stacked semiconductor device
US8477855B2 (en) 2006-01-30 2013-07-02 Nec Corporation Signal transmission system and semiconductor integrated circuit device
US7764564B2 (en) 2006-12-04 2010-07-27 Nec Corporation Semiconductor device
US8588681B2 (en) 2007-02-23 2013-11-19 Nec Corporation Semiconductor device performing signal transmission by using inductor coupling
US8315331B2 (en) 2008-02-28 2012-11-20 Nec Corporation Transmission method, transmission circuit and transmission system

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