JPH10256472A - Structure of semiconductor device provided with ic chips - Google Patents
Structure of semiconductor device provided with ic chipsInfo
- Publication number
- JPH10256472A JPH10256472A JP9058906A JP5890697A JPH10256472A JP H10256472 A JPH10256472 A JP H10256472A JP 9058906 A JP9058906 A JP 9058906A JP 5890697 A JP5890697 A JP 5890697A JP H10256472 A JPH10256472 A JP H10256472A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- another
- corners
- semiconductor device
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、一つのICチップ
の上面に、別のICチップを積み重ねることによって集
積度を高めるように構成した半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device configured to increase the degree of integration by stacking another IC chip on the upper surface of one IC chip.
【0002】[0002]
【従来の技術】平面視で矩形に形成した一つのICチッ
プの上面に、同じく平面視で矩形に形成した別のICチ
ップを、その相互間を電気的に接続するように積み重ね
ることにより、一つの半導体装置における集積度を高め
る場合において、前記別のICチップが、前記一つのI
Cチップと同じ大きさの合同形であると、前記一つIC
チップにおける上面の全体が、この別のICチップにて
覆われることになるから、前記一つのICチップの上面
に設けられている各外部接続用電極部の各々に対してリ
ード端子をワイヤボンディング等にて接続することがで
きない。2. Description of the Related Art Another IC chip also formed in a rectangular shape in plan view is stacked on the upper surface of one IC chip formed in a rectangular shape in plan view so as to electrically connect the IC chips to each other. In the case where the integration degree in one semiconductor device is increased, the another IC chip is connected to the one IC chip.
If the congruent shape is the same size as the C chip, the one IC
Since the entire upper surface of the chip is covered with this another IC chip, lead terminals are connected to each of the external connection electrode portions provided on the upper surface of the one IC chip by wire bonding or the like. Cannot connect.
【0003】そこで、従来は、一つのICチップの上面
に積み重ねられる別のICチップの大きさを、前記一つ
のICチップよりも小さくした相似形にすることによ
り、この別のICチップにおける四つの各側面の外側
に、前記一つのICチップの上面における各外部接続用
電極部が露出するように構成しているのである。Therefore, conventionally, the size of another IC chip stacked on the upper surface of one IC chip is made smaller and similar to that of the one IC chip, so that the four The configuration is such that the external connection electrode portions on the upper surface of the one IC chip are exposed outside the respective side surfaces.
【0004】[0004]
【発明が解決しようとする課題】しかし、このように、
前記別のICチップにおける外側に前記一つのICチッ
プの上面における各外部接続用電極部が露出するように
構成するためには、前記別のICチップの大きさを、前
記一つのICチップよりも可成り小さくしなければなら
ないから、一つの半導体装置における集積度を充分に高
めることができないと言う問題があった。However, as described above,
In order to configure each of the external connection electrode portions on the upper surface of the one IC chip to be exposed to the outside of the another IC chip, the size of the another IC chip must be larger than that of the one IC chip. There has been a problem that the degree of integration in one semiconductor device cannot be sufficiently increased because the size must be considerably reduced.
【0005】本発明は、この問題を解消できるようにし
た半導体装置の構造を提供することを技術的課題とする
ものである。An object of the present invention is to provide a structure of a semiconductor device which can solve this problem.
【0006】[0006]
【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「平面視で矩形に形成した一つのIC
チップの上面に、同じく平面視で矩形に形成した別のI
Cチップを、その相互間を電気的に接続するように積み
重ねて成る半導体装置において、前記別のICチップ
を、当該別のICチップにおける四隅部が前記一つのI
Cチップにおける四隅部と不一致とするように前記一つ
のICチップに対して回しずらせる。」と言う構成にし
た。In order to achieve this technical object, the present invention provides an "one IC formed in a rectangular shape in plan view".
Another I formed in a rectangular shape in plan view on the upper surface of the chip
In a semiconductor device in which C chips are stacked so as to electrically connect the C chips to each other, the other IC chip is connected to the one IC chip at four corners.
The one IC chip is rotated so as not to coincide with the four corners of the C chip. ".
【0007】[0007]
【発明の作用・効果】このように、別のICチップを、
当該別のICチップにおける四隅部を一つのICチップ
における四隅部と不一致とするように前記一つのICチ
ップに対して回しずらせることにより、前記両ICチッ
プを、同じ大きさの合同形にしても、前記一つのICチ
ップにおける四隅部が、前記別のICチップにおける四
つの側面よりも外側にはみ出すことになり、つまり、こ
の四隅部の上面が、前記別のICチップの外側に露出す
ることになるから、この四隅部の上面の部分の各々に外
部接続用電極部を形成することができるのである。As described above, another IC chip is
By turning the four corners of the another IC chip with respect to the one IC chip so that the four corners do not coincide with the four corners of the one IC chip, the two IC chips are congruently formed in the same size. Also, the four corners of the one IC chip protrude outside the four side surfaces of the another IC chip, that is, the upper surfaces of the four corners are exposed outside the another IC chip. Therefore, an external connection electrode portion can be formed on each of the upper surface portions of the four corners.
【0008】従って、本発明によると、一つのICチッ
プにおける上面のうち別のICチップの外側の部分に複
数個の外部接続用電極部を設けることができる形態のも
とで、前記別のICチップを、前記従来の場合よりも遙
かに大きくすることができるから、半導体装置における
集積度を大幅に向上できる効果を有する。特に、「請求
項2」のように構成すると、別のICチップを、当該別
のICチップにおける四隅部が一つのICチップにおけ
る各側面から外側にはみ出す一方、前記一つのICチッ
プにおける四隅部が前記別のICチップにおける各側面
から外側にはみ出すように前記一つのICチップに対し
て回しずらせることにより、前記別のICチップを一つ
のICチップに近づけるように大きくした状態のもと
で、前記一つのICチップにおける上面のうち四隅部の
部分と、前記別のICチップにおける下面のうち四隅部
の部分との両方に、外部接続用電極部を形成することが
できるから、両ICチップに形成することができる外部
接続用電極部の数を増大できるのである。Therefore, according to the present invention, another IC is provided in a form in which a plurality of external connection electrode portions can be provided on a portion of the upper surface of one IC chip outside the other IC chip. Since the size of the chip can be made much larger than in the conventional case, there is an effect that the degree of integration in the semiconductor device can be greatly improved. In particular, when configured as in "Claim 2", while four corners of another IC chip protrude outward from each side surface of one IC chip, four corners of the one IC chip are By rotating the one IC chip so as to protrude outward from each side surface of the another IC chip, in a state where the another IC chip is enlarged so as to approach the one IC chip, External connection electrode portions can be formed on both the four corner portions of the upper surface of the one IC chip and the four corner portions of the lower surface of the another IC chip. The number of external connection electrode portions that can be formed can be increased.
【0009】[0009]
【発明の実施の形態】以下、本発明の実施の形態を図1
及び図2の図面について説明する。この図において符号
1は、一つのチップマウント部1aと、このチップマウ
ント部1aの周囲から外向きに延びる多数本のリード端
子1bとを備えた薄い金属板製のリードフレームを、符
号2は、前記リードフレーム1におけるチップマウント
部1aにダイボンディングした一つのICチップを各々
示す。FIG. 1 is a block diagram showing an embodiment of the present invention.
2 and the drawing of FIG. In this figure, reference numeral 1 denotes a thin metal plate lead frame including one chip mount portion 1a and a number of lead terminals 1b extending outward from the periphery of the chip mount portion 1a. One IC chip die-bonded to the chip mount portion 1a of the lead frame 1 is shown.
【0010】前記一つのICチップ2は、平面視におい
て略正方形に形成され、且つ、その上面のうち周囲を除
く中心の部分に能動素子及び/又は受動素子等のような
各種の回路素子の多数個が形成されている。符号3は、
前記一つのICチップ2の上面に積み重ねられる別のI
Cチップを示し、この別のICチップは、平面視におい
て前記一つのICチップと略同じ大きさの略正方形に形
成され、且つ、その下面のうち周囲を除く中心の部分に
能動素子及び受動素子のうちいずれか一方又は両方等の
ような各種の回路素子の多数個が形成されている。The one IC chip 2 is formed in a substantially square shape in a plan view, and a large number of various circuit elements such as active elements and / or passive elements are provided on a central portion of the upper surface excluding the periphery. Individuals are formed. Symbol 3 is
Another IC stacked on the upper surface of the one IC chip 2
C shows a C chip, and another IC chip is formed in a substantially square shape having substantially the same size as the one IC chip in a plan view, and has an active element and a passive element in a central portion of its lower surface excluding the periphery. A large number of various circuit elements such as one or both of them are formed.
【0011】そして、前記別のICチップ3を、前記一
つのICチップ2の上面に対して、この両ICチップ
2,3のうちいずれか一方に設けた多数個のバンプ4に
て互いに電気的に接続した状態にして積み重ねるに際し
て、当該別のICチップ3における四隅部3a,3b,
3c,3dが前記一つのICチップ2における四隅部2
a,2b,2c,2dに一致しない(不一致)ように、
前記一つのICチップ2に対して回しずらせて、この状
態で、この両ICチップ2,3のうちいずれか一方に設
けた多数個のバンプ4にて互いに電気的に接続するよう
に積み重ねるのである。The other IC chip 3 is electrically connected to the upper surface of the one IC chip 2 by a large number of bumps 4 provided on one of the two IC chips 2 and 3. When stacking in a state of being connected to the other IC chip 3, the four corners 3a, 3b,
3c and 3d are four corners 2 of the one IC chip 2
a, 2b, 2c, 2d so as not to match (mismatch)
The IC chip 2 is rotated so as to be rotated, and in this state, the bumps 4 provided on one of the two IC chips 2 and 3 are stacked so as to be electrically connected to each other. .
【0012】これにより、前記一つのICチップ2にお
ける四隅部2a,2b,2c,2dが、この一つのIC
チップ2の上面に積み重ねた前記別のICチップ3にお
ける四つの各側面から外側にはみ出す一方、前記別のI
Cチップ3における四隅部3a,3b,3c,3dが、
前記一つのICチップ2における四つの各側面から外側
にはみ出すことになるなるから、両ICチップ2,3を
略同じ大きさの合同形にした形態のままで、前記一つの
ICチップ2の上面のうち四隅部2a,2b,2c,2
dの部分の各々に、外部接続用電極部5の複数個を形成
することができる一方、前記別のICチップ3における
下面のうち四隅部3a,3b,3c,3dの部分の各々
にも、外部接続用電極部6の複数個を形成することがで
きるのである。As a result, the four corners 2a, 2b, 2c and 2d of the one IC chip 2 are
The other IC chip 3 stacked on the upper surface of the chip 2 protrudes outward from each of the four sides, while the other IC chip 3
The four corners 3a, 3b, 3c, 3d of the C chip 3
Since the four IC chips 2 protrude outward from the four side surfaces, the upper surface of the one IC chip 2 is kept in a form in which the two IC chips 2 and 3 are formed into a congruent shape having substantially the same size. Of the four corners 2a, 2b, 2c, 2
While a plurality of external connection electrode portions 5 can be formed in each of the portions d, each of the four corner portions 3a, 3b, 3c and 3d of the lower surface of the another IC chip 3 also has A plurality of external connection electrode portions 6 can be formed.
【0013】このように、一つのICチップ2に対して
別のICチップ3を積み重ね接続すると、これら両IC
チップ2,3の各四隅部における各外部接続用電極部
5,6と、前記リードフレーム1における各リード端子
1bとの間を、細い金属線7によるワイヤボンディング
にて電気的に接続したのち、これらの全体を、図1及び
図2に二点鎖線で示すように、合成樹脂製のパッケージ
体8にて密封する。As described above, when another IC chip 3 is stacked on one IC chip 2 and connected,
After electrically connecting the external connection electrode portions 5 and 6 at the four corners of the chips 2 and 3 and the lead terminals 1b of the lead frame 1 by wire bonding with a thin metal wire 7, The whole of them is sealed with a package body 8 made of synthetic resin as shown by a two-dot chain line in FIGS.
【0014】次いで、前記各リード端子1bを、リード
フレーム1から切り離すたのち、図2に二点鎖線で示す
ように、折り曲げすることにより、半導体装置の完成品
にするのである。なお、前記実施の形態は、両ICチッ
プ2,3における各外部接続用電極部5,6に対してリ
ードフレーム1におけるリード端子1bを、ワイヤボン
ディングにて接続する場合であったが、本発明はこれに
限らず、合成樹脂のフレキシブルフィルムの表面に形成
した金属箔製のリード端子を、前記両ICチップ2,3
における各外部接続用電極部5,6に対して、バンプに
より直接的に接続する場合にも適用できることは言うま
でもない。Next, each of the lead terminals 1b is separated from the lead frame 1 and then bent as shown by a two-dot chain line in FIG. 2 to obtain a completed semiconductor device. In the above embodiment, the lead terminals 1b of the lead frame 1 are connected to the external connection electrodes 5 and 6 of the two IC chips 2 and 3 by wire bonding. The present invention is not limited to this. The lead terminals made of metal foil formed on the surface of a synthetic resin flexible film may be connected to both IC chips 2 and 3.
Needless to say, the present invention can also be applied to a case where the external connection electrode portions 5 and 6 are directly connected by bumps.
【図1】本発明の実施の形態を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.
【図2】図1のII−II視拡大断面図である。FIG. 2 is an enlarged sectional view taken along line II-II of FIG.
1 リードフレーム 1a チップマウント部 1b リード端子 2 一つのICチップ 2a,2b,2c,2d 一つのICチップにおけ
る四隅部 3 別のICチップ 3a,3b,3c,3d 別のICチップにおける
四隅部 4 バンプ 5,6 外部接続用電極部 7 金属線 8 パッケージ体DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 One IC chip 2a, 2b, 2c, 2d Four corners in one IC chip 3 Another IC chip 3a, 3b, 3c, 3d Four corners in another IC chip 4 Bump 5, 6 External connection electrode part 7 Metal wire 8 Package body
Claims (2)
の上面に、同じく平面視で矩形に形成した別のICチッ
プを、その相互間を電気的に接続するように積み重ねて
成る半導体装置において、 前記別のICチップを、当該別のICチップにおける四
隅部が前記一つのICチップにおける四隅部と不一致と
するように前記一つのICチップに対して回しずらせた
ことを特徴とする複数のICチップを備えた半導体装置
の構造。1. A semiconductor device in which another IC chip also formed in a rectangular shape in plan view is stacked on the upper surface of one IC chip formed in a rectangular shape in plan view so as to electrically connect the IC chips to each other. The method according to claim 2, wherein the another IC chip is rotated with respect to the one IC chip such that four corners of the another IC chip do not coincide with four corners of the one IC chip. Structure of a semiconductor device provided with an IC chip.
の上面に、同じく平面視で矩形に形成した別のICチッ
プを、その相互間を電気的に接続するように積み重ねて
成る半導体装置において、 前記別のICチップを、当該別のICチップにおける四
隅部が前記一つのICチップにおける各側面から外側に
はみ出す一方、前記一つのICチップにおける四隅部が
前記別のICチップにおける各側面から外側にはみ出す
ように前記一つのICチップに対して回しずらせたこと
を特徴とする複数のICチップを備えた半導体装置の構
造。2. A semiconductor device in which another IC chip also formed in a rectangular shape in plan view is stacked on the upper surface of one IC chip formed in a rectangular shape in plan view so as to electrically connect the IC chips to each other. In the another IC chip, four corners of the another IC chip may protrude outward from each side surface of the one IC chip, while four corners of the one IC chip may extend from each side surface of the another IC chip. A structure of a semiconductor device provided with a plurality of IC chips, wherein the semiconductor device is rotated with respect to the one IC chip so as to protrude outside.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP05890697A JP3316409B2 (en) | 1997-03-13 | 1997-03-13 | Structure of a semiconductor device having a plurality of IC chips |
KR10-2004-7000090A KR100467946B1 (en) | 1997-01-24 | 1998-01-22 | Method for manufacturing a semiconductor chip |
PCT/JP1998/000281 WO1998033217A1 (en) | 1997-01-24 | 1998-01-22 | Semiconductor device and method for manufacturing thereof |
US09/155,134 US6133637A (en) | 1997-01-24 | 1998-01-22 | Semiconductor device having a plurality of semiconductor chips |
EP98900725A EP0890989A4 (en) | 1997-01-24 | 1998-01-22 | Semiconductor device and method for manufacturing thereof |
KR10-1998-0707403A KR100522223B1 (en) | 1997-01-24 | 1998-01-22 | Semiconductor device and method for manufacturing thereof |
US09/612,480 US6458609B1 (en) | 1997-01-24 | 2000-07-07 | Semiconductor device and method for manufacturing thereof |
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JP05890697A JP3316409B2 (en) | 1997-03-13 | 1997-03-13 | Structure of a semiconductor device having a plurality of IC chips |
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JPH10256472A true JPH10256472A (en) | 1998-09-25 |
JP3316409B2 JP3316409B2 (en) | 2002-08-19 |
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Cited By (7)
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US6677674B2 (en) | 2001-06-13 | 2004-01-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor package having two chips internally connected together with bump electrodes and both chips externally connected to a lead frame with bond wires |
WO2004107440A1 (en) * | 2003-05-28 | 2004-12-09 | Sharp Kabushiki Kaisha | Electronic parts, module, module assembling method, identification method, and environment setting method |
KR100464561B1 (en) * | 2000-04-11 | 2004-12-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and manufacturing method the same |
JP2006295136A (en) * | 2005-03-18 | 2006-10-26 | Canon Inc | Stacked semiconductor package |
US7145247B2 (en) | 2003-11-28 | 2006-12-05 | Nec Electronics Corporation | Offset-bonded, multi-chip semiconductor device |
US8981574B2 (en) | 2012-12-20 | 2015-03-17 | Samsung Electronics Co., Ltd. | Semiconductor package |
JPWO2013153742A1 (en) * | 2012-04-11 | 2015-12-17 | パナソニックIpマネジメント株式会社 | Semiconductor device |
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1997
- 1997-03-13 JP JP05890697A patent/JP3316409B2/en not_active Expired - Fee Related
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100464561B1 (en) * | 2000-04-11 | 2004-12-31 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and manufacturing method the same |
US6677674B2 (en) | 2001-06-13 | 2004-01-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor package having two chips internally connected together with bump electrodes and both chips externally connected to a lead frame with bond wires |
KR100497974B1 (en) * | 2001-06-13 | 2005-07-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
WO2004107440A1 (en) * | 2003-05-28 | 2004-12-09 | Sharp Kabushiki Kaisha | Electronic parts, module, module assembling method, identification method, and environment setting method |
US7145247B2 (en) | 2003-11-28 | 2006-12-05 | Nec Electronics Corporation | Offset-bonded, multi-chip semiconductor device |
JP2006295136A (en) * | 2005-03-18 | 2006-10-26 | Canon Inc | Stacked semiconductor package |
JPWO2013153742A1 (en) * | 2012-04-11 | 2015-12-17 | パナソニックIpマネジメント株式会社 | Semiconductor device |
US8981574B2 (en) | 2012-12-20 | 2015-03-17 | Samsung Electronics Co., Ltd. | Semiconductor package |
US9633973B2 (en) | 2012-12-20 | 2017-04-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
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