JPH04164345A - Resin-sealed semiconductor device and its manufacture - Google Patents
Resin-sealed semiconductor device and its manufactureInfo
- Publication number
- JPH04164345A JPH04164345A JP2292408A JP29240890A JPH04164345A JP H04164345 A JPH04164345 A JP H04164345A JP 2292408 A JP2292408 A JP 2292408A JP 29240890 A JP29240890 A JP 29240890A JP H04164345 A JPH04164345 A JP H04164345A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- electrode
- semiconductor device
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000011347 resin Substances 0.000 claims abstract description 26
- 229920005989 resin Polymers 0.000 claims abstract description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000010931 gold Substances 0.000 claims abstract description 21
- 229910052737 gold Inorganic materials 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 238000007747 plating Methods 0.000 abstract description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、金属ワイヤを有しない樹脂打止半導体装置お
よびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a resin-molded semiconductor device having no metal wires and a method for manufacturing the same.
従来の技術 以下、従来の樹脂封止半導体装置について説明する。Conventional technology A conventional resin-sealed semiconductor device will be described below.
第２図（ａ＞〜（ｃ）は従来の樹脂打止半導体装置の組
立工程断面図であり、１はリード、２は半導体チップ、
３は金などの金属ワイヤ、４は絶縁性の樹脂である。Figures 2 (a> to (c)) are cross-sectional views of the assembly process of a conventional resin-molded semiconductor device, in which 1 is a lead, 2 is a semiconductor chip,
3 is a metal wire such as gold, and 4 is an insulating resin.
まず第２図（ａ）に示すように、リード１上に半導体チ
ップ２を接着した後に、半導体チップ２上の電極とリー
ド１の間を金ワイヤ３で接続する。First, as shown in FIG. 2(a), after bonding the semiconductor chip 2 onto the leads 1, the electrodes on the semiconductor chip 2 and the leads 1 are connected using gold wires 3.
次に第２図（ｂ）に示すように樹脂４で封止する。Next, as shown in FIG. 2(b), it is sealed with resin 4.
さらに第２図（Ｃ）に示すようにリード１を切断し曲げ
加工を行なう。Furthermore, the lead 1 is cut and bent as shown in FIG. 2(C).
発明が解決しようとする課題
このような従来の樹脂打止半導体装置では、樹脂４によ
る封止の際、複数の金ワイヤ３どうしの接触や金ワイヤ
３の剥れおよびリード１の加工精度等のため、小型化に
限界があるという問題かあった。例えば現時点てはり一
ド１のビンのピッチは０．５−である。Problems to be Solved by the Invention In such a conventional resin-molded semiconductor device, when sealing with the resin 4, there are problems such as contact between a plurality of gold wires 3, peeling of the gold wires 3, and processing accuracy of the leads 1. Therefore, there was a problem that there was a limit to miniaturization. For example, at present, the pitch of the 1-do-1 bin is 0.5-.
本発明は上記従来の課題を解決するもので、より小型の
樹脂封止半導体装置を製造するために金属ワイヤの不要
な樹脂封止半導体装置を提供することを目的とする。The present invention is intended to solve the above-mentioned conventional problems, and an object of the present invention is to provide a resin-sealed semiconductor device that does not require metal wires in order to manufacture a smaller resin-sealed semiconductor device.
課題を解決するための手段
本発明は上記目的を達成するために、金バンプ等を電極
とした半導体チップと、その半導体チ、。Means for Solving the Problems In order to achieve the above objects, the present invention provides a semiconductor chip using gold bumps or the like as electrodes, and a semiconductor chip thereof.
ブの下面に接着したリードと、そのリードおよび前記電
極上部を除いた半導体チップを封止した絶縁体の樹脂と
、絶縁体の樹脂が除かれた前記半導体チップの電極上に
形成された外部接続用の電極とを有する構成よりなる。A lead bonded to the bottom surface of the board, an insulating resin that encapsulates the semiconductor chip except for the lead and the upper part of the electrode, and an external connection formed on the electrode of the semiconductor chip from which the insulating resin has been removed. It consists of a structure having an electrode for
作用
本発明は上記構成により、樹脂封止半導体装置の外部電
極のピッチを小さくでき、しかも外部電極にリードを用
いないため、従来より小型の樹脂封止半導体装置を製造
することが可能となる。According to the present invention, with the above configuration, the pitch of the external electrodes of the resin-sealed semiconductor device can be reduced, and since no leads are used for the external electrodes, it is possible to manufacture a resin-sealed semiconductor device that is smaller than the conventional one.
実施例
以下、本発明の一実施例について図面を参照しながら説
明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.
第１図Ｃａ）〜（ｅ）は本発明の一実施例における樹脂
封止半導体装置の工程断面図を示すものである。FIGS. 1C to 1E are cross-sectional views showing the steps of a resin-sealed semiconductor device according to an embodiment of the present invention.
図において、１１はリード、１２は半導体チ・ツブ、１
３は金バンプ等の半導体チ・ツブ１２の電極、１４は絶
縁性の樹脂、１５は金メ・ツキ等の外部接続用の電極で
ある。In the figure, 11 is a lead, 12 is a semiconductor chip, 1
3 is an electrode of the semiconductor chip 12 such as a gold bump, 14 is an insulating resin, and 15 is an electrode for external connection such as gold plating.
製造工程としては、まず第１図（ａ）に示すよう ゛に
、金バンプ１３を電極とした半導体チ・ツブ１２をリー
ド１１に接着する。In the manufacturing process, first, as shown in FIG. 1(a), a semiconductor chip 12 with a gold bump 13 as an electrode is bonded to a lead 11.
次に第１図（ｂ）に示すように樹脂１４を用む）封止を
行なう。Next, as shown in FIG. 1(b), sealing is performed using resin 14.
さらに第１図（Ｃ）に示すように半導体チ・ツブ１２の
金バンプ１３上の樹脂を除去する。このため、半導体チ
ップ１２はリード１１上の定められた位置に接着されな
ければならない。しかし実際（こ（よずれが生じるため
、Ｘ線透視装置を用Ｌ１半導体チップ１２の、金バンプ
１３を検出する。また樹脂を部分的に除去するために、
その他の部分を硝酸により分解しないレジストで被覆し
上記方法により検出した電極１３上の樹脂を発煙硝酸に
、より化学的に除去する。微細な樹脂の穴を開孔するに
は、電極１３上の樹脂の膜厚は品質等に問題ない範囲で
てきるだけ薄くしなければならない。このとき、金バン
プ１３は半導体チップを発煙硝酸より保護するのに有効
に働く。Furthermore, as shown in FIG. 1(C), the resin on the gold bumps 13 of the semiconductor chip 12 is removed. For this reason, the semiconductor chip 12 must be bonded to a predetermined position on the leads 11. However, in reality (this occurs), an X-ray fluoroscope is used to detect the gold bumps 13 on the L1 semiconductor chip 12. Also, in order to partially remove the resin,
Other parts are covered with a resist that is not decomposed by nitric acid, and the resin on the electrode 13 detected by the above method is chemically removed using fuming nitric acid. In order to form fine holes in the resin, the thickness of the resin film on the electrode 13 must be made as thin as possible without causing any quality problems. At this time, the gold bumps 13 work effectively to protect the semiconductor chip from fuming nitric acid.
その後に電極１３上にメツキ等の手法を用い外部接続用
の電極１５を第１図（ｄ）に示すように設ける。Thereafter, an electrode 15 for external connection is provided on the electrode 13 using a method such as plating, as shown in FIG. 1(d).
最後に第１図（ｅ）に示すようにリード１１を切断し、
金属ワイヤを有しない樹脂封止半導体装置の構成が可能
となる。Finally, the lead 11 is cut as shown in FIG. 1(e),
It becomes possible to construct a resin-sealed semiconductor device without metal wires.
以上のように本実施例によれば、半導体チップ１２は金
などの金属ワイヤを用いずに半導体チップ１２の電極１
３を外部に取り出すことかでき、しかも金属ワイヤやリ
ード１１の持つ小型化に伴う問題を回避することにより
、従来より小型の樹脂封止半導体装置を構成できる。As described above, according to this embodiment, the semiconductor chip 12 can be connected to the electrodes 1 of the semiconductor chip 12 without using metal wires such as gold.
3 can be taken out to the outside, and the problems associated with miniaturization of metal wires and leads 11 can be avoided, thereby making it possible to construct a resin-sealed semiconductor device that is smaller than the conventional one.
発明の効果
以上の実施例から明らかなように本発明によれば金バン
プ等を電極とした半導体チップと、その半導体チップの
下面に接着したリードと、そのリードおよび前記電極上
部を除いた半導体チップを封止した絶縁性の樹脂と、絶
縁性の樹脂が除かれた半導体チップの電極に形成された
外部接続用の電極とを有する構成であるから、金などの
金属ワイヤを用いずに樹脂封止半導体装置を構成するこ
とができ、信頼性が高く小型、高性能の樹脂封止半導体
装置を提供できる。Effects of the Invention As is clear from the above embodiments, the present invention provides a semiconductor chip using gold bumps or the like as electrodes, leads bonded to the lower surface of the semiconductor chip, and a semiconductor chip excluding the leads and the upper portions of the electrodes. The structure has an insulating resin sealed with an insulating resin and an electrode for external connection formed on the electrode of the semiconductor chip from which the insulating resin has been removed, so it can be sealed with a resin without using metal wires such as gold. A highly reliable, compact, and high-performance resin-sealed semiconductor device can be provided.
第１図（ａ）〜（ｅ）は本発明の一実施例における樹脂
封止半導体装置の組立工程の工程断面図、第２図（ａ）
〜（Ｃ）は従来の樹脂封止半導体装置の組立工程の工程
断面図である。
１１・・・・・・リード、１２・・・・・・半導体チッ
プ、１３・・・・・・金バンプ（電極）、１４・・・・
・・絶縁性の樹脂、１５・・・・・・外部接続用の電極
。
代理人の氏名 弁理士小蝦治明 ほか２名第１図
第２１”？１FIGS. 1(a) to (e) are process sectional views of the assembly process of a resin-sealed semiconductor device according to an embodiment of the present invention, and FIG. 2(a) is
-(C) are process cross-sectional views of the assembly process of a conventional resin-sealed semiconductor device. 11...Lead, 12...Semiconductor chip, 13...Gold bump (electrode), 14...
...Insulating resin, 15... Electrode for external connection. Name of agent: Patent attorney Haruaki Koebi and two others Figure 1, Figure 21”?1
Claims (2)
導体チップの下面に接着したリードと、 そのリードおよび前記電極の上部を除いた半導体チップ
を封止した絶縁性の樹脂と、 絶縁性の樹脂が除かれた前記半導体チップの電極上に形
成された外部接続用の電極と を少なくとも有する樹脂封止半導体装置。(1) A semiconductor chip with a gold bump or the like as an electrode, a lead bonded to the bottom surface of the semiconductor chip, an insulating resin that encapsulates the semiconductor chip except for the lead and the upper part of the electrode, and an insulating resin. A resin-sealed semiconductor device having at least an electrode for external connection formed on the electrode of the semiconductor chip from which the resin is removed.
接着する工程と、そのリードおよび半導体チップを樹脂
封止する工程と、前記半導体チップの電極上部の封止樹
脂を除去する工程と、その樹脂を除去した半導体チップ
の電極に外部接続のための電極を取り付ける工程とを有
する樹脂封止半導体装置の製造方法。(2) A step of adhering a semiconductor chip having gold bumps or the like as electrodes to a lead, a step of sealing the lead and the semiconductor chip with resin, a step of removing the sealing resin on the upper part of the electrode of the semiconductor chip, and A method for manufacturing a resin-sealed semiconductor device, comprising the step of attaching electrodes for external connection to electrodes of a semiconductor chip from which resin has been removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2292408A JPH04164345A (en) | 1990-10-29 | 1990-10-29 | Resin-sealed semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2292408A JPH04164345A (en) | 1990-10-29 | 1990-10-29 | Resin-sealed semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04164345A true JPH04164345A (en) | 1992-06-10 |
Family
ID=17781400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2292408A Pending JPH04164345A (en) | 1990-10-29 | 1990-10-29 | Resin-sealed semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04164345A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5893724A (en) * | 1995-10-28 | 1999-04-13 | Institute Of Microelectronics | Method for forming a highly reliable and planar ball grid array package |
| KR20020057358A (en) * | 2001-01-04 | 2002-07-11 | 마이클 디. 오브라이언 | Multichip module package and manufacture methode the same |
-
1990
- 1990-10-29 JP JP2292408A patent/JPH04164345A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5893724A (en) * | 1995-10-28 | 1999-04-13 | Institute Of Microelectronics | Method for forming a highly reliable and planar ball grid array package |
| KR20020057358A (en) * | 2001-01-04 | 2002-07-11 | 마이클 디. 오브라이언 | Multichip module package and manufacture methode the same |
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