JPH04159740A - Chip bonding method - Google Patents
Chip bonding methodInfo
- Publication number
- JPH04159740A JPH04159740A JP2286210A JP28621090A JPH04159740A JP H04159740 A JPH04159740 A JP H04159740A JP 2286210 A JP2286210 A JP 2286210A JP 28621090 A JP28621090 A JP 28621090A JP H04159740 A JPH04159740 A JP H04159740A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- substrate
- chip
- base material
- intermediate base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000002844 melting Methods 0.000 claims abstract description 14
- 230000008018 melting Effects 0.000 claims abstract description 14
- 239000011159 matrix material Substances 0.000 claims abstract description 10
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000010438 heat treatment Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010828 elution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はチップのボンディング方法に係り、チップに形
成された電極と、基板に７１−リクス状に形成された電
極を、中間基材を介してバンプ手段によりボンディング
するための方法に関する。Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for bonding chips, in which electrodes formed on a chip and electrodes formed in a 71-axis shape on a substrate are bonded via an intermediate base material. The present invention relates to a method for bonding by bump means.
（従来の技術）
ＩＣやＬＳＩなどのチップの電極は、高集積化の要請か
ら、益々多数且つ狭ピッチ化しており、チ・ノブによっ
ては、電極の数は数１００以」二にも達することから、
チップの電極を基板の電極に合致させてボンディングす
ることは次第に困難になってきている。(Prior Art) Due to the demand for higher integration, the electrodes of chips such as ICs and LSIs are becoming more numerous and narrower in pitch. Depending on the chip or knob, the number of electrodes can reach several hundred or more. from,
It is becoming increasingly difficult to match and bond the electrodes of a chip to the electrodes of a substrate.
このよ・うな問題を解決するために、チップを中間基材
を介して、基板にボンディングすることが知られている
。In order to solve such problems, it is known to bond a chip to a substrate via an intermediate base material.
第４図はその従来手段を示すものであって、１００はチ
ップ、１０１は中間基材、］０２は基板である。この手
段は、チップ１００の電極と中間基材１０１の電極をリ
ード１０３やワイヤにより接続した後、中間基材１０１
の下面に７１−リクス状に植設されたピン１０４を、基
板１０２にマトリクス状に開孔されたビン孔１０５に挿
着するようになっている。１０６はビン１０４をビン孔
１０５に固定するための半田である。FIG. 4 shows the conventional means, in which 100 is a chip, 101 is an intermediate base material, and ]02 is a substrate. This means connects the electrodes of the chip 100 and the electrodes of the intermediate base material 101 with leads 103 or wires, and then
Pins 104 are implanted in a 71-axis shape on the lower surface of the substrate 102, and are inserted into bottle holes 105 formed in a matrix in the substrate 102. 106 is solder for fixing the bottle 104 to the bottle hole 105.
（発明が解決しようとする課題）
ところが上記従来手段は、ピン１０４の剛性確保の為に
、かなり大きなビン径ｄか必要であり、しかも半田１０
６を十分に塗４】シておかねばならないため、半田径り
もかなり大きなものとなる。このため、中間Ｊ、ｔｌＪ
１０１の寸法はかなり大きくならざるを得す、小形コン
バクＩ・化には限界があった。(Problem to be Solved by the Invention) However, the above conventional means requires a considerably large pin diameter d in order to ensure the rigidity of the pin 104, and moreover, the solder 10
Since it is necessary to sufficiently apply 6 and 4), the solder diameter becomes quite large. Therefore, intermediate J, tlJ
The size of the 101 had to be quite large, and there was a limit to how small it could be.
そこで本発明は、チップを中間１４４を介してコンパク
トに基板にボンディングできる手段を桿（共することを
目的とする。Therefore, it is an object of the present invention to provide a means for compactly bonding a chip to a substrate via the intermediate 144.
（課題を解決するための手段）
本発明は、チップに形成された電極を、基板に７１〜リ
クス状に形成された電極にボンディングするにあたり、
−１−記チップの電極を、中間、１４．Ｈの表面に形成
された電極にバンプ手段によりボンディングする工程と
、この中間基材の裏面に」−記基板の電極を同一・ピッ
チで７トリクス状に形成された電極と、」−記基板の電
極にバンプ手段によりボンディングする工程とを組み合
わせ、
上記２回のバンプ手段におけるバンプの融点に差異を付
与したものである。(Means for Solving the Problems) In the present invention, when bonding an electrode formed on a chip to an electrode formed in a shape of 71 to 14 on a substrate, the electrode of the chip described in -1- is bonded to the middle electrode, 14. A step of bonding to the electrode formed on the surface of the intermediate substrate by bump means, and an electrode formed on the back surface of this intermediate base material in a 7-trix shape with the same pitch, and This method combines the step of bonding to the electrode with a bump means, and gives a difference in the melting point of the bump in the two bump means described above.
（作用）
上記構成において、例えばチップの電極を第１回目のバ
ンプ手段により中間基材の電極にボンディングし、次い
で中間基材の電極を、第２回目のバンプ手段により基板
の電極にボンディングするが、第２回目のバンプ手段の
バンプの融点を、第１回目のバンプ手段のバンプの融点
よりも低くしておくことにより、先にボンディングした
第１回目のバンプが、後の第２回目のバンプ手段の加熱
により悪影響を受けることはなく、電極同士を確実にボ
ンディングできる。(Function) In the above configuration, for example, the electrodes of the chip are bonded to the electrodes of the intermediate base material by the first bumping means, and then the electrodes of the intermediate base material are bonded to the electrodes of the substrate by the second bumping means. By setting the melting point of the bump of the second bump means lower than the melting point of the bump of the first bump means, the first bump bonded earlier is bonded to the second bump bonded later. The electrodes can be reliably bonded to each other without being adversely affected by the heating of the means.
（実施例） 次に、図面を参照しながら本発明の実施例を説明する。(Example) Next, embodiments of the present invention will be described with reference to the drawings.
第１図において、１ばチップ、２は中間基材、３は基板
である。チップ１の下面には、電極４がデツプ１の側縁
部に沿って千鳥状に形成されている。また中間基材２の
表面には、チップ１の電極４に対応するように、電極５
が千鳥状に形成されている。また中間基材２の裏面には
、電極６がマトリクス状に形成されており、また基板３
の上面には、この電極６に対応する電極７が同一ビノヂ
でマトリクス状に形成されている。In FIG. 1, 1 is a chip, 2 is an intermediate base material, and 3 is a substrate. On the lower surface of the chip 1, electrodes 4 are formed in a staggered manner along the side edges of the depth 1. Further, an electrode 5 is provided on the surface of the intermediate base material 2 so as to correspond to the electrode 4 of the chip 1.
are formed in a staggered manner. Furthermore, electrodes 6 are formed in a matrix on the back surface of the intermediate base material 2, and the substrate 3
On the upper surface of the electrode 6, electrodes 7 corresponding to the electrode 6 are formed in a matrix with the same width.
第２図は、第１回目のバンプ手段によるボンディングを
示している。１１はバンプであり、チップ１の電極４と
、中間基材２の電極５をボンディングしている。１２は
電極５の表面に形成された半田である。本実施例では、
チップ１の電極４に、ワイヤボンディング手段によりバ
ンプ１１を形成し、このバンプ１１を中間基材２の電極
５に着地させる。次いで加熱手段により、バンプ】１や
、電極５」二の半田１２を加熱して溶融させ、電極４と
電極５をボンディングする。FIG. 2 shows the first bonding by the bump means. Reference numeral 11 denotes a bump, which bonds the electrode 4 of the chip 1 and the electrode 5 of the intermediate base material 2. 12 is solder formed on the surface of the electrode 5. In this example,
A bump 11 is formed on the electrode 4 of the chip 1 by wire bonding means, and this bump 11 is landed on the electrode 5 of the intermediate base material 2. Next, the solder 12 on the bumps 1 and 5 is heated and melted by a heating means, and the electrodes 4 and 5 are bonded together.
第３図は、第２回目のバンプ手段によるボンディングを
示している。１３はバンプであり、中間基Ｈ’２の電極
６と、基板３の電極７をボンディングしている。１４は
電極７の表面に形成された半田である。本実施例では、
中間基材２の電極６に、ワイヤボンディング手段により
バンプ１３を形成し、このバンプ１３を電極７に着地さ
せたうえで、加熱手段によりバンプ１３と半田１４を？
容融さセてボンディングする。１５は中間基材２の表面
の電極５と裏面の電極６を接続する導電材である。FIG. 3 shows bonding by the second bump means. Reference numeral 13 denotes a bump, which bonds the electrode 6 of the intermediate group H'2 and the electrode 7 of the substrate 3. 14 is solder formed on the surface of the electrode 7. In this example,
Bumps 13 are formed on the electrodes 6 of the intermediate base material 2 by wire bonding means, and after landing the bumps 13 on the electrodes 7, the bumps 13 and solder 14 are bonded together by heating means.
Bonding is carried out after melting. 15 is a conductive material that connects the electrode 5 on the front surface of the intermediate base material 2 and the electrode 6 on the back surface.
ここで、バンプ１３の融点ば、バンプ１１の融点よりも
低くしである。すなわち、バンプ１１により電極４と電
極５をボンディングした後、バンプ１３により、電極６
と電極７をボンディングするごとから、先にボンディン
グされたバンプ１１は、再度加熱されることとなるが、
ごのバンプ１１の融点が、バンプ１３の融点と同等若し
くはこれよりも低いと、第２回目の加熱処理により、こ
のバンプ１１は再度溶融してしまい、その溶出によりバ
ンプ１１同士が短絡するなどの悪影害を受ける。そこで
−１−記のように融点を設定することにより、このよう
な不都合が生しないようにしている。勿論、電極６と電
極７をバンブ１３により先にボンディングし、その後で
、電極４と電極５をバンプ１１によりボンディングする
場合は、バンプ１１の融点をバンプ１３の融点よりも低
くする。Here, the melting point of the bumps 13 is lower than that of the bumps 11. That is, after bonding the electrodes 4 and 5 using the bumps 11, the bumps 13 bond the electrodes 6 to 6.
Each time the electrode 7 is bonded, the previously bonded bump 11 is heated again.
If the melting point of the bump 11 is equal to or lower than the melting point of the bump 13, the bump 11 will melt again during the second heat treatment, and the elution may cause the bumps 11 to short-circuit. suffer from bad influence. Therefore, by setting the melting point as described in -1-, such inconveniences are avoided. Of course, if the electrodes 6 and 7 are first bonded with the bumps 13 and then the electrodes 4 and 5 are bonded with the bumps 11, the melting point of the bumps 11 is made lower than the melting point of the bumps 13.
バンプ１３は、上記従来手段の半田１０６の外径よりも
かなり小さくすることが可能であり、したがって上記手
段によれば、中間基材２の寸法をより小さくして、チッ
プ１を基板３にコンパクトにボンディングできる。The bumps 13 can be made considerably smaller than the outer diameter of the solder 106 in the conventional means, and therefore, according to the above means, the dimensions of the intermediate base material 2 can be made smaller and the chip 1 can be compactly attached to the substrate 3. Can be bonded to.
（発明の効果）
以上説明したように本発明は、上記チップの電極を、中
間基材の表面に形成された電極にバンプ手段によりボン
ディングする工程と、この中間基土オの裏面に上記基板
の電極と同一ピッチでマＩ・リクス状に形成された電極
を、上記基板の電極にバンプ手段によりボンディングす
る工程とを組み合わせ、
」上記２回のバンプ手段におけるバンプの融点に差異を
付与しているので、中間基材の寸法を小さくし、チップ
をコンパクトに基板にボンディングすることができる。(Effects of the Invention) As explained above, the present invention includes the steps of bonding the electrodes of the chip to the electrodes formed on the surface of the intermediate base material by bump means, and the step of bonding the electrodes of the chip to the electrodes formed on the surface of the intermediate base material, and the step of bonding the electrodes of the chip to the electrodes formed on the surface of the intermediate base material. By combining the step of bonding the electrodes formed in a matrix shape with the same pitch as the electrodes to the electrodes of the substrate by bumping means, ``a difference is given to the melting point of the bumps in the above two bumping means. Therefore, the size of the intermediate base material can be reduced and the chip can be bonded to the substrate in a compact manner.
図は本発明の実施例を示すものであって、第１図は全体
斜視図、第２図は第１回目のボンディングの側面図、第
３図は゛第２回目のボンディングの側面図、第４図は従
来手段のボンディングの側面図である。
１・・・チップ
２・・・中間基材
３・・・基板
４．５．６．７・・・電極
１１．１３・・・バンプThe figures show an embodiment of the present invention, in which Fig. 1 is an overall perspective view, Fig. 2 is a side view of the first bonding, Fig. 3 is a side view of the second bonding, and Fig. 4 is a side view of the second bonding. The figure is a side view of bonding by conventional means. 1... Chip 2... Intermediate base material 3... Substrate 4.5.6.7... Electrode 11.13... Bump
Claims (1)
された電極にボンディングするにあたり、 上記チップの電極を、中間基材の表面に形成された電極
にバンプ手段によりボンディングする工程と、この中間
基材の裏面に上記基板の電極と同一ピッチでマトリクス
状に形成された電極を、上記基板の電極にバンプ手段に
よりボンディングする工程とを組み合わせ、上記２回の
バンプ手段におけるバンプの融点に差異を付与したこと
を特徴とするチップのボンディング方法。[Claims] When bonding electrodes formed on a chip to electrodes formed in a matrix on a substrate, the electrodes of the chip are bonded to electrodes formed on the surface of an intermediate base material by bump means. and a step of bonding electrodes formed in a matrix on the back surface of this intermediate base material at the same pitch as the electrodes of the substrate to the electrodes of the substrate by bump means, and the bumps in the bump means of the above two times are combined. A chip bonding method characterized in that the melting points of the chips are differentiated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2286210A JPH04159740A (en) | 1990-10-23 | 1990-10-23 | Chip bonding method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2286210A JPH04159740A (en) | 1990-10-23 | 1990-10-23 | Chip bonding method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04159740A true JPH04159740A (en) | 1992-06-02 |
Family
ID=17701397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2286210A Pending JPH04159740A (en) | 1990-10-23 | 1990-10-23 | Chip bonding method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04159740A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282072A (en) | 2003-03-14 | 2004-10-07 | General Electric Co <Ge> | Interposer, interposer package, and device assembly employing the same |
-
1990
- 1990-10-23 JP JP2286210A patent/JPH04159740A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282072A (en) | 2003-03-14 | 2004-10-07 | General Electric Co <Ge> | Interposer, interposer package, and device assembly employing the same |
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