JP2000208544A - Bare ic chip and semiconductor device - Google Patents
Bare ic chip and semiconductor deviceInfo
- Publication number
- JP2000208544A JP2000208544A JP11007785A JP778599A JP2000208544A JP 2000208544 A JP2000208544 A JP 2000208544A JP 11007785 A JP11007785 A JP 11007785A JP 778599 A JP778599 A JP 778599A JP 2000208544 A JP2000208544 A JP 2000208544A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bare
- electrodes
- wiring board
- anisotropic conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板と対向す
る能動面に複数個の電極を備えて成るベアＩＣチップ、
および該ベアＩＣチップを配線基板にフリップチップ実
装して成る半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bare IC chip having a plurality of electrodes on an active surface facing a wiring board.
And a semiconductor device formed by flip-chip mounting the bare IC chip on a wiring board.
【０００２】[0002]
【従来の技術】近年における半導体装置の小型化、薄型
化の要求に応えるものとして、ベアＩＣチップを配線基
板に直接に実装するフリップチップ実装方法（フリップ
チップボンディング法）が提供されている。2. Description of the Related Art A flip-chip mounting method (flip-chip bonding method) for directly mounting a bare IC chip on a wiring board has been provided to meet recent demands for miniaturization and thinning of semiconductor devices.
【０００３】図１０(ａ)および(ｂ)に示す如く、フリッ
プチップ実装されるベアＩＣチップＡは、能動面Ａａに
複数個の電極Ａｂ，Ａｂ…が設けられており、各電極Ａ
ｂ，Ａｂ…の表面には各々バンプＡｃ，Ａｃ…が形成さ
れている。As shown in FIGS. 10A and 10B, a bare IC chip A to be flip-chip mounted has a plurality of electrodes Ab, Ab... On an active surface Aa.
are formed on the surfaces of b, Ab... respectively.
【０００４】一方、図１１から図１４に示す如く、配線
基板Ｂの実装面Ｂａには、ベアＩＣチップＡの電極Ａ
ｂ，Ａｂ…と対応する基板側電極Ｂｂ，Ｂｂ…を有する
配線パターンＢｃが形成され、後述する異方性導電接合
材料Ｃの供給される範囲を除いた部分はソルダーレジス
トＢｄで覆われている。On the other hand, as shown in FIGS. 11 to 14, the mounting surface Ba of the wiring board B is provided with the electrodes A of the bare IC chip A.
A wiring pattern Bc having substrate-side electrodes Bb, Bb,... corresponding to b, Ab,... is formed, and a portion excluding a range to which an anisotropic conductive bonding material C described later is supplied is covered with a solder resist Bd. .
【０００５】上述したベアＩＣチップＡを配線基板Ｂに
フリップチップ実装する場合には、図１１および図１２
に示す如く、先ず絶縁性樹脂Ｃａに導電粒子Ｃｂ，Ｃｂ
…を混在させて成る異方性導電接合材料(異方性導電フ
ィルム)Ｃを、配線基板Ｂの実装面Ｂａに供給して仮接
着する。When the above-described bare IC chip A is flip-chip mounted on a wiring board B, FIGS.
As shown in the figure, first, conductive particles Cb, Cb are added to insulating resin Ca.
Are mixed and supplied to the mounting surface Ba of the wiring board B and temporarily bonded.
【０００６】次いで、図１３に示す如く、異方性導電接
合材料Ｃの上にベアＩＣチップＡを載置したのち、図１
４に示す如く、ボンディング装置Ｄを用いてベアＩＣチ
ップＡを加圧し、かつ異方性導電接合材料Ｃを加熱す
る。Next, as shown in FIG. 13, after the bare IC chip A is mounted on the anisotropic conductive bonding material C,
As shown in FIG. 4, the bare IC chip A is pressed using the bonding apparatus D, and the anisotropic conductive bonding material C is heated.
【０００７】かくすることにより、ベアＩＣチップＡと
配線基板Ｂとが、異方性導電接合材料Ｃの絶縁性樹脂Ｃ
ａによって接合され、かつ電極Ａｂ（バンプＡｃ）と基
板側電極Ｂｂと間に異方性導電接合材料Ｃの導電粒子Ｃ
ｂが介在することにより電気的に接続される。[0007] Thus, the bare IC chip A and the wiring board B are separated from each other by the insulating resin C of the anisotropic conductive bonding material C.
a and the conductive particles C of the anisotropic conductive bonding material C between the electrode Ab (bump Ac) and the substrate-side electrode Bb.
Electrical connection is achieved by the presence of b.
【０００８】[0008]
【発明が解決しようとする課題】ところで、上述の如く
異方性導電接合材料Ｃを介してベアＩＣチップＡを配線
基板Ｂにフリップチップ実装する場合、ボンディング装
置Ｄによる加圧／加熱工程において、異方性導電接合材
料Ｃの絶縁性樹脂Ｃａが溶融して流動することで、ベア
ＩＣチップＡと配線基板Ｂとの間に絶縁性樹脂Ｃａが充
填される。When the bare IC chip A is flip-chip mounted on the wiring board B via the anisotropic conductive bonding material C as described above, the pressing / heating process by the bonding apparatus D By melting and flowing the insulating resin Ca of the anisotropic conductive bonding material C, the insulating resin Ca is filled between the bare IC chip A and the wiring board B.
【０００９】しかし、上述したベアＩＣチップＡでは、
図１０に示す如く電極Ａｂ，Ａｂ…が、能動面Ａａの外
周縁部に沿って配列配置されており、しかも外観の小型
化を達成しつつ必要数の電極を確保するべく、隣合う電
極Ａｂ，Ａｂ同士の間隔は極めて狭く設定されている。However, in the above-mentioned bare IC chip A,
As shown in FIG. 10, the electrodes Ab, Ab... Are arranged along the outer peripheral edge of the active surface Aa, and adjacent electrodes Ab are arranged so as to secure a required number of electrodes while miniaturizing the appearance. , Ab are set to be extremely narrow.
【００１０】このため、上述したボンディング装置Ｄに
よる加圧／加熱工程において、溶融した絶縁性樹脂Ｃａ
の流動が、列を成す電極Ａｂ，Ａｂ…によって堰き止め
られる格好となり、ベアＩＣチップＡの中央から外周に
向かって流動する絶縁性樹脂Ｃａが、電極Ａｂ，Ａｂ…
に妨げられてベアＩＣチップＡの外周部分に供給されな
い、あるいはベアＩＣチップＡの外周から中央に向かっ
て流動する絶縁性樹脂Ｃａが、電極Ａｂ，Ａｂ…に妨げ
られることによって、これら電極Ａｂ，Ａｂ…の内側の
領域に供給されない等の虞れがあった。For this reason, in the pressing / heating step by the bonding apparatus D, the molten insulating resin Ca is used.
Of the bare IC chip A flows from the center to the outer periphery of the bare IC chip A, and the electrodes Ab, Ab.
Are prevented from being supplied to the outer peripheral portion of the bare IC chip A, or the insulating resin Ca flowing from the outer periphery of the bare IC chip A toward the center is blocked by the electrodes Ab, Ab. Ab is not supplied to the area inside.
【００１１】このように、ベアＩＣチップＡと配線基板
Ｂとの接合部全域に、異方性導電接合材料Ｃが均一に充
填されない場合、ベアＩＣチップＡと配線基板Ｂとの結
合強度が低下したり、電気的な接続が不確実なものとな
る等、接合信頼性の低下を招いてしまう不都合があっ
た。As described above, when the entire bonding portion between the bare IC chip A and the wiring board B is not uniformly filled with the anisotropic conductive bonding material C, the bonding strength between the bare IC chip A and the wiring board B decreases. Or the electrical connection becomes unreliable, resulting in inconvenience of lowering the bonding reliability.
【００１２】本発明は上記実状に鑑みて、異方性導電接
合材料を介してベアＩＣチップを配線基板にフリップチ
ップ実装した際に、ベアＩＣチップと配線基板との高い
接合信頼性を得ることの可能な、ベアＩＣチップおよび
半導体装置の提供を目的とするものである。In view of the above situation, the present invention is to obtain high bonding reliability between a bare IC chip and a wiring board when the bare IC chip is flip-chip mounted on the wiring board via an anisotropic conductive bonding material. It is an object of the present invention to provide a bare IC chip and a semiconductor device which can be used.
【００１３】[0013]
【課題を解決するための手段】上記目的を達成するべ
く、請求項１の発明に関わるベアＩＣチップは、配線基
板と対向する能動面に、複数個の電極を格子状に配設し
ている。In order to achieve the above object, in a bare IC chip according to the first aspect of the present invention, a plurality of electrodes are arranged in a grid on an active surface facing a wiring board. .
【００１４】また、請求項２の発明に関わるベアＩＣチ
ップは、配線基板と対向する能動面に、複数個の電極を
同心円状に配設している。In the bare IC chip according to the second aspect of the present invention, a plurality of electrodes are arranged concentrically on the active surface facing the wiring substrate.
【００１５】さらに、請求項３の発明に関わるベアＩＣ
チップは、配線基板と対向する能動面に、複数個の電極
を千鳥状に配設している。Furthermore, a bare IC according to the invention of claim 3
The chip has a plurality of electrodes arranged in a staggered pattern on an active surface facing the wiring substrate.
【００１６】一方、請求項４の発明に関わる半導体装置
は、配線基板と対向する能動面に複数個の電極を格子状
に配設したベアＩＣチップを、該ベアＩＣチップにおけ
る複数個の電極に対応した基板側電極を備えて成る配線
基板に、異方性導電接合材料を介してフリップチップ実
装している。On the other hand, a semiconductor device according to a fourth aspect of the present invention is a semiconductor device, comprising: a bare IC chip having a plurality of electrodes arranged in a grid on an active surface facing a wiring board; It is flip-chip mounted on a wiring board provided with a corresponding substrate-side electrode via an anisotropic conductive bonding material.
【００１７】また、請求項５の発明に関わる半導体装置
は、配線基板と対向する能動面に複数個の電極を同心円
状に配設したベアＩＣチップを、該ベアＩＣチップにお
ける複数個の電極に対応した基板側電極を備えて成る配
線基板に、異方性導電接合材料を介してフリップチップ
実装している。According to a fifth aspect of the present invention, in a semiconductor device, a bare IC chip having a plurality of electrodes arranged concentrically on an active surface facing a wiring board is provided on a plurality of electrodes of the bare IC chip. It is flip-chip mounted on a wiring board provided with a corresponding substrate-side electrode via an anisotropic conductive bonding material.
【００１８】さらに、請求項６の発明に関わる半導体装
置は、配線基板と対向する能動面に複数個の電極を千鳥
状に配設したベアＩＣチップを、該ベアＩＣチップにお
ける複数個の電極に対応した基板側電極を備えて成る配
線基板に、異方性導電接合材料を介してフリップチップ
実装している。Furthermore, in the semiconductor device according to the invention of claim 6, a bare IC chip having a plurality of electrodes arranged in a staggered pattern on an active surface facing a wiring board is provided as a plurality of electrodes in the bare IC chip. It is flip-chip mounted on a wiring board provided with a corresponding substrate-side electrode via an anisotropic conductive bonding material.
【００１９】[0019]
【発明の実施の形態】以下、実施例を示す図面に基づい
て、本発明を詳細に説明する。図１(ａ)および(ｂ)に示
す如く、本発明に関わるベアＩＣチップ１は、チップ本
体１Ａの能動面１Ａａに、Ａｌ(アルミニウム)等の導電
材料から成る複数個の電極１Ｂ，１Ｂ…が設けられてお
り、各々の電極１Ｂ，１Ｂ…は、矩形を呈するチップ本
体１Ａの能動面１Ａａに、その全体に分散する態様で格
子状に配設されている。さらに、各電極１Ｂ，１Ｂ…の
表面には、Ａｕ(金)またはＳｎ−Ｐｂ(錫−鉛)合金等の
金属材料によってバンプ１Ｃ，１Ｃ…が形成されてい
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments. As shown in FIGS. 1A and 1B, a bare IC chip 1 according to the present invention has a plurality of electrodes 1B, 1B,... Made of a conductive material such as Al (aluminum) on an active surface 1Aa of a chip body 1A. Are arranged on the active surface 1Aa of the rectangular chip body 1A in a grid pattern so as to be dispersed throughout the active surface 1Aa. Further, bumps 1C, 1C,... Are formed on the surfaces of the electrodes 1B, 1B,... By a metal material such as Au (gold) or Sn—Pb (tin—lead) alloy.
【００２０】一方、本発明に関わる半導体装置１０は、
図２に示す如く、上述したベアＩＣチップ１を、後述す
る配線基板２に異方性導電接合材料３を介してフリップ
チップ実装して成るものである。On the other hand, the semiconductor device 10 according to the present invention
As shown in FIG. 2, the above-described bare IC chip 1 is flip-chip mounted on a wiring board 2 described below via an anisotropic conductive bonding material 3.
【００２１】配線基板２は、ガラスエポキシ樹脂等によ
り構成される基板ベース２Ａの実装面２Ａａに、導電材
料から成る配線パターン２Ｐが形成され、配線パターン
２Ｐの先端表面に金メッキを施すことで、ベアＩＣチッ
プ１の電極１Ｂ，１Ｂ…と対応する基板側電極２Ｂ，２
Ｂ…が構成されている。なお、配線パターン２Ｐは、異
方性導電接合材料３の供給される範囲を除いた部分が、
ソルダーレジスト２Ｃによって覆われている。The wiring board 2 is formed by forming a wiring pattern 2P made of a conductive material on a mounting surface 2Aa of a substrate base 2A made of a glass epoxy resin or the like. The substrate-side electrodes 2B, 2 corresponding to the electrodes 1B, 1B,.
B ... are constituted. The wiring pattern 2P has a portion excluding a range in which the anisotropic conductive bonding material 3 is supplied,
It is covered with the solder resist 2C.
【００２２】また、ベアＩＣチップ１を配線基板２に実
装するための異方性導電接合材料３は、絶縁性樹脂３Ａ
に多数の導電粒子３Ｂ，３Ｂ…を混在させてフィルム状
に形成した、いわゆる異方性導電フィルムと称されるも
のである。なお、異方性導電接合材料３としては、上述
した異方性導電フィルムのみならず、ペースト状の絶縁
性樹脂に多数の導電粒子を混練した、いわゆる異方性導
電ペーストを採用することも可能である。The anisotropic conductive bonding material 3 for mounting the bare IC chip 1 on the wiring board 2 is made of an insulating resin 3A.
Are formed into a film shape by mixing a large number of conductive particles 3B, 3B,... With a so-called anisotropic conductive film. In addition, as the anisotropic conductive bonding material 3, not only the above-described anisotropic conductive film but also a so-called anisotropic conductive paste obtained by kneading a large number of conductive particles into a paste-like insulating resin can be used. It is.
【００２３】上述した半導体装置１０の製造工程は、図
１１から図１４を示して説明した、従来の半導体装置の
製造工程と基本的に変わるところはない。The manufacturing process of the semiconductor device 10 described above is basically the same as the manufacturing process of the conventional semiconductor device described with reference to FIGS.
【００２４】すなわち、先ず配線基板２の実装面２Ａａ
に、異方性導電接合材料（異方性導電フィルム）３を載
置して熱圧着する。なお、異方性導電ペーストを採用し
た場合には、塗布によって異方性導電ペーストを配線基
板２の実装面２Ａａに供給する。That is, first, the mounting surface 2Aa of the wiring board 2
Then, an anisotropic conductive bonding material (anisotropic conductive film) 3 is placed and thermocompression-bonded. When the anisotropic conductive paste is adopted, the anisotropic conductive paste is supplied to the mounting surface 2Aa of the wiring board 2 by coating.
【００２５】次いで、配線基板２をヒータステージにセ
ットして加熱するとともに、ベアＩＣチップ１をセット
したボンディングツールを下降させて、配線基板２に供
給されている異方性導電接合材料３にベアＩＣチップ１
を押し付けることにより、異方性導電接合材料３を加熱
するとともに加圧する。Next, the wiring board 2 is set on a heater stage and heated, and at the same time, the bonding tool on which the bare IC chip 1 is set is lowered, and the bare anisotropic conductive bonding material 3 supplied to the wiring board 2 IC chip 1
, The anisotropic conductive bonding material 3 is heated and pressurized.
【００２６】かくすることにより、ベアＩＣチップ１と
配線基板２とが、異方性導電接合材料３の絶縁性樹脂３
Ａにより機械的に接合され、かつ電極１Ｂ（バンプ１
Ｃ）と基板側電極２Ｂと間に異方性導電接合材料３の導
電粒子３Ｂが介在することにより、ベアＩＣチップ１と
配線基板２とが電気的に接合されることとなる。Thus, the bare IC chip 1 and the wiring board 2 are separated from the insulating resin 3 of the anisotropic conductive bonding material 3.
A, and are mechanically joined by an electrode 1B (bump 1).
By interposing conductive particles 3B of anisotropic conductive bonding material 3 between C) and substrate-side electrode 2B, bare IC chip 1 and wiring substrate 2 are electrically bonded.
【００２７】ここで、先にも述べた如く、異方性導電接
合材料３を介してベアＩＣチップ１を配線基板２にフリ
ップチップ実装する場合、異方性導電接合材料３を加熱
／加圧する工程において、異方性導電接合材料３の絶縁
性樹脂３Ａが溶融して流動することで、ベアＩＣチップ
１と配線基板２との間に絶縁性樹脂３Ａが充填されるこ
ととなる。Here, as described above, when the bare IC chip 1 is flip-chip mounted on the wiring board 2 via the anisotropic conductive bonding material 3, the anisotropic conductive bonding material 3 is heated / pressed. In the process, the insulating resin 3A of the anisotropic conductive bonding material 3 melts and flows, so that the insulating resin 3A is filled between the bare IC chip 1 and the wiring board 2.
【００２８】このとき、図１から明らかなように、ベア
ＩＣチップ１における各電極１Ｂ，１Ｂ…は、チップ本
体１Ａにおける能動面１Ａａの全体に分散する態様で格
子状に配設されているため、互いに隣接する電極１Ｂ同
士の間隔は十分に広いものとなっている。At this time, as is clear from FIG. 1, the electrodes 1B, 1B... Of the bare IC chip 1 are arranged in a grid pattern so as to be distributed over the entire active surface 1Aa of the chip body 1A. The distance between the adjacent electrodes 1B is sufficiently large.
【００２９】これにより、溶融した異方性導電接合材料
３の絶縁性樹脂３Ａは、図３中に矢印ｆ，ｆ…で示す如
く、円滑な流動を妨げられることなく、電極１Ｂ，１Ｂ
…の間を容易に通過して、ベアＩＣチップ１と配線基板
２との接合部の全体に均一に充填されることとなる。As a result, as shown by arrows f, f... In FIG. 3, the molten insulating resin 3A of the anisotropic conductive bonding material 3 does not impede the smooth flow of the electrodes 1B, 1B.
., And the entire joint between the bare IC chip 1 and the wiring board 2 is uniformly filled.
【００３０】このようにして、ベアＩＣチップ１と配線
基板２との接合部全域に、異方性導電接合材料３が均一
に充填されることにより、ベアＩＣチップ１と配線基板
２との高い接合信頼性を得ることが可能となる。In this way, the entire area of the joint between the bare IC chip 1 and the wiring board 2 is uniformly filled with the anisotropic conductive bonding material 3, so that the bare IC chip 1 and the wiring board 2 can be kept high. It is possible to obtain joint reliability.
【００３１】図４および図５に示すベアＩＣチップ１′
は、チップ本体１Ａ′における能動面１Ａａ′に、Ａｌ
(アルミニウム)等の導電材料から成る複数個の電極１
Ｂ′，１Ｂ′…が、全体に分散する態様で同心円状、詳
しくは図４中に破線で示した同心円Ｓ１，Ｓ２，Ｓ３に
沿って配設されており、各々の各電極１Ｂ′，１Ｂ′…
の表面には、Ａｕ(金)等の金属材料によってバンプ１
Ｃ′，１Ｃ′…が形成されている。The bare IC chip 1 'shown in FIGS. 4 and 5
Is formed on the active surface 1Aa 'of the chip body 1A'.
Plural electrodes 1 made of conductive material such as (aluminum)
B ', 1B', ... are arranged concentrically in such a manner as to be dispersed throughout, specifically, along concentric circles S1, S2, S3 shown by broken lines in FIG. 4, and each of the electrodes 1B ', 1B ´…
Bumps 1 made of a metal material such as Au (gold)
C ', 1C'... Are formed.
【００３２】一方、図６に示す半導体装置１０′は、上
述したベアＩＣチップ１′を配線基板２′に異方性導電
接合材料３′を介してフリップチップ実装して成るもの
であり、半導体装置１０′を構成する配線基板２′に
は、ベアＩＣチップ１′の電極１Ｂ′，１Ｂ′…と対応
する基板側電極２Ｂ′，２Ｂ′…が設けられている。On the other hand, a semiconductor device 10 'shown in FIG. 6 is formed by flip-chip mounting the bare IC chip 1' described above on a wiring board 2 'via an anisotropic conductive bonding material 3'. The wiring board 2 'constituting the device 10' is provided with board-side electrodes 2B ', 2B',... Corresponding to the electrodes 1B ', 1B',... Of the bare IC chip 1 '.
【００３３】なお、上述した半導体装置１０′の構成
は、ベアＩＣチップ１′および配線基板２′以外、図２
に示した半導体装置１０と変わるところはないので、半
導体装置１０′の構成要素において、半導体装置１０の
構成要素と同一の作用を成すものには、図６において図
２と同一の符号に′(ダッシュ)を附すことで詳細な説明
は省略する。また、上述した半導体装置１０′の製造工
程に関しても、図２に示した半導体装置１０と基本的に
同一なので、製造工程についての詳細な説明は省略す
る。The configuration of the above-described semiconductor device 10 'is the same as that of FIG. 2 except for the bare IC chip 1' and the wiring board 2 '.
6 is the same as that of the semiconductor device 10 shown in FIG. 6, the components of the semiconductor device 10 ′ having the same functions as those of the semiconductor device 10 are denoted by the same reference numerals as those in FIG. A detailed description is omitted by adding a dash. Also, the manufacturing process of the above-described semiconductor device 10 'is basically the same as that of the semiconductor device 10 shown in FIG. 2, and thus the detailed description of the manufacturing process is omitted.
【００３４】ここで、図４から明らかなように、ベアＩ
Ｃチップ１′における電極１Ｂ′，１Ｂ′…は、チップ
本体１Ａ′における能動面１Ａａ′の全体に分散して同
心円状に配設されているため、互いに隣接する電極１
Ｂ′同士の間隔は十分に広いものとなっている。Here, as is apparent from FIG.
Since the electrodes 1B ', 1B',... In the C chip 1 'are arranged concentrically and distributed over the entire active surface 1Aa' in the chip body 1A ', the electrodes 1B'
The distance between B's is sufficiently wide.
【００３５】このため、半導体装置１０′を製造するべ
く、異方性導電接合材料３′を介してベアＩＣチップ
１′を配線基板２′にフリップチップ実装する際、異方
性導電接合材料３′を加熱／加圧する工程において溶融
した絶縁性樹脂３Ａ′は、図５中に矢印ｆ，ｆ…で示す
ように、円滑な流動を妨げられることなく電極１Ｂ′，
１Ｂ′の間を容易に通過して、ベアＩＣチップ１′と配
線基板２′との接合部の全体に均一に充填され、もって
ベアＩＣチップ１′と配線基板２′との高い接合信頼性
を得ることができる。Therefore, when the bare IC chip 1 ′ is flip-chip mounted on the wiring board 2 ′ via the anisotropic conductive bonding material 3 ′ to manufacture the semiconductor device 10 ′, the anisotropic conductive bonding material 3 The insulating resin 3A 'melted in the step of heating / pressing the electrode 1B', without being hindered from flowing smoothly, as shown by arrows f, f ... in FIG.
1B ', and easily fills the entire joint between the bare IC chip 1' and the wiring board 2 ', thereby providing high joining reliability between the bare IC chip 1' and the wiring board 2 '. Can be obtained.
【００３６】図７および図８に示すベアＩＣチップ１″
は、チップ本体１Ａ″における能動面１Ａａ″の周縁部
に沿って、Ａｌ(アルミニウム)等の導電材料から成る複
数個の電極１Ｂ″，１Ｂ″…が千鳥状に配設されてい
る。また、各電極１Ｂ″，１Ｂ″…の表面には、Ａｕ
(金)等の金属材料によってバンプ１Ｃ″，１Ｃ″…が形
成されている。The bare IC chip 1 ″ shown in FIGS. 7 and 8
A plurality of electrodes 1B ", 1B"... Made of a conductive material such as Al (aluminum) are arranged in a zigzag pattern along the periphery of the active surface 1Aa "in the chip body 1A". The surface of each electrode 1B ", 1B"...
The bumps 1C ", 1C",... Are formed of a metal material such as (gold).
【００３７】一方、図９に示す半導体装置１０″は、上
述したベアＩＣチップ１″を配線基板２″に異方性導電
接合材料３″を介してフリップチップ実装して成るもの
であり、半導体装置１０″を構成する配線基板２″に
は、ベアＩＣチップ１″の電極１Ｂ″，１Ｂ″…と対応
する基板側電極２Ｂ″，２Ｂ″…が設けられている。On the other hand, a semiconductor device 10 "shown in FIG. 9 is formed by flip-chip mounting the bare IC chip 1" described above on a wiring board 2 "via an anisotropic conductive bonding material 3". The wiring board 2 "constituting the device 10" is provided with board-side electrodes 2B ", 2B",... Corresponding to the electrodes 1B ", 1B",... Of the bare IC chip 1 ".
【００３８】なお、上述した半導体装置１０″の構成
は、ベアＩＣチップ１″および配線基板２″以外、図２
に示した半導体装置１０と変わるところはないので、半
導体装置１０″の構成要素において、半導体装置１０の
構成要素と同一の作用を成すものには、図９において図
２と同一の符号に″(ツーダッシュ)を附すことで詳細な
説明は省略する。また、上述した半導体装置１０″の製
造工程に関しても、図２に示した半導体装置１０と基本
的に同一なので、製造工程についての詳細な説明は省略
する。The configuration of the semiconductor device 10 "described above is the same as that of FIG. 2 except for the bare IC chip 1" and the wiring board 2 ".
9 is the same as that of the semiconductor device 10 shown in FIG. 9, the components of the semiconductor device 10 ″ having the same functions as those of the semiconductor device 10 are denoted by the same reference numerals in FIG. A detailed description will be omitted by adding two dashes. Further, the manufacturing process of the above-described semiconductor device 10 ″ is basically the same as that of the semiconductor device 10 shown in FIG. 2, and thus the detailed description of the manufacturing process is omitted.
【００３９】ここで、図７および図８から明らかな如
く、ベアＩＣチップ１″における電極１Ｂ″，１Ｂ″…
は、チップ本体１Ａ″における能動面１Ａａ″の縁部に
千鳥状に配設されているため、多数の電極をチップ本体
の縁部に沿って一列に配置していた従来のベアＩＣチッ
プ(図１０参照)に比べて、互いに隣接する電極１Ｂ″，
１Ｂ″の間を溶融した絶縁性樹脂３Ａ″が通過し易いも
のとなっている。Here, as is clear from FIGS. 7 and 8, the electrodes 1B ", 1B".
Are arranged in a staggered manner at the edge of the active surface 1Aa "in the chip body 1A", so that a conventional bare IC chip (FIG. 1) in which a large number of electrodes are arranged in a line along the edge of the chip body. 10), the adjacent electrodes 1B ″,
The insulating resin 3A "melted between the portions 1B" is easy to pass.
【００４０】このため、半導体装置１０″を製造するべ
く、異方性導電接合材料３″を介してベアＩＣチップ
１″を配線基板２″にフリップチップ実装する際、異方
性導電接合材料３″を加熱／加圧する工程において溶融
した絶縁性樹脂３Ａ″は、図８中に矢印ｆ，ｆ…で示す
ように、円滑な流動を妨げられることなく電極１Ｂ″，
１Ｂ″…の間を容易に通過して、ベアＩＣチップ１″と
配線基板２″との接合部の全体に均一に充填され、もっ
てベアＩＣチップ１″と配線基板２″との高い接合信頼
性を得ることができる。Therefore, when the bare IC chip 1 ″ is flip-chip mounted on the wiring board 2 ″ via the anisotropic conductive bonding material 3 ″ in order to manufacture the semiconductor device 10 ″, As shown by arrows f, f... In FIG. 8, the insulating resin 3A "melted in the step of heating / pressurizing" the electrodes 1B ",
1B "..., And is uniformly filled in the entire joint portion between the bare IC chip 1" and the wiring board 2 ", so that a high bonding reliability between the bare IC chip 1" and the wiring board 2 "is obtained. Sex can be obtained.
【００４１】[0041]
【発明の効果】以上、詳述した如く、請求項１の発明に
関わるベアＩＣチップは、配線基板と対向する能動面
に、複数個の電極を格子状に配設している。また、請求
項２の発明に関わるベアＩＣチップは、配線基板と対向
する能動面に、複数個の電極を同心円状に配設してい
る。さらに、請求項３の発明に関わるベアＩＣチップ
は、配線基板と対向する能動面に、複数個の電極を千鳥
状に配設している。上記構成のベアＩＣチップによれ
ば、異方性導電接合材料を介して配線基板にフリップチ
ップ実装する場合、溶融した異方性導電接合材料の絶縁
性樹脂が、円滑な流動を妨げられることなく、隣接する
電極同士の間を容易に通過して、配線基板との接合部の
全体に均一に充填されることとなり、もって配線基板と
の高い接合信頼性を得ることが可能となる。As described above in detail, the bare IC chip according to the first aspect of the present invention has a plurality of electrodes arranged in a grid on the active surface facing the wiring substrate. In the bare IC chip according to the second aspect of the present invention, a plurality of electrodes are arranged concentrically on the active surface facing the wiring substrate. Further, in the bare IC chip according to the third aspect of the present invention, a plurality of electrodes are arranged in a staggered manner on the active surface facing the wiring substrate. According to the bare IC chip having the above configuration, when the flip-chip mounting is performed on the wiring board via the anisotropic conductive bonding material, the melted insulating resin of the anisotropic conductive bonding material does not hinder smooth flow. In addition, the electrode easily passes between adjacent electrodes and is uniformly filled in the entire joint portion with the wiring board, so that high joining reliability with the wiring board can be obtained.
【００４２】一方、上述した如く、請求項４の発明に関
わる半導体装置は、配線基板と対向する能動面に複数個
の電極を格子状に配設したベアＩＣチップを、該ベアＩ
Ｃチップにおける複数個の電極に対応した基板側電極を
備えて成る配線基板に、異方性導電接合材料を介してフ
リップチップ実装している。また、請求項５の発明に関
わる半導体装置は、配線基板と対向する能動面に複数個
の電極を同心円状に配設したベアＩＣチップを、該ベア
ＩＣチップにおける複数個の電極に対応した基板側電極
を備えて成る配線基板に、異方性導電接合材料を介して
フリップチップ実装している。さらに、請求項６の発明
に関わる半導体装置は、配線基板と対向する能動面に複
数個の電極を千鳥状に配設したベアＩＣチップを、該ベ
アＩＣチップにおける複数個の電極に対応した基板側電
極を備えて成る配線基板に、異方性導電接合材料を介し
てフリップチップ実装している。上記構成の半導体装置
によれば、異方性導電接合材料を介してベアＩＣチップ
を配線基板にフリップチップ実装する場合、溶融した異
方性導電接合材料の絶縁性樹脂が、円滑な流動を妨げら
れることなく、隣接する電極同士の間を容易に通過し
て、ベアＩＣチップと配線基板との接合部の全体に均一
に充填されることとなり、もってベアＩＣチップと配線
基板との高い接合信頼性を得ることが可能となる。On the other hand, as described above, in the semiconductor device according to the fourth aspect of the present invention, the bare IC chip having a plurality of electrodes arranged in a grid on the active surface facing the wiring board is formed by the bare IC chip.
It is flip-chip mounted on a wiring board including substrate-side electrodes corresponding to a plurality of electrodes in the C chip via an anisotropic conductive bonding material. A semiconductor device according to a fifth aspect of the present invention is a semiconductor device, comprising: a bare IC chip having a plurality of electrodes arranged concentrically on an active surface facing a wiring board; It is flip-chip mounted on a wiring board having side electrodes via an anisotropic conductive bonding material. Further, the semiconductor device according to the invention of claim 6 includes a bare IC chip in which a plurality of electrodes are arranged in a staggered manner on an active surface facing a wiring board, the substrate corresponding to the plurality of electrodes in the bare IC chip. It is flip-chip mounted on a wiring board having side electrodes via an anisotropic conductive bonding material. According to the semiconductor device having the above configuration, when the bare IC chip is flip-chip mounted on the wiring board via the anisotropic conductive bonding material, the molten insulating resin of the anisotropic conductive bonding material prevents smooth flow. Without passing through, it easily passes between the adjacent electrodes, and is uniformly filled in the entire joint between the bare IC chip and the wiring board, so that high bonding reliability between the bare IC chip and the wiring board is achieved. Character can be obtained.
【図１】(ａ)および(ｂ)は、請求項１の発明に関わるベ
アＩＣチップを示す底面図および側面図。1 (a) and 1 (b) are a bottom view and a side view showing a bare IC chip according to the invention of claim 1;
【図２】請求項４の発明に関わる半導体装置を示す概念
的な全体側面図。FIG. 2 is a conceptual overall side view showing a semiconductor device according to the invention of claim 4;
【図３】異方性導電接合材料における絶縁性樹脂の流動
態様を示す請求項１の発明に関わるベアＩＣチップの底
面図。FIG. 3 is a bottom view of the bare IC chip according to the invention of claim 1, showing a flow mode of the insulating resin in the anisotropic conductive bonding material.
【図４】請求項２の発明に関わるベアＩＣチップを示す
底面図。FIG. 4 is a bottom view showing a bare IC chip according to the invention of claim 2;
【図５】異方性導電接合材料における絶縁性樹脂の流動
態様を示す請求項２の発明に関わるベアＩＣチップの底
面図。FIG. 5 is a bottom view of the bare IC chip according to the invention of claim 2, showing a flow mode of the insulating resin in the anisotropic conductive bonding material.
【図６】請求項５の発明に関わる半導体装置を示す概念
的な全体側面図。FIG. 6 is a conceptual overall side view showing a semiconductor device according to the invention of claim 5;
【図７】請求項３の発明に関わるベアＩＣチップを示す
底面図。FIG. 7 is a bottom view showing a bare IC chip according to the invention of claim 3;
【図８】異方性導電接合材料における絶縁性樹脂の流動
態様を示す請求項３の発明に関わるベアＩＣチップの底
面図。FIG. 8 is a bottom view of the bare IC chip according to the invention of claim 3, showing a flow mode of the insulating resin in the anisotropic conductive bonding material.
【図９】請求項６の発明に関わる半導体装置を示す概念
的な全体側面図。FIG. 9 is a conceptual overall side view showing a semiconductor device according to the invention of claim 6;
【図１０】(ａ)および(ｂ)は、従来のベアＩＣチップを
示す底面図および側面図。FIGS. 10 (a) and (b) are a bottom view and a side view showing a conventional bare IC chip.
【図１１】半導体装置の製造工程を示す概念図。FIG. 11 is a conceptual diagram illustrating a manufacturing process of the semiconductor device.
【図１２】半導体装置の製造工程を示す概念図。FIG. 12 is a conceptual diagram illustrating a manufacturing process of a semiconductor device.
【図１３】半導体装置の製造工程を示す概念図。FIG. 13 is a conceptual diagram illustrating a manufacturing process of the semiconductor device.
【図１４】半導体装置の製造工程を示す概念図。FIG. 14 is a conceptual diagram illustrating a manufacturing process of a semiconductor device.
１，１′，１″…ベアＩＣチップ、 １Ａ，１Ａ′，１Ａ″…チップ本体、 １Ａａ，１Ａａ′，１Ａａ″…能動面、 １Ｂ，１Ｂ′，１Ｂ″…電極、 １Ｃ，１Ｃ′，１Ｃ″…バンプ、 ２，２′，２″…配線基板、 ２Ｐ，２Ｐ′，２Ｐ″…配線パターン、 ２Ｂ，２Ｂ′，２Ｂ″…基板側電極、 ３，３′，３″…異方性導電接合材料、 ３Ａ，３Ａ′，３Ａ″…絶縁性樹脂、 ３Ｂ，３Ｂ′，３Ｂ″…導電粒子、 １０，１０′，１０″…半導体装置。 1, 1 ', 1 "... bare IC chip, 1A, 1A', 1A" ... chip body, 1Aa, 1Aa ', 1Aa "... active surface, 1B, 1B', 1B" ... electrode, 1C, 1C ', 1C "... bump, 2,2 ', 2" ... wiring board, 2P, 2P', 2P "... wiring pattern, 2B, 2B ', 2B" ... board side electrode, 3,3', 3 "... anisotropic conductive Bonding material, 3A, 3A ', 3A "... insulating resin, 3B, 3B', 3B" ... conductive particles, 10, 10 ', 10 "... semiconductor device.
Claims (6)
電極を備え、上記配線基板に異方性導電接合材料を介し
てフリップチップ実装されるベアＩＣチップであって、 上記複数個の電極を格子状に配設したことを特徴とする
ベアＩＣチップ。1. A bare IC chip provided with a plurality of electrodes on an active surface opposed to a wiring board and flip-chip mounted on the wiring board via an anisotropic conductive bonding material, wherein the plurality of electrodes are Are arranged in a lattice pattern.
電極を備え、上記配線基板に異方性導電接合材料を介し
てフリップチップ実装されるベアＩＣチップであって、 上記複数個の電極を同心円状に配設したことを特徴とす
るベアＩＣチップ。2. A bare IC chip provided with a plurality of electrodes on an active surface facing a wiring board and flip-chip mounted on the wiring board via an anisotropic conductive bonding material, the bare IC chip comprising: Are arranged concentrically in a bare IC chip.
電極を備え、上記配線基板に異方性導電接合材料を介し
てフリップチップ実装されるベアＩＣチップであって、 上記複数個の電極を千鳥状に配設したことを特徴とする
ベアＩＣチップ。3. A bare IC chip provided with a plurality of electrodes on an active surface facing a wiring board and flip-chip mounted on the wiring board via an anisotropic conductive bonding material, the bare IC chip comprising: Are arranged in a zigzag pattern.
電極を格子状に配設したベアＩＣチップを、該ベアＩＣ
チップにおける複数個の電極に対応した基板側電極を備
えて成る配線基板に、異方性導電接合材料を介してフリ
ップチップ実装して成ることを特徴とする半導体装置。4. A bare IC chip in which a plurality of electrodes are arranged in a grid on an active surface facing a wiring board.
A semiconductor device which is flip-chip mounted on a wiring board including substrate-side electrodes corresponding to a plurality of electrodes in a chip via an anisotropic conductive bonding material.
電極を同心円状に配設したベアＩＣチップを、該ベアＩ
Ｃチップにおける複数個の電極に対応した基板側電極を
備えて成る配線基板に、異方性導電接合材料を介してフ
リップチップ実装して成ることを特徴とする半導体装
置。5. A bare IC chip having a plurality of electrodes arranged concentrically on an active surface facing a wiring board, wherein said bare IC chip is
A semiconductor device which is flip-chip mounted on a wiring board including substrate-side electrodes corresponding to a plurality of electrodes in a C chip via an anisotropic conductive bonding material.
電極を千鳥状に配設したベアＩＣチップを、該ベアＩＣ
チップにおける複数個の電極に対応した基板側電極を備
えて成る配線基板に、異方性導電接合材料を介してフリ
ップチップ実装して成ることを特徴とする半導体装置。6. A bare IC chip having a plurality of electrodes arranged in a zigzag pattern on an active surface facing a wiring substrate.
A semiconductor device which is flip-chip mounted on a wiring board including substrate-side electrodes corresponding to a plurality of electrodes in a chip via an anisotropic conductive bonding material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11007785A JP2000208544A (en) | 1999-01-14 | 1999-01-14 | Bare ic chip and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11007785A JP2000208544A (en) | 1999-01-14 | 1999-01-14 | Bare ic chip and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000208544A true JP2000208544A (en) | 2000-07-28 |
Family
ID=11675335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11007785A Withdrawn JP2000208544A (en) | 1999-01-14 | 1999-01-14 | Bare ic chip and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000208544A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066551A (en) * | 2004-08-25 | 2006-03-09 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP2007142037A (en) * | 2005-11-16 | 2007-06-07 | Shinko Electric Ind Co Ltd | Mounting substrate and semiconductor device |
| JP2009208285A (en) * | 2008-03-03 | 2009-09-17 | Seiko Epson Corp | Thermal head and thermal printer |
-
1999
- 1999-01-14 JP JP11007785A patent/JP2000208544A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066551A (en) * | 2004-08-25 | 2006-03-09 | Renesas Technology Corp | Method for manufacturing semiconductor device |
| JP4565931B2 (en) * | 2004-08-25 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP2007142037A (en) * | 2005-11-16 | 2007-06-07 | Shinko Electric Ind Co Ltd | Mounting substrate and semiconductor device |
| JP4685601B2 (en) * | 2005-11-16 | 2011-05-18 | 新光電気工業株式会社 | Mounting substrate and semiconductor device |
| JP2009208285A (en) * | 2008-03-03 | 2009-09-17 | Seiko Epson Corp | Thermal head and thermal printer |
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