JPH04142805A - Automatic gain control circuit - Google Patents
Automatic gain control circuitInfo
- Publication number
- JPH04142805A JPH04142805A JP26495590A JP26495590A JPH04142805A JP H04142805 A JPH04142805 A JP H04142805A JP 26495590 A JP26495590 A JP 26495590A JP 26495590 A JP26495590 A JP 26495590A JP H04142805 A JPH04142805 A JP H04142805A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gain
- variable gain
- detection
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 24
- 230000003321 amplification Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000003199 nucleic acid amplification method Methods 0.000 description 7
- 230000005684 electric field Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は無線受信機の自動利得制御回路（以下ＡＧＣ回
路という）に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an automatic gain control circuit (hereinafter referred to as an AGC circuit) for a radio receiver.
（従来の技術）
第２図は従来のＡＧＣ回路の一構成例を示すブロックで
あって、１は雑音除去用ろ波器、２は可変利得回路、３
は検波回路、４は時定数回路である。(Prior Art) FIG. 2 is a block diagram showing an example of the configuration of a conventional AGC circuit, in which 1 is a noise removal filter, 2 is a variable gain circuit, and 3 is a block diagram showing a configuration example of a conventional AGC circuit.
is a detection circuit, and 4 is a time constant circuit.
第２図において、入力電圧室、は雑音除去用ろ波器１を
通過した後、可変利得回路２を通過して出力電圧室。が
得られる。出力電圧苔。は検波回路３で直流に変換され
、時定数回路４を通して可変利得回路２へ負帰還される
。この結果入力電圧７１の変化が圧縮されたかたちで出
力電圧賓。が得られる。第３図は可変利得回路２の制御
特性の一例であり、直流の制御電圧Ｖにより高周波の利
得Ｇを制御することができる。In FIG. 2, the input voltage chamber passes through a noise removal filter 1 and then a variable gain circuit 2 to form an output voltage chamber. is obtained. Output voltage moss. is converted into direct current by the detection circuit 3, and is negatively fed back to the variable gain circuit 2 through the time constant circuit 4. As a result, changes in the input voltage 71 are compressed to increase the output voltage. is obtained. FIG. 3 shows an example of the control characteristics of the variable gain circuit 2, and the high frequency gain G can be controlled by the DC control voltage V.
第４図は第２図に示す従来のＡＧＣ回路の動作を説明す
るための等価回路であって、点数で囲った部分が可変利
得回路２の等価回路である。ここでは説明を簡単にする
ため雑音除去用ろ波器１は省略してあり、また検波回路
３の交流から直流への変換係数には１とし、時定数回路
４の直流における損失は無いものとする。可変利得回路
２におけるα及びβは増幅係数を示し、ループゲインは
αβで示される。増幅係数αばその入力電圧室、−β（
ｅｏ ｅｄ）と出力電圧ｄ。の比で表わされ、（１
）式のようになる。FIG. 4 is an equivalent circuit for explaining the operation of the conventional AGC circuit shown in FIG. 2, and the portion surrounded by dots is the equivalent circuit of the variable gain circuit 2. Here, to simplify the explanation, the noise removal filter 1 is omitted, and the conversion coefficient from AC to DC in the detection circuit 3 is set to 1, and it is assumed that there is no loss in the DC in the time constant circuit 4. do. α and β in the variable gain circuit 2 represent amplification coefficients, and the loop gain is represented by αβ. The amplification factor α is the input voltage chamber, −β(
eo ed) and output voltage d. It is expressed as the ratio of (1
) is as follows.
宣。Declaration.
（１）式を変形すると、
となる。ここでループゲインαβが１に比し充分大きけ
れば、
各１
宣。ζ ＋ ｅ ａ （３）
β
となる。従って、増幅係数βを充分大きくすれば、入力
電圧室１が変動しても出力電圧ｄ。がほぼ−定となり、
ＡＧＣとしての動作を得ることができる。When formula (1) is transformed, it becomes. Here, if the loop gain αβ is sufficiently large compared to 1, each 1 is declared. ζ + e a (3)
Becomes β. Therefore, if the amplification coefficient β is made sufficiently large, the output voltage d will remain the same even if the input voltage chamber 1 fluctuates. becomes almost constant,
Operation as AGC can be obtained.
（発明が解決しようとする課題）
しかしながら、上記ＡＧＣ回路において増幅係数βを充
分大きくするとループゲインαβが非常に大きくなり、
負帰還回路の帰還量も大きくなる。(Problem to be Solved by the Invention) However, if the amplification coefficient β is sufficiently increased in the above AGC circuit, the loop gain αβ becomes extremely large.
The amount of feedback from the negative feedback circuit also increases.
この帰還量が大きくなるとループの位相回転により回路
の動作が不安定になるため、安定に動作させるためには
時定数回路４の時定数を充分大きく選ぶ必要があり、こ
の結果ＡＧＣ回路の応答時間が遅（なるという問題点が
あった。If this amount of feedback becomes large, the circuit operation becomes unstable due to the phase rotation of the loop. Therefore, in order to operate stably, it is necessary to select a sufficiently large time constant for the time constant circuit 4. As a result, the response time of the AGC circuit There was a problem that it was slow.
本発明は上記の問題点を除去するために、フィードフォ
ワード回路とフィードバック回路の組合せにより応答の
高速化を図ったＡＧＣ回路を提供することを目的とする
。SUMMARY OF THE INVENTION In order to eliminate the above-mentioned problems, it is an object of the present invention to provide an AGC circuit that achieves faster response by combining a feedforward circuit and a feedback circuit.
（課題を解決するための手段）
本発明は上記目的を達成するため、入力信号を増幅して
出力信号を得る、利得が可変の可変利得回路と、前記入
力信号を検波する第１の検波回路と、前記出力信号を検
波する第２の検波回路と、前記第１の検波回路と第２の
検波回路の出力を加算する加算回路とを有し、前記加算
回路の出力で前記可変利得回路の利得を前記出力信号の
レベルが一定になるように制御するものである。(Means for Solving the Problems) In order to achieve the above object, the present invention includes a variable gain circuit with a variable gain that amplifies an input signal to obtain an output signal, and a first detection circuit that detects the input signal. and a second detection circuit that detects the output signal, and an addition circuit that adds the outputs of the first detection circuit and the second detection circuit, and the output of the addition circuit is used to add the output of the variable gain circuit. The gain is controlled so that the level of the output signal is constant.
（作 用）
第１の検波回路の検波出力を加算回路を介して可変利得
回路に加えることによりフィードフォワードである程度
その利得を制御し、第２の検波回路の検波出力を前記加
算回路を介して前記可変利得回路に加えることによりフ
ィードバックで出力信号レベル目標値との残差骨を補償
するよ・うにその利得を制御するものであり、これによ
りＡＧＣ回路の応答の高速化を図ることができる。(Function) By adding the detection output of the first detection circuit to the variable gain circuit via the addition circuit, its gain is controlled to some extent by feedforward, and the detection output of the second detection circuit is added to the variable gain circuit via the addition circuit. When added to the variable gain circuit, the gain is controlled by feedback to compensate for the residual difference between the output signal level and the target value, thereby increasing the response speed of the AGC circuit.
（実施例）
第１図は本発明の実施例を示すブロック図であって、■
は雑音除去用ろ波器、２ば可変利得回路、３は検波回路
、４は時定数回路であり、いずれも第２図において同一
の符号を付したものと同等のものである。また、５は電
界強度表示回路、６は加算回路である。ここで、電界強
度表示回路５は広い入力電圧範囲に亙って入力電圧の対
数に比例した直流電圧を得る回路であって、無線受信機
において正確な電界強度表示を必要とする場合に用いら
れるものであり、本実施例ではこの電界強度表示回路５
の出力電圧をＡＧＣ回路に利用するものである。従って
、電界強度表示回路を有しない場合は、同様な内容の回
路を設ければよい。(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention.
2 is a noise removal filter, 2 is a variable gain circuit, 3 is a detection circuit, and 4 is a time constant circuit, all of which are equivalent to those given the same reference numerals in FIG. Further, 5 is an electric field strength display circuit, and 6 is an addition circuit. Here, the field strength display circuit 5 is a circuit that obtains a DC voltage proportional to the logarithm of the input voltage over a wide input voltage range, and is used when accurate field strength display is required in a wireless receiver. In this embodiment, this electric field strength display circuit 5
The output voltage is used for the AGC circuit. Therefore, if a field strength display circuit is not provided, a circuit with similar content may be provided.
次に本実施例の動作について説明する。Next, the operation of this embodiment will be explained.
入力電圧で、は雑音除去用ろ波器１を通過した後可変利
得回路２を通過して出力電圧室。が得られる。この出力
電圧で。は検波回路３で直流に変換され、入力電圧の対
数に比例した電界強度表示回路５の出力電圧と加算回路
６で加算され、更に時定数回路４を経由して可変利得回
路２へ帰還される。この結果入力電圧ざ、の変化が圧縮
されたかたちで出力電圧７゜が得られる。The input voltage passes through a noise removal filter 1 and then a variable gain circuit 2 to an output voltage chamber. is obtained. At this output voltage. is converted into direct current by the detection circuit 3, added to the output voltage of the field strength display circuit 5 proportional to the logarithm of the input voltage by the addition circuit 6, and then fed back to the variable gain circuit 2 via the time constant circuit 4. . As a result, an output voltage of 7° can be obtained with a compressed change in input voltage pitch.
第５図は第１図の動作を説明する等価回路で点線で囲っ
た部分が可変利得回路２の等価回路である。ここでは、
説明を簡単にするために雑音除去用ろ波器１は省略して
あり、また検波回路３の交流から直流への変換係数には
１とし、時定数回路４の直流に対する損失は無いものと
し、更に電界強度表示回路５の交流から直流への変換係
数をａとし、電界強度表示回路５の出力電圧であるａｅ
。FIG. 5 is an equivalent circuit for explaining the operation of FIG. 1, and the portion surrounded by a dotted line is the equivalent circuit of the variable gain circuit 2. here,
In order to simplify the explanation, the noise removal filter 1 is omitted, and it is assumed that the conversion coefficient from AC to DC in the detection circuit 3 is 1, and there is no loss in the time constant circuit 4 for DC. Furthermore, the conversion coefficient from AC to DC of the electric field strength display circuit 5 is a, and the output voltage of the electric field strength display circuit 5 is ae.
.
のｅ８は入力電圧で、に等しいものとする。また可変利
得回路２におけるα及びβは増幅係数は示し、ループゲ
インはαβで示される。e8 is the input voltage, which is assumed to be equal to . Further, α and β in the variable gain circuit 2 represent amplification coefficients, and αβ represents a loop gain.
第５図に基づいて本実施例の動作を詳しく以下説明する
。The operation of this embodiment will be explained in detail below based on FIG.
増幅係数αばその入力電圧 ｄ、−β（ｅｏ＋ａ ｅｉ −ｅｄ ）と出力電圧ａ。Input voltage of amplification coefficient α d, -β (eo+a ei -ed) and output voltage a.
の比で表わされるため、
て−
と表わされる。（４）式を変形すると
となる。（５）式においてループゲインが１に比し充分
大きれば、
苔。Since it is expressed as a ratio of , it is expressed as te-. Transforming equation (4), we get In equation (5), if the loop gain is sufficiently larger than 1, it is moss.
筈。＝ −ａｅＩ＋ｅａ （６）β
となる。先に貨、と０８が等しいものと仮定したので、
（６）式は
となる。Should be. = −aeI+ea (6)β. First, we assumed that currency and 08 were equal, so
Equation (6) becomes.
本実施例における出力電圧省。を示す（力式と、第２図
に示す従来のＡＧＣ回路における出力電圧蒼。を示す（
３）式とを比較した場合、同一の性能を得るためには本
実施例の方が小さい増幅係数βで良いこととなり、ルー
プゲインαβを下げることができる。別な言い方をすれ
ば、本実施例の方が時定数回路４の時定数を小さくして
も回路が安定に動作するためＡＧＣの応答を高速化する
ことができる。Output voltage saving in this embodiment. (The power equation and the output voltage in the conventional AGC circuit shown in Fig. 2 are shown.)
When comparing Equation 3), in order to obtain the same performance, a smaller amplification coefficient β is required in this embodiment, and the loop gain αβ can be lowered. In other words, in this embodiment, even if the time constant of the time constant circuit 4 is made smaller, the circuit operates more stably, so that the AGC response can be made faster.
なお、フィードフォワードによる利得制御による残差分
をフィードバックで補償するためには、６ｏ＞ａ ｅｉ
の関係を保つ必要がある。In addition, in order to compensate for the residual difference due to feedforward gain control by feedback, 6o>a ei
It is necessary to maintain this relationship.
（発明の効果）
以上、詳細に説明したように本発明によれば、高速のＡ
ＧＣ応答が得られるため、フェージングによる電界強度
の変動に追随できる受信機が容易に得られる。(Effects of the Invention) As described above in detail, according to the present invention, high-speed A
Since a GC response can be obtained, a receiver that can follow fluctuations in electric field strength due to fading can be easily obtained.
また、自動車電話方式用の受信機に適用した場合、電界
強度表示回路は無線受信機に必須であるため、この電界
強度表示回路を本発明の自動利得制御に利用すれば、従
来のＡＧＣ回路に比してコストアップは殆んど無視する
ことができ、スペース的にも有利である。Furthermore, when applied to a receiver for a car telephone system, a field strength display circuit is essential to the wireless receiver, so if this field strength display circuit is used in the automatic gain control of the present invention, it can be used as a conventional AGC circuit. In comparison, the increase in cost can be almost ignored, and it is also advantageous in terms of space.
第１図は本発明の実施例のブロック図、第２図は従来の
ＡＧＣ回路のブロック図、第３図は可変利得回路の制御
特性の一例を示す図、第４図は第２図の動作説明用の等
価回路のブロック図、第５図は第１図の動作説明用の等
価回路のブロック図である。
■・・・雑音除去用ろ波器、２・・・可変利得回路、３
・・・検波回路、４・・・時定数回路、訃・・電界強度
表示回路、６・・・加算回路。Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a block diagram of a conventional AGC circuit, Fig. 3 is a diagram showing an example of control characteristics of a variable gain circuit, and Fig. 4 is the operation of Fig. 2. 5 is a block diagram of an equivalent circuit for explaining the operation of FIG. 1. FIG. ■...Noise removal filter, 2...Variable gain circuit, 3
...Detection circuit, 4.Time constant circuit, 2..Field strength display circuit, 6.Addition circuit.
Claims (2)
の可変利得回路と、 前記入力信号を検波する第１の検波回路と、前記出力信
号を検波する第２の検波回路と、前記第１の検波回路と
第２の検波回路の出力を加算する加算回路と を有し、前記加算回路の出力で前記可変利得回路の利得
を前記出力信号のレベルが一定になるように制御するこ
とを特徴とする自動利得制御回路。(1) a variable gain circuit with a variable gain that amplifies an input signal to obtain an output signal; a first detection circuit that detects the input signal; a second detection circuit that detects the output signal; It has an addition circuit that adds the outputs of the first detection circuit and the second detection circuit, and controls the gain of the variable gain circuit using the output of the addition circuit so that the level of the output signal is constant. An automatic gain control circuit featuring:
回路であることを特徴とする請求項１記載の自動利得制
御回路。(2) The automatic gain control circuit according to claim 1, wherein the first detection circuit is a field strength display circuit of a radio receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26495590A JPH04142805A (en) | 1990-10-04 | 1990-10-04 | Automatic gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26495590A JPH04142805A (en) | 1990-10-04 | 1990-10-04 | Automatic gain control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04142805A true JPH04142805A (en) | 1992-05-15 |
Family
ID=17410525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26495590A Pending JPH04142805A (en) | 1990-10-04 | 1990-10-04 | Automatic gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04142805A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01101711A (en) * | 1987-10-15 | 1989-04-19 | Nec Corp | Automatic signal stabilizing circuit |
| JPH01311709A (en) * | 1988-06-10 | 1989-12-15 | Hitachi Ltd | Automatic gain control circuit |
-
1990
- 1990-10-04 JP JP26495590A patent/JPH04142805A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01101711A (en) * | 1987-10-15 | 1989-04-19 | Nec Corp | Automatic signal stabilizing circuit |
| JPH01311709A (en) * | 1988-06-10 | 1989-12-15 | Hitachi Ltd | Automatic gain control circuit |
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