JPH04127544A - Manufacture of semiconductor crystal and semiconductor manufacturing device therefor - Google Patents
Manufacture of semiconductor crystal and semiconductor manufacturing device thereforInfo
- Publication number
- JPH04127544A JPH04127544A JP24935690A JP24935690A JPH04127544A JP H04127544 A JPH04127544 A JP H04127544A JP 24935690 A JP24935690 A JP 24935690A JP 24935690 A JP24935690 A JP 24935690A JP H04127544 A JPH04127544 A JP H04127544A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor crystal
- compound semiconductor
- crystal layer
- liquid phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000013078 crystal Substances 0.000 title claims abstract description 81
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 150000001875 compounds Chemical class 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000007791 liquid phase Substances 0.000 claims abstract description 19
- 239000000470 constituent Substances 0.000 claims abstract description 8
- 239000000155 melt Substances 0.000 claims description 14
- 238000000927 vapour-phase epitaxy Methods 0.000 claims 1
- 238000001816 cooling Methods 0.000 abstract description 6
- 239000003708 ampul Substances 0.000 description 23
- 229910004613 CdTe Inorganic materials 0.000 description 21
- 238000010586 diagram Methods 0.000 description 16
- 238000001947 vapour-phase growth Methods 0.000 description 12
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 229910052714 tellurium Inorganic materials 0.000 description 4
- 229910052793 cadmium Inorganic materials 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000012047 saturated solution Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
液相エピタキシャル成長法にて赤外線検知器用化合物半
導体結晶を製造する方法及びそれに用いる製造装置に関
し、
成長終了後の冷却過程において基板が反らないようにす
ることを目的とし、
基板の表面上に液相エピタキシャル成長法にて第１の化
合物半導体結晶層を形成する半導体結晶の製造方法にお
いて、前記第１の化合物半導体結晶層と同一の構成元素
で、かつ、略同じ厚さの第２の化合物半導体結晶層を、
液相エピタキシャル成長工程時に前記基板の裏面に形成
するよう構成する。[Detailed Description of the Invention] [Summary] Regarding a method of manufacturing a compound semiconductor crystal for an infrared detector by a liquid phase epitaxial growth method and a manufacturing apparatus used therefor, the present invention aims to prevent the substrate from warping during the cooling process after the completion of growth. A method for manufacturing a semiconductor crystal in which a first compound semiconductor crystal layer is formed on the surface of a substrate by a liquid phase epitaxial growth method, wherein the first compound semiconductor crystal layer has the same constituent elements and is substantially the same as the first compound semiconductor crystal layer. A second compound semiconductor crystal layer with a thickness of
The structure is such that it is formed on the back surface of the substrate during a liquid phase epitaxial growth process.
本発明は半導体結晶の製造方法及びそれに用いる製造装
置に係り、特に液相エピタキシャル成長法にて赤外線検
知器用化合物半導体結晶層を製造する方法及びそれに用
いる製造装置に関する。The present invention relates to a method of manufacturing a semiconductor crystal and a manufacturing apparatus used therein, and more particularly to a method of manufacturing a compound semiconductor crystal layer for an infrared detector by a liquid phase epitaxial growth method and a manufacturing apparatus used therein.
赤外線検知器にはエネルギーバンドギャップが狭い化合
物半導体結晶、例えば水銀・カドミウム・テルル（Ｈｇ
＋−ｘｃｄ工Ｔｅ）結晶が光導電素子として用いられる
。このようなＨｇ ＋イＣｄ。Infrared detectors use compound semiconductor crystals with narrow energy band gaps, such as mercury, cadmium, and tellurium (Hg).
A +-xcd (Te) crystal is used as a photoconductive element. Such Hg + ICd.
Ｔｅ結晶を製造するに際しては、例えば閉管チッピング
式の液相エピタキシャル成長（ＬＰＥ：Ｌｉｑｕｉｄ
Ｐｈａｓｅ Ｂｐｉｔａｘｙ）装置が使用されるが、表
面ができるだけ平坦なＨｇ＋−ｘ Ｃｄｘ Ｔｅ結晶を
基板上にエピタキシャル成長させることが重要となる。When manufacturing a Te crystal, for example, liquid phase epitaxial growth (LPE) using a closed tube chipping method is used.
It is important to epitaxially grow a Hg+-x Cdx Te crystal with a surface as flat as possible on the substrate.
（従来の技術〕
第８図は従来の半導体結晶製造装置の一例の構成図を示
す。同図中、ｌは円筒状の石英管（アンプル）で、その
内部に基板ホルダ２．ＣｄＴｅ基板３．エピタキシャル
結晶成長メルト４が配置されている。また、５は炉心管
、６は例えばカーボンよりなるヒートシンクブロック、
７はヒータ、８は回転装置、９は回転装置８からの回転
力をアンプルｌに伝達する回転軸である。(Prior Art) Fig. 8 shows a configuration diagram of an example of a conventional semiconductor crystal manufacturing apparatus. In the figure, l is a cylindrical quartz tube (ampule), and inside thereof there are a substrate holder 2, a CdTe substrate 3, and a cylindrical quartz tube (ampule). An epitaxial crystal growth melt 4 is arranged.Furthermore, 5 is a furnace tube, 6 is a heat sink block made of carbon, for example,
7 is a heater, 8 is a rotating device, and 9 is a rotating shaft that transmits the rotational force from the rotating device 8 to the ampoule l.
次に、この従来の製造装置の動作について、第８図中、
ＩＸ−ＩＸ線に沿う断面図を示す第９図と共に説明する
。メルト４はＨｇ、Ｃｄ、Ｔｅを所定の比重で混合後溶
融した飽和状態の溶液で、まず回転装置８により第８図
に示した状態からアンプルｌを１８０°回転して第９図
（Ａ）に示す如くＣｄＴｅ基板３の表面をメルト４に接
触させて所定温度で所定時間保持させ、ＣｄＴｅ基板３
上に所望の厚さのＨｇＣｄＴｅ層をエピタキシャル成長
させる。Next, regarding the operation of this conventional manufacturing equipment, in Fig. 8,
This will be explained with reference to FIG. 9, which shows a cross-sectional view taken along line IX-IX. Melt 4 is a saturated solution in which Hg, Cd, and Te are mixed and melted at a predetermined specific gravity. First, the ampoule 1 is rotated 180 degrees from the state shown in FIG. As shown in the figure, the surface of the CdTe substrate 3 is brought into contact with the melt 4 and held at a predetermined temperature for a predetermined period of time.
A HgCdTe layer of desired thickness is epitaxially grown on top.
続いて、回転装置８により第９図（Ｂ）に示す如くアン
プル１を再び１８０°回転し、基板２とメルト４とが接
触しないようにした状態を所定時間保持し、炉中冷却を
行なう。Subsequently, the ampoule 1 is rotated 180° again by the rotating device 8 as shown in FIG. 9(B), and a state in which the substrate 2 and the melt 4 do not come into contact is maintained for a predetermined period of time to perform cooling in the furnace.
このようにして、従来はＬＰＥ法によりＣｄＴｅ基板２
の表面に第１Ｏ図（Ａ）に１０で示す如＜Ｈｇ＋−ｘ
Ｃｄｘ Ｔｅ１ｔ ｏを成長させていた。In this way, conventionally, the CdTe substrate 2 is
on the surface of <Hg+-x as shown by 10 in Fig.
I was growing Cdx Te1to.
なお、ＣｄＴｅ基板２は、サファイア、シリコン（Ｓｔ
）又はＧａＡｓ等の異種基板上にＣｄＴｅ層が形成され
たＣｄＴｅ／異種基板を用いてもよい。Note that the CdTe substrate 2 is made of sapphire, silicon (St
) or a CdTe/different substrate in which a CdTe layer is formed on a different substrate such as GaAs.
しかるに、上記の従来方法では、成長温度（５００℃）
においては、ＨｇＣｄＴｅ層１０とＣｄＴｅ基板２との
間には応力は働いていないか、両者には熱膨張率に差か
あるため（ＨｇＣｄＴｅ ：４．３ Ｘ １ ０
− ＠ｄｅｇ −＋、 ＣｄＴｅ ：５．５
ｘ］ ０−’ｄｅｇ −’） 、室温まで冷却すると
一般には熱膨張率が大きなＣｄＴｅ基板２の方がＨｇＣ
ｄＴｅ層ＩＯよりも大きく収縮し、その結果、第１０図
（Ｂ）に示す如＜ＨｇＣｄＴｅ層ｌＯが凸状に反ってし
まう。また、ＨｇＣｄＴｅＪｉｉｌ ０の表面が平坦で
ないと、マスク合わせ等の工程で高精度に合わせできな
いという問題がある。However, in the above conventional method, the growth temperature (500°C)
In this case, either there is no stress acting between the HgCdTe layer 10 and the CdTe substrate 2, or there is a difference in thermal expansion coefficient between the two (HgCdTe: 4.3 x 10
- @deg -+, CdTe: 5.5
x] 0-'deg-'), when cooled to room temperature, the CdTe substrate 2, which has a larger coefficient of thermal expansion, generally has a higher coefficient of HgC.
It contracts more than the dTe layer IO, and as a result, the HgCdTe layer IO warps in a convex shape as shown in FIG. 10(B). Further, if the surface of HgCdTeJil 0 is not flat, there is a problem that high precision alignment cannot be performed in a process such as mask alignment.
なお、上記の反りの防止のため、ＣｄＴｅ基板２の裏面
にＳｔ層を予め形成することも知られているが、この方
法は成長温度付近でＳｔを蒸着するため、工数がかかり
、また汚染の原因にもなるという問題がある。In order to prevent the above-mentioned warping, it is known to form an St layer on the back surface of the CdTe substrate 2 in advance, but this method requires a lot of man-hours because St is evaporated near the growth temperature, and it also reduces the risk of contamination. There is also the problem of being the cause.
本発明は以上の点に鑑みなされたもので、成長終了後の
冷却過程において基板が反らないようにできる半導体結
晶の製造方法及びそれに用いる半導体製造装置を提供す
ることを目的とする。The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor crystal manufacturing method that can prevent a substrate from warping during the cooling process after the completion of growth, and a semiconductor manufacturing apparatus used therein.
第１図は本発明の原理説明図を示す。本発明方法は第１
図（Ａ）に示す如く、基板１１の表面上に液相エピタキ
シャル成長法にて第１の化合物半導体結晶層１２を形成
するに際し、第１の化合物半導体結晶層１２と同一の構
成元素で、かつ、略同じ厚さの第２の化合物半導体結晶
層１３を、液相エピタキシャル成長工程時に基板１１の
裏面に形成するようにしたものである。FIG. 1 shows a diagram explaining the principle of the present invention. The method of the present invention is the first
As shown in Figure (A), when forming the first compound semiconductor crystal layer 12 on the surface of the substrate 11 by the liquid phase epitaxial growth method, the first compound semiconductor crystal layer 12 is made of the same constituent elements as the first compound semiconductor crystal layer 12, and A second compound semiconductor crystal layer 13 having substantially the same thickness is formed on the back surface of the substrate 11 during a liquid phase epitaxial growth process.
また、本発明装置では、閉管チッピング方式の液相エピ
タキシャル成長装置において、基板ホルダの底部に小孔
を設けるか、又は基板表面へのエピタキシャル結晶成長
用メルトの通路をメルトが通過できる最小の大きさに設
定したものである。In addition, in the apparatus of the present invention, in a liquid phase epitaxial growth apparatus using a closed tube tipping method, a small hole is provided at the bottom of the substrate holder, or a hole is formed in the minimum size that allows the melt to pass through the passage for epitaxial crystal growth to the substrate surface. This is the setting.
本発明方法では、基板１１の裏面にも、表面と同じ構成
元素で、かつ、略同じ厚さの第２の化合物半導体層１３
が成長されるので、室温まで冷却した際に基板１１の表
面に成長された第１の化合物半導体層１２と基板１１と
の間の熱膨張率の差に基づく反り応力を、第１図（Ｂ）
に示す如く基板１１と第２の化合物半導体層１３との間
の熱膨張率の差に基づく反り応力で打ち消すことができ
る。In the method of the present invention, a second compound semiconductor layer 13 is also formed on the back surface of the substrate 11, which has the same constituent elements as the front surface and has approximately the same thickness.
is grown, the warpage stress based on the difference in thermal expansion coefficient between the first compound semiconductor layer 12 grown on the surface of the substrate 11 and the substrate 11 when the substrate 11 is cooled to room temperature is calculated as shown in FIG. )
As shown in FIG. 2, this can be canceled out by the warping stress based on the difference in thermal expansion coefficient between the substrate 11 and the second compound semiconductor layer 13.
また、本発明装置では基板ホルダ底部に小孔を設けたり
、あるいは前記通路の大きさを設定しているため、基板
１１の底部に位置する基板裏面に対する気相成長を促進
できる。Furthermore, in the apparatus of the present invention, a small hole is provided at the bottom of the substrate holder or the size of the passage is set, so that vapor phase growth on the back surface of the substrate located at the bottom of the substrate 11 can be promoted.
第２図は本発明方法の第１実施例の説明図を示す。本実
施例は前記した第８図に示すＬＰＥ装置と基本的には同
様の構成によって液相エピタキシャル成長を行なうが、
本実施例では等温気相成長も行なう点で従来方法と大き
く異なる。FIG. 2 shows an explanatory diagram of a first embodiment of the method of the present invention. In this example, liquid phase epitaxial growth is performed using basically the same configuration as the LPE apparatus shown in FIG. 8 described above.
This embodiment differs greatly from the conventional method in that isothermal vapor phase growth is also performed.
まず、第２図（Ａ）に示す状態で等温気相成長を行なう
。同図中、アンプル２０内では基板ホルダ２１に保持さ
れたエピタキシャル成長用基板２２（前記基板１１に相
当）が、エピタキシャル結晶成長用メルト２３と非接触
の状態とされており、基板２２の裏面が基板ホルダ２１
を介してメルト２３に対向するように位置している。こ
こで基板２２はバルクＣｄＴｅ、あるいは異種基板（サ
ファイア、Ｓｉ、ＧａＡｓ等）の両面にＣｄＴｅを成長
したＣｄＴｅ／異種基板／ Ｃｄ Ｔ ｅである。First, isothermal vapor phase growth is performed in the state shown in FIG. 2(A). In the figure, in the ampoule 20, an epitaxial growth substrate 22 (corresponding to the substrate 11) held by a substrate holder 21 is in a non-contact state with an epitaxial crystal growth melt 23, and the back surface of the substrate 22 is in contact with the epitaxial crystal growth melt 23. Holder 21
It is located so as to face the melt 23 via. Here, the substrate 22 is bulk CdTe or CdTe/different substrate/CdTe in which CdTe is grown on both sides of a different substrate (sapphire, Si, GaAs, etc.).
また、エピタキシャル結晶成長用メルト２３は所謂Ｔｅ
リッチメルトと称されるもので（Ｈｇ＋−ｚ Ｃｄｚ
）ｌ−ｙ Ｔｅｙ （ｙは０．５以上）で表わされる
、Ｈｇ原子とＣｄ原子の和の原子数よりもＴｅ原子の個
数が多い融液である。Further, the epitaxial crystal growth melt 23 is made of so-called Te.
It is called rich melt (Hg+-z Cdz
)ly Tey (y is 0.5 or more), which is a melt in which the number of Te atoms is greater than the total number of Hg atoms and Cd atoms.
等温気相成長は例えば本出願人が特願平ｌ−１８７９９
０号にて提案した成長法で、第２図（Ａ）に示す状態で
、アンプル２０内の温度を昇温し、エピタキシャル結晶
成長用メルト２３の液相化温度ＴＬ以上の所定の温度で
長時間基板２２を保持することで行なわれる。上記の液
相化温度ＴＬ以上の所定温度では、メルト２３．雰囲気
ガス及び基板２２で構成される三相が平衡状態となり、
基板２２の表面と裏面の各ＣｄＴｅ層には、メルト２３
より析出する固相のＨｇ、−ｘ Ｃｄｚ Ｔ６の結晶の
Ｘ値と等しい値に、Ｘ値が到達するまでＨｇとＴｅが輸
送されることにより、Ｈｇ ＋−ｘ Ｃｄ ｘＴｅ結晶
層が形成されると共に、ＣｄＴｅ層内部ではこのＨｇ
＋−ｘ Ｃｄ ｘ Ｔ ｅ結晶層と相互拡散を起こす。Isothermal vapor phase growth is described, for example, in Japanese Patent Application No. 1-18799 by the present applicant.
In the growth method proposed in No. 0, the temperature inside the ampoule 20 is raised in the state shown in FIG. This is done by holding the time board 22. At a predetermined temperature above the liquidus temperature TL, the melt 23. The three phases composed of the atmospheric gas and the substrate 22 are in equilibrium,
A melt 23 is applied to each CdTe layer on the front and back surfaces of the substrate 22.
A Hg +-x Cd xTe crystal layer is formed by transporting Hg and Te until the X value reaches a value equal to the X value of the solid phase Hg, -x Cdz T6 crystal, which precipitates more. At the same time, this Hg inside the CdTe layer
+-x Cd x Te Interdiffusion occurs with the crystal layer.
その結果、基板２２の表面と裏面の各ＣｄＴｅ層は、Ｈ
ｇ＋−ｘ Ｃｄｘ Ｔｅ結晶層に変換される。As a result, each CdTe layer on the front and back surfaces of the substrate 22 has H
g+-x Cdx is converted into a Te crystal layer.
このときのＨｇ ＋−エＣｄｘＴｅ結晶層の厚みは、予
め形成したＣｄＴｅ層の厚さ及びＨｇ ＋−ｘ Ｃｄｘ
ＴｅのＸ値によって定まる値になり、ここでは後述のＬ
ＰＥ成長によって基板２２の表面に形成されるＨｇ＋−
ｘ Ｃｄｘ Ｔｅ層の厚さに等しい値に設定される。な
お、基板２２は基板ホルダ２１に保持されているが、基
板ホルダ２１と基板２２との隙間を介して、上記のＨｇ
１−ウＣｄｘ Ｔｅ結晶層の気相成長が基板２２の裏面
に対しても行なわれる。The thickness of the Hg +-x CdxTe crystal layer at this time is the thickness of the previously formed CdTe layer and the Hg +-x Cdx
The value is determined by the X value of Te, and here L
Hg+- formed on the surface of the substrate 22 by PE growth
x Cdx is set equal to the thickness of the Te layer. Note that although the substrate 22 is held by the substrate holder 21, the above-mentioned Hg
1-U Vapor phase growth of a Cdx Te crystal layer is also performed on the back surface of the substrate 22.
次にアンプル２０内の温度を降温しながら、前記液相化
温度Ｔ１以上の所定の成長開始温度でアンプル２０を１
８０°回転して第２図（Ｂ）に示す如く、基板２２の表
面を飽和状態のメルト２３に接触させる。これにより、
前記等温気相成長時に基板２２の表面に形成されたＨｇ
＋−ｘ Ｃｄｘ Ｔｅ結晶層はメルトバックにより除去
され、その後基板２２の表面にＬＰＥ成長が始まり、Ｈ
ｇ ＋イＣｄ ｘ Ｔ ｅ層が成長される。Next, while lowering the temperature inside the ampoule 20, the ampoule 20 is heated to a predetermined growth start temperature equal to or higher than the liquid phase temperature T1.
The substrate 22 is rotated by 80 degrees to bring the surface of the substrate 22 into contact with the saturated melt 23 as shown in FIG. 2(B). This results in
Hg formed on the surface of the substrate 22 during the isothermal vapor phase growth
+-x Cdx The Te crystal layer is removed by meltback, and then LPE growth begins on the surface of the substrate 22, and H
A g+I Cd x T e layer is grown.
次に所定時間後、アンプル２０を再び１８０°回転して
ＬＰＥ成長を終了する。これにより、第１図（Ａ）に示
したように、基板２２（１１）の表面には第１の化合物
半導体層１２としてＬＰＥ成長されたＨｇ＋−ｘ Ｃｄ
ｘ Ｔｅ層が形成され、また基板２２（１１）の裏面に
は第２の化合物半導体層１３として等温気相成長された
Ｈ ｇ ＋−ｘ Ｃｄ、Ｔｅ結晶層が形成された半導体
結晶が得られる。Next, after a predetermined time, the ampoule 20 is rotated 180 degrees again to complete the LPE growth. As a result, as shown in FIG. 1(A), the surface of the substrate 22 (11) has Hg+-x Cd grown by LPE as the first compound semiconductor layer 12.
A semiconductor crystal is obtained in which a H g +-x Te layer is formed, and a H g +-x Cd, Te crystal layer is formed on the back surface of the substrate 22 (11) by isothermal vapor phase growth as the second compound semiconductor layer 13. .
その後、アンプル２０内の温度を室温まで冷却するが、
その際、基板２２の表面と裏面には同じ組成Ｈｇ＋−ｘ
Ｃｄｘ Ｔｅの結晶層が略同じ厚さて形成されている
から、基板と結晶層間の熱膨張率の差に基づく反り応力
が基板の表面と裏面で釣り合い、反りの無い表面が平坦
な半導体結晶が製造される。After that, the temperature inside the ampoule 20 is cooled to room temperature,
At that time, the front and back surfaces of the substrate 22 have the same composition Hg+-x.
Since the Cdx Te crystal layers are formed with approximately the same thickness, the warping stress due to the difference in thermal expansion coefficient between the substrate and the crystal layer is balanced between the front and back surfaces of the substrate, producing a semiconductor crystal with a flat surface without warping. be done.
次に本発明方法の第２実施例について説明する。Next, a second embodiment of the method of the present invention will be described.
本実施例では第３図に示す公知のＬＰＥ装置が使用され
る。同図中、３０はアンプルで、その内部には基板ホル
ダ３１により保持された基板３２かエピタキシャル結晶
成長用メルト２３の上方に配置されている。In this embodiment, a known LPE device shown in FIG. 3 is used. In the figure, numeral 30 is an ampoule in which a substrate 32 held by a substrate holder 31 is placed above a melt 23 for epitaxial crystal growth.
また、基板ホルダ３１は第３図中、アンプル３０の長手
方向に沿う縦断面図である第４図に示すように、アンプ
ル３０内に基板ホルダ３１の両側に配置された固定治具
３４の凹部３５に嵌合固定されている。アンプル３０は
その軸線を中心として回転自在に構成されており、また
固定治具３４はアンプル３０と一体的に回転するように
なされているから、基板３２は基板ホルダ３１と共にア
ンプル３０と一体的に回転する。Further, as shown in FIG. 4, which is a longitudinal cross-sectional view of the ampoule 30 in FIG. 35 is fitted and fixed. Since the ampoule 30 is configured to be rotatable about its axis, and the fixing jig 34 is configured to rotate integrally with the ampoule 30, the substrate 32 and the substrate holder 31 are integrally rotated with the ampoule 30. Rotate.
上記の基板３２はバルクＣｄＴｅ、あるいは前記したＣ
ｄＴｅ／異種基板／ Ｃｄ Ｔ ｅであり、また上記の
エピタキシャル結晶成長用メルト３３は例えば前記した
Ｔｅリッチメルトである。The above substrate 32 is made of bulk CdTe or the above-mentioned CdTe.
dTe/different substrate/CdTe, and the above-mentioned epitaxial crystal growth melt 33 is, for example, the above-mentioned Te-rich melt.
次に本実施例の動作について第５図と共に説明する。同
図中、第３図及び第４図と同一構成部分には同一符号を
付し、その説明を省略する。また、第５図には動作説明
に必要最小限なもののみ図示しである。まず、Ｈｇ、Ｃ
ｄ及びＴｅを所定の比率で混合後溶融して所定の形に成
形した固形の原料結晶をアンプル３０内の所定位置に置
き、アンプル３０内を昇温し、所定の温度て短時間溶融
し、第５図（Ａ）に示すようにエピタキシャル結晶成長
用メルト３３を得る。Next, the operation of this embodiment will be explained with reference to FIG. In the figure, the same components as in FIGS. 3 and 4 are denoted by the same reference numerals, and their explanations will be omitted. Further, FIG. 5 shows only the minimum necessary components for explaining the operation. First, Hg, C
d and Te in a predetermined ratio, and then melted and formed into a predetermined shape. A solid raw material crystal is placed in a predetermined position in an ampoule 30, the temperature inside the ampoule 30 is raised, and the mixture is melted at a predetermined temperature for a short period of time. A melt 33 for epitaxial crystal growth is obtained as shown in FIG. 5(A).
次に、アンプル３０内を降温しでいき、成長開始温度で
アンプル３０を１８０°回転し、第５図（Ｂ）に示す如
く基板３２を上記メルト３３中に浸し、基板３２の両面
にＨｇ ｌ−ｘ Ｃｄ ｘ Ｔ ｅのＬＰＥ成長を開始
する。この状態を所定時間継続した後、アンプル３０を
再び１８０°回転して第５図（Ａ）の状態にすると、第
１図（Ａ）に示したように、基板３２（１１）の表面と
裏面の夫々に、第１及び第２の化合物半導体層１２及び
Ｉ３として、同じ厚さのＨｇ＋−ｘ Ｃｄｘ Ｔｅ層が
ＬＰＥ成長された半導体結晶が得られる。その後、第５
図（Ａ）の状態でアンプル３０内の温度を室温にまで冷
却する。この冷却を行なった際、本実施例によれば、第
１実施例と同様の理由で反りのない、表面が平坦な半導
体結晶が得られる。また、基板の両面にＨｇ＋−ｘ Ｃ
ｄｘ Ｔｅ結晶層をＬＰＥ成長時に同時に形成するため
、工数がかからず、汚染もない。Next, the temperature inside the ampoule 30 is lowered, the ampoule 30 is rotated 180 degrees at the growth starting temperature, the substrate 32 is immersed in the melt 33 as shown in FIG. 5(B), and Hg l is applied to both sides of the substrate 32. -x Begin LPE growth of Cd x Te. After continuing this state for a predetermined time, the ampoule 30 is rotated 180 degrees again to the state shown in FIG. 5(A), and as shown in FIG. A semiconductor crystal is obtained in which Hg+-x Cdx Te layers having the same thickness are grown by LPE as the first and second compound semiconductor layers 12 and I3, respectively. Then the fifth
In the state shown in Figure (A), the temperature inside the ampoule 30 is cooled to room temperature. When this cooling is performed, according to this embodiment, a semiconductor crystal with a flat surface without warpage can be obtained for the same reason as in the first embodiment. Also, Hg+-x C on both sides of the board.
Since the dx Te crystal layer is formed at the same time as the LPE growth, there is no need for man-hours and there is no contamination.
次に本発明装置の各実施例について説明する。Next, each embodiment of the device of the present invention will be described.
第６図は本発明製造装置の要部の一実施例の斜視図を示
す。同図は基板ホルダ４０の斜視図を示している。基板
ホルダ４０は矩形の箱状のもので、基板を収納する凹部
４１と基板を載置する底部４２とを有し、底部４２には
多数の小孔４３が穿設されている。FIG. 6 shows a perspective view of an embodiment of the essential parts of the manufacturing apparatus of the present invention. This figure shows a perspective view of the substrate holder 40. The substrate holder 40 is shaped like a rectangular box and has a recess 41 for storing the substrate and a bottom 42 for placing the substrate, and the bottom 42 has a large number of small holes 43 bored therein.
この基板ホルダ４０を前記基板ホルダ２１として用いた
場合は、等温気相成長時に基板２２の裏面に対して小孔
４３を通しても気相成長か行なわれるから、小孔４３を
有さない基板ホルダ使用時に比し、基板２２裏面の気相
成長を促進することができる。When this substrate holder 40 is used as the substrate holder 21, vapor phase growth is performed even if the small hole 43 is passed through the back surface of the substrate 22 during isothermal vapor phase growth, so a substrate holder without the small hole 43 is used. The vapor phase growth on the back surface of the substrate 22 can be promoted more than usual.
次に本発明装置の他の実施例について第７図と共に説明
する。同図中、第２図及び第６図と同一構成部分には同
一符号を付し、その説明を省略する。第７図において、
アンプル２０の内壁に一端が固定され、他端が基板ホル
ダ４０の外周側面に近接離間対向するように部材５０が
配置されている。従って、この部材５０と基板ホルダ４
０の外周側面との間に通路５１が形成され、その通路５
真の大きさはメルト２３が通過できる最小の大きさ（例
えば数百μｍ）に設定されている。Next, another embodiment of the device of the present invention will be described with reference to FIG. In the figure, the same components as in FIGS. 2 and 6 are denoted by the same reference numerals, and their explanations will be omitted. In Figure 7,
A member 50 is arranged such that one end is fixed to the inner wall of the ampoule 20 and the other end faces the outer circumferential side surface of the substrate holder 40 in close proximity to and away from it. Therefore, this member 50 and the substrate holder 4
A passage 51 is formed between the outer peripheral side surface of
The true size is set to the minimum size (for example, several hundred μm) through which the melt 23 can pass.
これにより、基板２２に対する気相成長は、小孔４３を
通して、基板裏面側において促進され、他方、基板表面
への通り路かできる限り細くされているため、基板表面
では抑制される。この結果、より短時間で所定厚みのＨ
ｇ ＋−ｘ ＣｄアＴｅ結晶層を基板２２の裏面に成長
させることができる。As a result, vapor phase growth on the substrate 22 is promoted on the back side of the substrate through the small holes 43, while being suppressed on the substrate surface because the path to the substrate surface is made as narrow as possible. As a result, H
A g + -x Cd-Te crystal layer can be grown on the backside of the substrate 22 .
上述の如く、本発明製造方法によれば、基板表面の第１
の化合物半導体層と基板との間の熱膨張率の差に基づく
反り応力を、基板裏面に形成した第２の化合物半導体層
と基板との間の熱膨張率の差に基づく反り応力で打ち消
すようにしたため、成長終了後の冷却過程において基板
が反ることなく、表面が平坦な半導体結晶を製造するこ
とかでき、またＬＰＥ成長時に上記の第１及び第２の化
合物半導体層を同時に形成しているため、工数もかから
ず汚染の心配もない。また、本発明製造装置によれば、
基板ホルダ底部に小孔を設けたり、基板表面へのメルト
の通路を狭くして基板裏面に対する気相成長を促進して
いるため、基板裏面への化合物半導体層の形成をより短
時間で行なうことができる等の特長を有するものである
。As described above, according to the manufacturing method of the present invention, the first
The warping stress due to the difference in thermal expansion coefficient between the second compound semiconductor layer and the substrate is canceled out by the warping stress due to the difference in thermal expansion coefficient between the second compound semiconductor layer formed on the back surface of the substrate and the substrate. As a result, a semiconductor crystal with a flat surface can be manufactured without causing the substrate to warp during the cooling process after the growth is completed, and the above-mentioned first and second compound semiconductor layers can be formed simultaneously during LPE growth. Because the process requires less man-hours and there is no need to worry about contamination. Moreover, according to the manufacturing apparatus of the present invention,
A small hole is provided at the bottom of the substrate holder and the path for the melt to the substrate surface is narrowed to promote vapor phase growth on the back surface of the substrate, allowing the formation of a compound semiconductor layer on the back surface of the substrate in a shorter time. It has features such as the ability to
第１図は本発明の原理説明図、
第２図は本発明方法の第１実施例の説明図、第３図は本
発明に適用し得るＬＰＥ装置の一例の構成図、
第４図は第３図の縦断面図、
第５図は本発明方法の第２実施例の説明図、第６図は本
発明装置の要部の一実施例の斜視図、第７図は本発明装
置の要部の他の実施例の構成図、
第８図は従来装置の一例の構成図、
第９図は第８図の動作説明図、
第１Ｏ図は従来方法の課題説明図である。
図において、
＋＋、２２．３２はエピタキシャル成長用基板、１２は
第１の化合物半導体結晶層、
１３は第２の化合物半導体結晶層、
２３．３３はエピタキシャル結晶成長用メルトを示す。
本発明の原理説明図
第１図
本発明方法の第１実施例の説明図
第２図
３３メルト
本発明１こ適用し得るＬＰＥ装置の一例の構成図筒
図
第３図の縦断面図
第
図
本発明方法の第２実施例の説明図
第５図
本発明装置の要部の
第６
実施例の斜視図
図
本発明装置の要部の他の実施例の構成図第７図
従来装置の一例の構成図
第８図
第８図の動作説明図
第９図
従来方法の課題説明図
第１０図
ｄＴｅ基板FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of a first embodiment of the method of the present invention, FIG. 3 is a configuration diagram of an example of an LPE device that can be applied to the present invention, and FIG. 3 is a longitudinal cross-sectional view, FIG. 5 is an explanatory diagram of the second embodiment of the method of the present invention, FIG. 6 is a perspective view of an embodiment of the main part of the device of the present invention, and FIG. 7 is a main part of the device of the present invention. FIG. 8 is a block diagram of an example of a conventional device; FIG. 9 is an explanatory diagram of the operation of FIG. 8; and FIG. 1O is a diagram explaining problems with the conventional method. In the figure, ++, 22.32 is a substrate for epitaxial growth, 12 is a first compound semiconductor crystal layer, 13 is a second compound semiconductor crystal layer, and 23.33 is a melt for epitaxial crystal growth. Fig. 1 is an explanatory diagram of the principle of the present invention. Fig. 2 is an explanatory diagram of the first embodiment of the method of the present invention. An explanatory diagram of the second embodiment of the method of the present invention. Figure 5. A perspective view of the sixth embodiment of the essential parts of the apparatus of the present invention. A configuration diagram of another embodiment of the essential parts of the apparatus of the present invention. Figure 7. An example of the conventional apparatus. Fig. 8 Fig. 8 is an explanatory diagram of its operation Fig. 9 is an explanatory diagram of the problems of the conventional method Fig. 10 is a dTe substrate
Claims (5)
法にて第１の化合物半導体結晶層（１２）を形成する半
導体結晶の製造方法において、前記第１の化合物半導体
結晶層（１２）と同一の構成元素で、かつ、略同じ厚さ
の第２の化合物半導体結晶層（１３）を、液相エピタキ
シャル成長工程時に前記基板（１１）の裏面に形成する
ことを特徴とする半導体結晶の製造方法。(1) A method for manufacturing a semiconductor crystal in which a first compound semiconductor crystal layer (12) is formed on the surface of a substrate (11) by a liquid phase epitaxial growth method, which is the same as the first compound semiconductor crystal layer (12). A method for manufacturing a semiconductor crystal, characterized in that a second compound semiconductor crystal layer (13) of constituent elements and having substantially the same thickness is formed on the back surface of the substrate (11) during a liquid phase epitaxial growth step.
前記第１の化合物半導体結晶層（１２）の構成元素を含
む結晶層からなり、かつ、前記液相エピタキシャル成長
前に、等温気相成長により前記基板（１１）の両面に夫
々前記第２の化合物半導体結晶層（１３）を成長した後
、前記液相エピタキシャル成長法を適用して該基板（１
１）の表面に形成された該第２の化合物半導体結晶層を
メルトバックで除去すると共に、前記第１の化合物半導
体結晶層（１２）を形成することを特徴とする請求項１
記載の半導体結晶の製造方法。(2) The front and back surfaces of the substrate (11) are each made of a crystal layer containing at least a constituent element of the first compound semiconductor crystal layer (12), and are formed by isothermal vapor phase epitaxy before the liquid phase epitaxial growth. After growing the second compound semiconductor crystal layer (13) on both sides of the substrate (11), the liquid phase epitaxial growth method is applied to grow the second compound semiconductor crystal layer (13) on both sides of the substrate (11).
1) The first compound semiconductor crystal layer (12) is formed at the same time as removing the second compound semiconductor crystal layer formed on the surface of the second compound semiconductor crystal layer (12) by melt-back.
A method for manufacturing the semiconductor crystal described above.
前記第１の化合物半導体結晶層（１２）の構成元素を含
む結晶層からなり、該基板の両面に夫々液相エピタキシ
ャル成長を行なって前記第１及び第２の化合物半導体結
晶層（１２、１３）を夫々形成することを特徴とする請
求項１記載の半導体結晶の製造方法。(3) The front and back surfaces of the substrate (11) are each made of a crystal layer containing at least the constituent elements of the first compound semiconductor crystal layer (12), and liquid phase epitaxial growth is performed on both surfaces of the substrate to form the first compound semiconductor crystal layer (12). 2. The method of manufacturing a semiconductor crystal according to claim 1, wherein the first and second compound semiconductor crystal layers (12, 13) are formed respectively.
）の表面をエピタキシャル結晶成長用メルト（２３）に
接触させて該基板（１１）表面に前記第１の化合物半導
体結晶層（１２）を成長させる閉管チッピング方式の液
相エピタキシャル成長装置において、 前記基板ホルダ（４０）の底部に小孔（４３）を設けた
ことを特徴とする請求項２記載の半導体結晶を製造する
半導体結晶製造装置。(4) The substrate (11) held by the substrate holder (40)
) in a liquid phase epitaxial growth apparatus using a closed tube tipping method in which the first compound semiconductor crystal layer (12) is grown on the surface of the substrate (11) by bringing the surface of the substrate holder into contact with an epitaxial crystal growth melt (23), 3. The semiconductor crystal manufacturing apparatus for manufacturing a semiconductor crystal according to claim 2, wherein a small hole (43) is provided at the bottom of the semiconductor crystal.
）の表面をエピタキシャル結晶成長用メルト（２３）に
接触させて該基板（１１）表面に前記第１の化合物半導
体結晶層（１２）を成長させる閉管チッピング方式の液
相エピタキシャル成長装置において、 前記基板（１１）表面への前記メルト（２３）の通路（
５１）を該メルト（２３）が通過できる最小の大きさに
設定したことを特徴とする請求項２記載の半導体結晶を
製造する半導体結晶製造装置。(5) The substrate (11) held by the substrate holder (40)
In a liquid phase epitaxial growth apparatus using a closed tube tipping method in which the first compound semiconductor crystal layer (12) is grown on the surface of the substrate (11) by bringing the surface of the substrate () into contact with an epitaxial crystal growth melt (23), 11) Passage of said melt (23) to the surface (
3. The semiconductor crystal manufacturing apparatus for manufacturing a semiconductor crystal according to claim 2, wherein the diameter of the semiconductor crystal 51) is set to a minimum size through which the melt (23) can pass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24935690A JPH04127544A (en) | 1990-09-19 | 1990-09-19 | Manufacture of semiconductor crystal and semiconductor manufacturing device therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24935690A JPH04127544A (en) | 1990-09-19 | 1990-09-19 | Manufacture of semiconductor crystal and semiconductor manufacturing device therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04127544A true JPH04127544A (en) | 1992-04-28 |
Family
ID=17191811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24935690A Pending JPH04127544A (en) | 1990-09-19 | 1990-09-19 | Manufacture of semiconductor crystal and semiconductor manufacturing device therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04127544A (en) |
-
1990
- 1990-09-19 JP JP24935690A patent/JPH04127544A/en active Pending
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