JPH04119962U - Terminal pin mounting structure on circuit board - Google Patents
Terminal pin mounting structure on circuit boardInfo
- Publication number
- JPH04119962U JPH04119962U JP2356891U JP2356891U JPH04119962U JP H04119962 U JPH04119962 U JP H04119962U JP 2356891 U JP2356891 U JP 2356891U JP 2356891 U JP2356891 U JP 2356891U JP H04119962 U JPH04119962 U JP H04119962U
- Authority
- JP
- Japan
- Prior art keywords
- terminal pin
- circuit board
- pattern
- terminal
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 7
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 238000005476 soldering Methods 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Multi-Conductor Connections (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
(57)【要約】
【目的】回路基板上のパターンに平板状の端子ピンを半
田付けする際に容融半田が端子ピンの下面に大きく回り
込むのを抑制して、必要に応じて端子ピンの取外しを容
易に行えるようにする。
【構成】回路基板１の表面に形成した端子ピン取り付け
用の導体パターン２に、端子ピン３重合面より小面積の
中抜き部５を形成し、この中抜き部５上に平板上の端子
ピン３を重合して前記導体パターン２に半田付けするよ
うにしている。
(57) [Summary] [Purpose] When soldering a flat terminal pin to a pattern on a circuit board, it is possible to suppress the molten solder from going around the bottom surface of the terminal pin, and to To allow easy removal. [Structure] A hollow part 5 with a smaller area than the overlapping surface of the terminal pins 3 is formed in the conductor pattern 2 for attaching the terminal pin formed on the surface of the circuit board 1, and the terminal pin on the flat plate is formed on the hollow part 5. 3 are polymerized and soldered to the conductive pattern 2.
Description
【０００１】0001
本考案は、回路基板の表面に形成した導体パターンに端子ピンを半田付け固定 する回路基板への取付構造に関する。 In this invention, terminal pins are fixed by soldering to the conductor pattern formed on the surface of the circuit board. The present invention relates to a mounting structure for mounting on a circuit board.
【０００２】0002
従来上記端子ピン取付構造としては、図４に示すように、回路基板１の表面に プリント形成した銅箱のパターン２に平板状の端子ピン３を重合して半田付けし ていた。 Conventionally, as shown in FIG. 4, the above-mentioned terminal pin mounting structure has been Overlap and solder flat terminal pins 3 to the printed copper box pattern 2. was.
【０００３】0003
上記従来構造によると、半田付け時に溶融した半田が端子ピン３の下に大きく 回り込み、端子ピン３の周辺のみならずその下面までもがパターン２に結合され ることがあり、後に端子ピン３を取外す必要が生じた場合に、端子ピン３下面に 回り込んだ半田が溶融しにくく、端子ピン３の取外しが困難になるものであり、 無理に取外すとパターンを損傷しかねないものであった。 According to the above conventional structure, the melted solder during soldering is large under the terminal pin 3. It wraps around and connects not only the periphery of terminal pin 3 but also its lower surface to pattern 2. If it becomes necessary to remove terminal pin 3 later, the bottom surface of terminal pin 3 may be The solder that has wrapped around it is difficult to melt, making it difficult to remove the terminal pin 3. Forcibly removing it could damage the pattern.
【０００４】 本考案は、パターンに簡単な形状改良を加えるだけで、端子ピンの取外しを容 易に行えるようにすることを目的とする。0004 This invention allows the removal of terminal pins by simply modifying the pattern. The purpose is to make it easy to do.
【０００５】[0005]
上記目的を達成するため、本考案においては、回路基板の表面に形成した端子 ピン取り付け用の導体パターンに、端子ピン重合面より小面積の中抜き部を形成 し、この中抜き部上に平板上の端子ピンを重合して前記導体パターンに半田付け するように構成している。 In order to achieve the above purpose, the present invention uses terminals formed on the surface of the circuit board. A hollow part with a smaller area than the terminal pin overlapping surface is formed in the conductor pattern for pin attachment. Then, overlap the terminal pin on the flat plate over this hollow part and solder it to the conductor pattern. It is configured to do so.
【０００６】[0006]
本考案によると、半田付け時に溶融した半田が端子ピンの下面に回り込もうと してもパターン中抜き部により半田の回り込みが不可能となる。 According to this invention, when soldering, molten solder tends to get around to the bottom surface of the terminal pin. Even if the pattern is hollowed out, it is impossible for solder to wrap around the pattern.
【０００７】[0007]
図１ないし図３に本考案の取付構造の一実施例が示されている。図１に示すよ うに、回路基板１の表面端部にプリント形成した銅箱のパターン２が形成され、 ここに平板状に形成された端子ピン３が重合されて、図２に示すようにその周辺 が半田４で結合される。 An embodiment of the mounting structure of the present invention is shown in FIGS. 1 to 3. It is shown in Figure 1. A printed copper box pattern 2 is formed on the edge of the surface of the circuit board 1. The terminal pins 3 formed in a flat plate shape are overlapped here, and the surrounding area is formed as shown in FIG. are connected with solder 4.
【０００８】 前記パターン２には、端子ピン３の幅よりも小幅の中抜き部５が形成されてお り、パータン２が抜かれた中抜き部５上に端子ピン３が重合されて半田付けされ る。[0008] The pattern 2 is formed with a hollow portion 5 having a width smaller than the width of the terminal pin 3. Then, the terminal pin 3 is overlaid and soldered onto the hollow part 5 from which the pattern 2 has been removed. Ru.
【０００９】 この構成によると、図３に示すように、中抜き部５までへの半田の回り込みが なく、端子ピン３はその周辺において少しの回り込みを許した状態でパターン２ に結合される。[0009] According to this configuration, as shown in FIG. 3, the solder does not wrap around to the hollow portion 5. Terminal pin 3 is connected to pattern 2 with a slight wraparound around it. is combined with
【００１０】 前記中抜き部５の形状及び個数は上記実施例に限られるものではなく、例えば 丸孔状の中抜き部５を複数個並べてもよく、要は端子ピン３のパターン２上への 重合面より小面積の中抜き部５を形成すればよい。0010 The shape and number of the hollow portions 5 are not limited to the above embodiments, and for example, A plurality of hollow holes 5 in the shape of round holes may be arranged in a row, and the point is that the hollow portions 5 in the shape of round holes are placed on the pattern 2 of the terminal pins 3. It is sufficient to form a hollow portion 5 having a smaller area than the overlapping surface.
【００１１】 尚、図３中の符号６は端子ピン３を支持した端子台であり、この端子台６を介 して外部装置と端子ピン３とを配線接続可能となっている。[0011] The reference numeral 6 in FIG. 3 is a terminal block that supports the terminal pin 3. This allows wiring connection between an external device and the terminal pin 3.
【００１２】0012
以上説明したように、本考案によれば端子ピン下面への半田の回り込みを抑制 でき、端子ピンの取外しの必要が生じた場合に、パターンに損傷を与えることな く端子ピンの取り外しを容易に行えるようになった。 As explained above, according to the present invention, solder wraps around the bottom surface of the terminal pin is suppressed. without damaging the pattern if it becomes necessary to remove the terminal pin. The terminal pins can now be easily removed.
【図１】本考案の一実施例を示す要部の分解斜視図であ
る。FIG. 1 is an exploded perspective view of essential parts showing an embodiment of the present invention.
【図２】半田付け状態を示す要部の斜視図である。FIG. 2 is a perspective view of main parts showing a soldered state.
【図３】要部の拡大断面図である。FIG. 3 is an enlarged sectional view of main parts.
【図４】従来例の要部を示す分解斜視図である。FIG. 4 is an exploded perspective view showing main parts of a conventional example.
１ 回路基板 ２ 導体パターン ３ 端子ピン 1 circuit board 2 Conductor pattern 3 Terminal pin
Claims (1)
取り付け用の導体パターン（２）に、端子ピン（３）重
合面より小面積の中抜き部（５）を形成し、この中抜き
部（５）上に平板上の端子ピン（３）を重合して前記導
体パターン（２）に半田付けすることを特徴とする回路
基板への端子ピン取付構造。Claim 1: A hollow portion (5) with a smaller area than the terminal pin (3) overlapping surface is formed in a conductor pattern (2) for attaching a terminal pin formed on the surface of a circuit board (1), A structure for attaching a terminal pin to a circuit board, characterized in that a terminal pin (3) on a flat plate is superimposed on the cutout (5) and soldered to the conductor pattern (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991023568U JP2569101Y2 (en) | 1991-04-10 | 1991-04-10 | Terminal pin mounting structure on circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1991023568U JP2569101Y2 (en) | 1991-04-10 | 1991-04-10 | Terminal pin mounting structure on circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04119962U true JPH04119962U (en) | 1992-10-27 |
| JP2569101Y2 JP2569101Y2 (en) | 1998-04-22 |
Family
ID=31908749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1991023568U Expired - Lifetime JP2569101Y2 (en) | 1991-04-10 | 1991-04-10 | Terminal pin mounting structure on circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2569101Y2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124069U (en) * | 1984-01-31 | 1985-08-21 | 日本電気ホームエレクトロニクス株式会社 | Printed board |
| JPS6175160U (en) * | 1984-10-22 | 1986-05-21 | ||
| JPS62126751A (en) * | 1985-11-27 | 1987-06-09 | Nec Corp | Check system of fault information transfer device |
| JPS62145373U (en) * | 1986-03-07 | 1987-09-12 | ||
| JPH01273387A (en) * | 1988-04-25 | 1989-11-01 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit device |
-
1991
- 1991-04-10 JP JP1991023568U patent/JP2569101Y2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60124069U (en) * | 1984-01-31 | 1985-08-21 | 日本電気ホームエレクトロニクス株式会社 | Printed board |
| JPS6175160U (en) * | 1984-10-22 | 1986-05-21 | ||
| JPS62126751A (en) * | 1985-11-27 | 1987-06-09 | Nec Corp | Check system of fault information transfer device |
| JPS62145373U (en) * | 1986-03-07 | 1987-09-12 | ||
| JPH01273387A (en) * | 1988-04-25 | 1989-11-01 | Matsushita Electric Ind Co Ltd | Hybrid integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2569101Y2 (en) | 1998-04-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |