JPH0411757A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0411757A JPH0411757A JP2114789A JP11478990A JPH0411757A JP H0411757 A JPH0411757 A JP H0411757A JP 2114789 A JP2114789 A JP 2114789A JP 11478990 A JP11478990 A JP 11478990A JP H0411757 A JPH0411757 A JP H0411757A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- bonding agent
- integrated circuit
- hybrid integrated
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 239000000843 powder Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 3
- 239000011347 resin Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000007767 bonding agent Substances 0.000 abstract 5
- 229910000679 solder Inorganic materials 0.000 description 14
- 239000010410 layer Substances 0.000 description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229920002050 silicone resin Polymers 0.000 description 7
- 230000008646 thermal stress Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000035882 stress Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、放熱体上に回路素子が取り付けられた厚膜
基板を取り付けた混成集積回路装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hybrid integrated circuit device in which a thick film substrate on which circuit elements are mounted is mounted on a heat sink.
第２図は従来の混成集積回路装置の一例を示す断面図で
あり、この図において、１は出力回路部を構成するＰＷ
Ｔｒ等の電力用半導体素子、２は銅ヒー１−シンク、３
は制御回路部であるＩＣチップ、４は前記電力用半導体
素子１を銅ヒー１−シンク２に固着する半田層、５は表
面をメタライズしたアルミナ絶縁基板、６は前記銅ヒー
トシンク２をアルミナ絶縁基板５に固着する半田層、７
は厚膜基板、８は表面をメツキしたｋｌヒートンツク等
の放熱体、９は前記放熱体８にアルミナ絶縁基板５を固
着する半田層、１０は前記放熱体８に厚膜基板７を固着
するンリコ、樹脂層である。FIG. 2 is a cross-sectional view showing an example of a conventional hybrid integrated circuit device.
Power semiconductor element such as Tr, 2 is copper heat sink 1-sink, 3
4 is a solder layer that fixes the power semiconductor element 1 to the copper heat sink 1-sink 2; 5 is an alumina insulating substrate whose surface is metallized; and 6 is an alumina insulating substrate for fixing the copper heat sink 2 to the copper heat sink 2. a solder layer that adheres to 5, 7
8 is a thick film substrate, 8 is a heat dissipation member such as a heat sink with a plated surface, 9 is a solder layer for fixing the alumina insulating substrate 5 to the heat dissipation member 8, and 10 is a solder layer for fixing the thick film substrate 7 to the heat dissipation member 8. , a resin layer.
次に動作について説明する。Next, the operation will be explained.
電力用半導体素子１を動作させた場合、発生した熱エネ
ルギーは、銅ヒ−１〜ンンク２．アルミナ絶縁基板５か
ら半田層９を通して放熱体８より放散される。When the power semiconductor device 1 is operated, the generated thermal energy is transferred to the copper heaters 1 to 2. The heat is radiated from the heat sink 8 from the alumina insulating substrate 5 through the solder layer 9.
一方、電力用半導体素子１の制御部にあたろ厚膜基板７
は、アルミナ絶縁基板５に比へ発熱が少ないので、放熱
体８との接合に半田を使用する必要がなく、半田を使用
した場合には、アルミナ絶縁基板５よりはるかに大きい
厚膜基板７を放熱体８に半田で接合することになり、両
者で発生する熱応力のために厚膜基板７が割れてしまう
。このへ、レリコノ樹脂は熱応力の緩和が大きいので、
厚膜基板７と放熱体８との接着には上記したようにシリ
コシ樹脂層１０が使用されている。On the other hand, the control section of the power semiconductor device 1 has a thick film substrate 7.
Since it generates less heat than the alumina insulating substrate 5, there is no need to use solder to connect it to the heat sink 8, and if solder is used, the thick film substrate 7, which is much larger than the alumina insulating substrate 5, can be used. Since it will be joined to the heat sink 8 by soldering, the thick film substrate 7 will crack due to the thermal stress generated in both. In addition, since Reikono resin has a large relaxation of thermal stress,
As described above, the silicone resin layer 10 is used to bond the thick film substrate 7 and the heat sink 8 together.
従来の混成集積回路装置は、以上のように構成されてい
るので、アルミナ絶縁基板５を放熱体８へ半田層９で半
田付けした後、厚膜基板７をシリコン樹膨層１０で接着
することが必要で、また、電力用半導体素子１を長時間
高温断通勤作させると半田層９の表面に熱応力によるク
ラックが入り、熱抵抗値が増大するという問題点があっ
た。Since the conventional hybrid integrated circuit device is configured as described above, the alumina insulating substrate 5 is soldered to the heat sink 8 with the solder layer 9, and then the thick film substrate 7 is bonded with the silicon dendritic layer 10. Moreover, when the power semiconductor device 1 is subjected to high-temperature disconnection operation for a long time, there is a problem that cracks occur on the surface of the solder layer 9 due to thermal stress, and the thermal resistance value increases.
この発明は、上記のような問題点を解消するためになさ
れたもので、アルミナ絶縁基板と放熱体間の接着層の劣
化をおさえるとともに、シリコシ樹脂で問題となる熱伝
導性を改善した混成集積回路装置を得ることを目的とす
る。This invention was made to solve the above-mentioned problems, and it suppresses the deterioration of the adhesive layer between the alumina insulating substrate and the heat sink, and also improves the thermal conductivity, which is a problem with silicone resin. The purpose is to obtain a circuit device.
この発明に係る混成集積回路装置は、電力用半導体素子
等の出力回路部とＩＣチップのような制御回路部とが装
着された厚膜基板を応力緩和性と熱伝導性を有する接合
材で放熱体に接着したものである。The hybrid integrated circuit device according to the present invention uses a thick film substrate on which an output circuit section such as a power semiconductor element and a control circuit section such as an IC chip are attached, and uses a bonding material that has stress relaxation properties and thermal conductivity to dissipate heat. It is attached to the body.
この発明においては、シリコシ樹脂に熱応力緩和性と熱
伝導性を有する接合材を用いることから、電力用半導体
素子から発生する熱エネルギーを放熱体−・放散させる
とともに、この放熱体とアルミナ絶縁基板間の熱応力を
緩和させる。In this invention, since a bonding material having thermal stress relaxation properties and thermal conductivity is used for the silicone resin, the thermal energy generated from the power semiconductor element is dissipated to the heat sink, and the heat sink and the alumina insulating substrate are Alleviates thermal stress between
以下、この発明の一実施例を第１図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図において、１１はこの発明による接合材で、シリ
コン樹脂に熱伝導性の良好な金属粉末、例えば銀粉、銅
粉ファイバ等を含有させたもので、この実施例では厚膜
基板７上へ電力用半導体素子１および制御用ｉＣチップ
３等の回路素子が装着されろ。すなわち電力用半導体素
子１は銅ヒート′Ｊ、り２を介して搭載されており、ま
た、制御用ＩＣチップ３は直接装着され、との厚膜基板
７と放熱板８とは前記液き材１１を用いて接着され、こ
の発明の混成集積回路装置が構成されている。In FIG. 1, reference numeral 11 denotes a bonding material according to the present invention, which is made by adding metal powder with good thermal conductivity, such as silver powder or copper powder fiber, to silicone resin. Circuit elements such as the power semiconductor element 1 and the control iC chip 3 are installed. That is, the power semiconductor element 1 is mounted via a copper heat shield 2, the control IC chip 3 is mounted directly, and the thick film substrate 7 and heat sink 8 are mounted on the liquid material. 11 to form a hybrid integrated circuit device of the present invention.
次に動作について説明する。Next, the operation will be explained.
半田を使用した場合の熱伝導性は、
（熱伝導率）×（半田層の厚さ）×（接合面積比率）で
示され、
１４−６Ｗ／ ｃ ｍ”／ｓｅｅ／ ℃となる。Thermal conductivity when using solder is expressed as (thermal conductivity) x (thickness of solder layer) x (joint area ratio), and is 14-6 W/cm''/see/°C.
一方、シリコン樹脂を使用した場合は、同様に計算する
と、０．５Ｗ／ Ｃｍ２／ｓｅｅ／ ℃となり、半田の
３％の熱伝導性しかないことになるが、この発明のよう
に、熱伝導性の良好な金属粉をシリコン樹脂に含有させ
た接合材１１の場合は、１．８Ｗ／ ｃ ｍ２／ ｓｅ
ｅ／ ℃となり、半田の１５％の熱伝導性にまで改善さ
れる。また、これに合オ）せて−次ヒートレンクの体積
を約１．８倍にすれば、十分に現状なみの熱伝導性は確
保可能である。On the other hand, if silicone resin is used, the same calculation results in 0.5W/Cm2/see/℃, which means that the thermal conductivity is only 3% of solder. In the case of bonding material 11 in which silicone resin contains metal powder of good quality, the power consumption is 1.8W/cm2/se
e/°C, and the thermal conductivity is improved to 15% that of solder. In addition, if the volume of the -order heat lens is increased by about 1.8 times in accordance with this, it is possible to sufficiently maintain the current level of thermal conductivity.
なお、上記実施例では、厚膜基板７と放熱体８とをシリ
コシ樹脂に熱伝導性の良好な金属粉を含有させた接合材
１１を用いているが、これは同程度の応力緩和性と熱伝
導性を有する接合材であれば何でもよい。In the above embodiment, the thick film substrate 7 and the heat sink 8 are bonded using the bonding material 11 made of silicone resin containing metal powder with good thermal conductivity. Any bonding material may be used as long as it has thermal conductivity.
思上説明したように、この発明は、出力回路部と制御回
路部とが装着された厚膜基板と放熱体とを、応力緩和性
と熱伝導性を有する接合材で接着したので、高品質な製
品が安価にできるという効果がある。As explained above, in this invention, the thick film substrate on which the output circuit section and the control circuit section are attached and the heat sink are bonded together using a bonding material that has stress relaxation properties and thermal conductivity, so that high quality can be achieved. This has the effect of producing products at low cost.
第１図はこの発明の一実施例による混成集積回路装置を
示す断面図、第２図は従来の混成集積回路装置を示す断
面図である。
図において、１は電力用半導体素子、２は銅ヒｊ−二・
７り、３は制纒用ＩＣチ、ンプ、４，６は半田層、７は
厚膜基板、８は放熱体、１１は接合材を小す、。
なお、各図中の同一符号は同一または相当部分を示す、
。
代理人 大 岩 増 雄 （外２名）第
図
第
図
５、補正の対象
明細書の発明の詳細な説明の欄
６、補正の内容
明細書の第５頁３行の［酊ＴｆｆＣｆｆＩＪく自発）
■２′
平−FIG. 1 is a sectional view showing a hybrid integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional hybrid integrated circuit device. In the figure, 1 is a power semiconductor element, 2 is a copper heater.
7, 3 is an IC chip for sealing, 4 and 6 are solder layers, 7 is a thick film substrate, 8 is a heat sink, and 11 is a bonding material. In addition, the same symbols in each figure indicate the same or corresponding parts.
. Agent Masuo Oiwa (2 others) Figure 5, column 6 of the detailed description of the invention in the specification subject to amendment, page 5, line 3 of the specification of contents of the amendment. ■2' flat-
Claims (1)
力緩和性と熱伝導性を有する接合材で放熱体に接着した
ことを特徴とする混成集積回路装置。1. A hybrid integrated circuit device characterized in that a thick film substrate on which an output circuit section and a control circuit section are attached is bonded to a heat sink using a bonding material having stress relaxation properties and thermal conductivity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2114789A JPH0411757A (en) | 1990-04-28 | 1990-04-28 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2114789A JPH0411757A (en) | 1990-04-28 | 1990-04-28 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0411757A true JPH0411757A (en) | 1992-01-16 |
Family
ID=14646724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2114789A Pending JPH0411757A (en) | 1990-04-28 | 1990-04-28 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0411757A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5552637A (en) * | 1993-06-14 | 1996-09-03 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US7362001B2 (en) | 2002-10-28 | 2008-04-22 | Toyota Jidosha Kabushiki Kaisha | Generator-motor |
| US7411324B2 (en) | 2002-10-28 | 2008-08-12 | Toyota Jidosha Kabushiki Kaisha | Generator-motor |
-
1990
- 1990-04-28 JP JP2114789A patent/JPH0411757A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5552637A (en) * | 1993-06-14 | 1996-09-03 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US7362001B2 (en) | 2002-10-28 | 2008-04-22 | Toyota Jidosha Kabushiki Kaisha | Generator-motor |
| US7411324B2 (en) | 2002-10-28 | 2008-08-12 | Toyota Jidosha Kabushiki Kaisha | Generator-motor |
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