JPH04117074A - Synchronization separator circuit - Google Patents
Synchronization separator circuitInfo
- Publication number
- JPH04117074A JPH04117074A JP23212490A JP23212490A JPH04117074A JP H04117074 A JPH04117074 A JP H04117074A JP 23212490 A JP23212490 A JP 23212490A JP 23212490 A JP23212490 A JP 23212490A JP H04117074 A JPH04117074 A JP H04117074A
- Authority
- JP
- Japan
- Prior art keywords
- comparator
- input
- constant current
- output
- mos transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002131 composite material Substances 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 12
- 230000000295 complement effect Effects 0.000 claims description 3
- 238000000926 separation method Methods 0.000 abstract description 17
- 230000001360 synchronised effect Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 5
- 238000007599 discharging Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は同期分離回路に係り、特にテレビやビデオ等の
分野の複合映像信号から同期信号を取り出す同期分離回
路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization separation circuit, and more particularly to a synchronization separation circuit for extracting a synchronization signal from a composite video signal in fields such as television and video.
第３図に、この種の従来例を示す。第３図において、従
来の同期分離回路は、入力端子５１とコンデンサ５２の
一端を接続し、コンデンサ５２の他端と抵抗５７と抵抗
５８との接続点と、コンパレータ５３の非反転入力（＋
）端子を接続し、コンパレータ５３の反転入力（−）端
子をバイアス電源６１に接続し、コンパレータ５３の出
力を、出力端子５４とＰチャンネルＭＯＳトランジスタ
５６とＮチャンネルＭＯＳトランジスタ５９のゲートに
接続し、ＰチャンネルＭＯＳトランジスタ５６のソース
を電源５５に接続し、ＰチャンネルＭＯＳトランジスタ
５６のドレインと抵抗５７の他端を接続し、Ｎチャンネ
ルトランジスタ５９のソースとグランド６０を接続し、
Ｎチャンネルトランジスタ５９のドレインと抵抗５８の
他端に接続する構成となっていた。FIG. 3 shows a conventional example of this type. In FIG. 3, the conventional synchronous separation circuit connects an input terminal 51 and one end of a capacitor 52, connects the other end of the capacitor 52 to a connection point between resistors 57 and 58, and connects the non-inverting input (+
) terminal, the inverting input (-) terminal of the comparator 53 is connected to the bias power supply 61, the output of the comparator 53 is connected to the output terminal 54 and the gates of the P-channel MOS transistor 56 and the N-channel MOS transistor 59, The source of the P-channel MOS transistor 56 is connected to the power supply 55, the drain of the P-channel MOS transistor 56 is connected to the other end of the resistor 57, the source of the N-channel transistor 59 is connected to the ground 60,
The drain of the N-channel transistor 59 was connected to the other end of the resistor 58.
前述した従来の同期分離回路では、第３図にも示すよう
に、複合映像信号２１の同期期間ｔ１と他の期間ｔ２と
に於て、期間ｔ１にコンデンサ５２を充電する電荷と期
間ｔ２にコンデンサ５２を放電する電荷とが等しいとき
に、正常な同期分離動作をする。即ち、ｔ １ ： ｔ
２＃Ｒ５ア：Ｒ５８に設定する事により、同期分離動
作をしていた。しかし映像信号が白のときと黒のときと
では、期間ｔ２にコンデンサ５２を放電する電荷が異な
る為、同期分離された出力パルス幅が変化するという欠
点を持っていた。In the conventional synchronization separation circuit described above, as shown in FIG. Normal synchronous separation operation occurs when the charges discharging 52 and 52 are equal. That is, t 1 : t
2#R5A: Synchronous separation was performed by setting R58. However, since the charge discharged from the capacitor 52 during the period t2 is different between when the video signal is white and when the video signal is black, there is a drawback that the width of the synchronously separated output pulse changes.
本発明の目的は、前記欠点を解決し、同期分離された出
力パルス幅が変化しないようにした同期分離回路を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous separation circuit which solves the above-mentioned drawbacks and prevents the width of synchronously separated output pulses from changing.
本発明の同期分離回路の構成は、複合映像信号が入力さ
れる入力端子は、コンデンサを介してコンパレータの一
入力に接続され、前記コンパレータの他入力はバイアス
電源に接続され、相補なるＭＯＳトランジスタの直列体
を設け、前記直列体の両端にそれぞれ第１．第２の定電
流源を直列接続し、前記ＭＯＳトランジスタの共通接続
点を前記コンパレータの一入力に接続し、前記ＭＯ８）
ランシスタのゲートを互いに接続して前記コンパレータ
の出力に接続したことを特徴とする。The configuration of the synchronous separation circuit of the present invention is such that an input terminal to which a composite video signal is input is connected to one input of a comparator via a capacitor, the other input of the comparator is connected to a bias power supply, and complementary MOS transistors are connected to each other. A series body is provided, and first . A second constant current source is connected in series, a common connection point of the MOS transistors is connected to one input of the comparator, and the MO8)
The present invention is characterized in that the gates of the Lancistors are connected to each other and connected to the output of the comparator.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の同期分離回路を示す回路図
である。第１図において、本実施例は、入力端子１をコ
ンデンサ２の一端と接続し、コンデンサ２の他端をコン
パレータ３の非反転入力（＋）とＰチャンネルＭＯＳト
ランジスタフ、及びＮチャンネルＭＯＳトランジスタ８
のドレインと接続する。フンパレータ３の反転入力（−
）をバイアス電源４に接続する。コンパレータ３の出力
を出力端子５、及びＰチャンネルトランジスタ７のゲー
トＮチャンネルトランジスタ８のゲートに接続する。Ｐ
チャンネルトランジスタ７のソースは、定電流源６を介
して、ｖｎｉ＋電源１０に接続する。FIG. 1 is a circuit diagram showing a synchronous separation circuit according to an embodiment of the present invention. In FIG. 1, in this embodiment, an input terminal 1 is connected to one end of a capacitor 2, and the other end of the capacitor 2 is connected to the non-inverting input (+) of a comparator 3, a P-channel MOS transistor 8, and an N-channel MOS transistor 8.
Connect to the drain of Inverting input of funparator 3 (-
) to the bias power supply 4. The output of the comparator 3 is connected to the output terminal 5 and the gate of the P-channel transistor 7 and the gate of the N-channel transistor 8 . P
The source of channel transistor 7 is connected to vni+ power supply 10 via constant current source 6.
Ｎチャンネルトランジスタ８のソースは、定電流源９を
介して、グランド１１に接続する。The source of N-channel transistor 8 is connected to ground 11 via constant current source 9 .
本実施例の同期分離回路は、第２図に示すように、複合
映像信号２０の同期期間ｔｌｌと他の期間ｔ１□に於て
、期間ｔ１１にコンデンサ２を充電する電荷と、期間ｔ
１２にコンデンサ２を放電する電荷とが等しいときに、
正常な同期分離動作をする。As shown in FIG. 2, the synchronization separation circuit of this embodiment is configured to charge the capacitor 2 during the period t11 and the period t during the synchronization period tll of the composite video signal 20 and the other period t1□.
When the charge discharging capacitor 2 is equal to 12,
Performs normal synchronization separation operation.
即ち、定電流源６の電流値をｌい定電流源９の電流値を
工、としたとき、ｔｏ ： ｔｕ＝Ｉｅ ： Ｉ。That is, when the current value of the constant current source 6 is l and the current value of the constant current source 9 is , to: tu=Ie: I.
に設定する事により、同期分離動作をする。ここで、従
来回路で問題となった映像信号２０が白のときと黒のと
きとでも、■、は一定の電流値であり、コンデンサ２を
放電する電荷に差異は無く、出力パルス幅変動のない同
期分離出力が得られる。By setting this, synchronous separation operation is performed. Here, even when the video signal 20 is white and black, which was a problem in the conventional circuit, ■ is a constant current value, there is no difference in the charge discharging the capacitor 2, and the output pulse width fluctuation A synchronized separated output is obtained.
以上説明したように、本発明は、コンパレータの反転入
力をバイアス電源に接続し、非反転入力にはコンデンサ
を介して複合映像信号を入力すると同時に、互いに相補
なるＭＯＳトランジスタと第１．第２の定電流源とを直
列接続し、前記ＭＯＳトランジスタのゲートをコンパレ
ータの出力に接続し、ＭＯＳトランジスタの共通接続点
をコンパレータの入力に接続しているから、複合映像信
号が、白、黒に変化しても、出力パルス幅が変化しない
同期分離出力が得られる効果がある。As described above, the present invention connects the inverting input of the comparator to the bias power supply, inputs the composite video signal to the non-inverting input via the capacitor, and simultaneously connects the first and second MOS transistors complementary to each other. The second constant current source is connected in series, the gate of the MOS transistor is connected to the output of the comparator, and the common connection point of the MOS transistors is connected to the input of the comparator. This has the effect of providing a synchronously separated output in which the output pulse width does not change even if the output pulse width changes.
第１図は本発明の一実施例の同期分離回路の回路図、第
２図は第１図の動作を示す波形図、第３図は従来の同期
分離回路図、第４図は第３図の動作を示す波形図である
。
１．５１・・・・・・複合映像信号入力端子、２゜５２
・・・・・・コンデンサ、３．５３・・・・・・フンパ
レータ、４．６１・・・・・・バイアス電源（ＶＢ）、
５，５４・・・・・・同期分離出力端子、６，９・・・
・・・定電流源、５７゜５８・・・・・・抵抗、７，８
，５６．５９・・・・・・ＭＯＳトランジスタ、１０．
５５・・・・・・電源（Ｖ Ｏ９）、２０゜２１・・・
・・・複合映像信号、１１．６０・・・・・・グランド
（ＧＮＤ）。
代理人 弁理士 内 原 晋
箒
／
国
卒
酊
箒
閲
第
コFIG. 1 is a circuit diagram of a synchronous separation circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of FIG. 1, FIG. 3 is a conventional synchronous separation circuit diagram, and FIG. FIG. 2 is a waveform diagram showing the operation of FIG. 1.51...Composite video signal input terminal, 2゜52
... Capacitor, 3.53 ... Humperator, 4.61 ... Bias power supply (VB),
5, 54... Synchronous separation output terminal, 6, 9...
...Constant current source, 57゜58...Resistance, 7,8
,56.59...MOS transistor, 10.
55...Power supply (V O9), 20°21...
...Composite video signal, 11.60...Ground (GND). Agent: Patent Attorney Shinho Uchihara / National Graduate Drunken Hoki Review Co.
Claims (1)
してコンパレータの一入力に接続され、前記コンパレー
タの他入力はバイアス電源に接続され、相補なるＭＯＳ
トランジスタの直列体を設け、前記直列体の両端にそれ
ぞれ第１、第２の定電流源を直列接続し、前記ＭＯＳト
ランジスタの共通接続点を前記コンパレータの一入力に
接続し、前記ＭＯＳトランジスタのゲートを互いに接続
して前記コンパレータの出力に接続したことを特徴とす
る同期分離回路。An input terminal into which a composite video signal is input is connected to one input of a comparator via a capacitor, and the other input of the comparator is connected to a bias power supply, and a complementary MOS
A series body of transistors is provided, first and second constant current sources are connected in series to both ends of the series body, a common connection point of the MOS transistors is connected to one input of the comparator, and a gate of the MOS transistor is connected to a common connection point of the MOS transistors. are connected to each other and connected to the output of the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23212490A JP2613964B2 (en) | 1990-08-31 | 1990-08-31 | Sync separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23212490A JP2613964B2 (en) | 1990-08-31 | 1990-08-31 | Sync separation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04117074A true JPH04117074A (en) | 1992-04-17 |
| JP2613964B2 JP2613964B2 (en) | 1997-05-28 |
Family
ID=16934381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23212490A Expired - Lifetime JP2613964B2 (en) | 1990-08-31 | 1990-08-31 | Sync separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2613964B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5410366A (en) * | 1993-11-01 | 1995-04-25 | Motorola, Inc. | Circuit and method of clamping a video signal with first and second current sources |
| KR20200021888A (en) | 2018-08-21 | 2020-03-02 | 토토 가부시키가이샤 | Deodorizing equipment for toilet space, and sanitary washing apparatus |
-
1990
- 1990-08-31 JP JP23212490A patent/JP2613964B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5410366A (en) * | 1993-11-01 | 1995-04-25 | Motorola, Inc. | Circuit and method of clamping a video signal with first and second current sources |
| KR20200021888A (en) | 2018-08-21 | 2020-03-02 | 토토 가부시키가이샤 | Deodorizing equipment for toilet space, and sanitary washing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2613964B2 (en) | 1997-05-28 |
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