JP2613964B2 - Sync separation circuit - Google Patents
Sync separation circuitInfo
- Publication number
- JP2613964B2 JP2613964B2 JP23212490A JP23212490A JP2613964B2 JP 2613964 B2 JP2613964 B2 JP 2613964B2 JP 23212490 A JP23212490 A JP 23212490A JP 23212490 A JP23212490 A JP 23212490A JP 2613964 B2 JP2613964 B2 JP 2613964B2
- Authority
- JP
- Japan
- Prior art keywords
- comparator
- input
- separation circuit
- capacitor
- sync separation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Synchronizing For Television (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は同期分離回路に係り、特にテレビやビデオ等
の分野の複合映像信号から同期信号を取り出す同期分離
回路に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization separation circuit, and more particularly to a synchronization separation circuit for extracting a synchronization signal from a composite video signal in the field of television, video, and the like.
第３図に、この種の従来例を示す。第３図において、
従来の同期分離回路は、入力端子51とコンデンサ52の一
端を接続し、コンデンサ52の他端と抵抗57と抵抗58との
接続点と、コンパレータ53の非反転入力（＋）端子を接
続し、コンパレータ53の反転入力（−）端子をバイアス
電源61に接続し、コンパレータ53の出力を、出力端子54
とＰチャンネルMOSトランジスタ56とＮチャンネルMOSト
ランジスタ59のゲートに接続し、ＰチャンネルMOSトラ
ンジスタ56のソースを電源55に接続し、ＰチャンネルMO
Sトランジスタ56のドレインと抵抗57の他端を接続し、
Ｎチャンネルトランジスタ59のソースとグランド60を接
続し、Ｎチャンネルトランジスタ59のドレインと抵抗58
の他端に接続する構成となっていた。FIG. 3 shows a conventional example of this kind. In FIG.
In the conventional sync separation circuit, the input terminal 51 is connected to one end of the capacitor 52, the other end of the capacitor 52 is connected to the connection point between the resistor 57 and the resistor 58, and the non-inverting input (+) terminal of the comparator 53 is connected. The inverting input (-) terminal of the comparator 53 is connected to the bias power supply 61, and the output of the comparator 53 is connected to the output terminal 54.
And the gates of the P-channel MOS transistor 56 and the N-channel MOS transistor 59, the source of the P-channel MOS transistor 56 is connected to the power supply 55,
Connect the drain of the S transistor 56 and the other end of the resistor 57,
The source of the N-channel transistor 59 is connected to the ground 60, and the drain of the N-channel transistor 59 and the resistor 58 are connected.
Connected to the other end of the device.
〔発明が解決しようとする課題〕 前述した従来の同期分離回路では、第３図にも示すよ
うに、複合映像信号21の同期時間t1と他の期間t2とに於
て、期間t1にコンデンサ52を充電する電荷と期間t2にコ
ンデンサ52を放電する電荷とが等しいときに、正常な同
期分離動作をする。即ち、t1:t2≒R57:R58に設定する事
により、同期分離動作をしていた。しかし映像信号が白
のときと黒のときとでは、期間t2にコンデンサ52を放電
する電荷が異なる為、同期分離された出力パルス幅が変
化するという欠点を持っていた。In conventional sync separator described above in which [Invention Problems to Solved] is Te at as shown in Figure 3, in a synchronization time t 1 and the other period t 2 of the composite video signal 21, the period t 1 when the charge and discharging the capacitor 52 to charge the period t 2 to charge the capacitor 52 is equal to, the normal sync separation operation. That is, the synchronization separation operation was performed by setting t 1 : t 2同期 R 57 : R 58 . However, in the case the video signal is black when the white, for the charge to discharge the capacitor 52 during the period t 2 are different, had the disadvantage of sync separator output pulse width changes.
本発明の目的は、前記欠点を解決し、同期分離された
出力パルス幅が変化しないようにした同期分離回路を提
供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a sync separation circuit which solves the above-mentioned drawbacks and does not change the output pulse width after sync separation.
本発明の同期分離回路の構成は、複合映像信号が入力
される入力端子は、コンデンサを介してコンパレータの
−入力に接続され、前記コンパレータの他入力はバイア
ス電源に接続され、相補なるMOSトランジスタの直列体
を設け、前記直列体の両端にそれぞれ第1,第２の定電流
源を直列接続し、前記MOSトランジスタの共通接続点を
前記コンパレータの−入力に接続し、前記MOSトランジ
スタのゲートを互いに接続して前記コンパレータの出力
に接続したことを特徴とする。In the configuration of the sync separation circuit of the present invention, an input terminal to which a composite video signal is input is connected to a negative input of a comparator via a capacitor, and another input of the comparator is connected to a bias power supply, and a complementary MOS transistor is connected. A series body is provided, first and second constant current sources are connected in series to both ends of the series body, a common connection point of the MOS transistors is connected to a negative input of the comparator, and gates of the MOS transistors are connected to each other. Connected to the output of the comparator.
次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の同期分離回路を示す回路
図である。第１図において、本実施例は、入力端子１を
コンデンサ２の一端と接続し、コンデンサ２の他端をコ
ンパレータ３の非反転入力（＋）とＰチャンネルMOSト
ランジスタ７、及びＮチャンネルMOSトランジスタ８の
ドレインと接続する。コンパレータ３の反転入力（−）
をバイアス電源４に接続する。コンパレータ３の出力を
出力端子５、及びＰチャンネルトランジスタ７のゲート
Ｎチャンネルトランジスタ８のゲートに接続する。Ｐチ
ャンネルトランジスタ７のソースは、定電流源６を介し
て、VDD電源10に接続する。Ｎチャンネルトランジスタ
８のソースは、定電流源９を介して、グランド11に接続
する。FIG. 1 is a circuit diagram showing a sync separation circuit according to one embodiment of the present invention. 1, in this embodiment, an input terminal 1 is connected to one end of a capacitor 2, and the other end of the capacitor 2 is connected to a non-inverting input (+) of a comparator 3, a P-channel MOS transistor 7, and an N-channel MOS transistor 8. Connect to the drain of Inverting input of comparator 3 (-)
Is connected to the bias power supply 4. The output of the comparator 3 is connected to the output terminal 5 and the gate of the P-channel transistor 7 and the gate of the N-channel transistor 8. The source of the P-channel transistor 7 is connected to the VDD power supply 10 via the constant current source 6. The source of the N-channel transistor 8 is connected to the ground 11 via the constant current source 9.
本実施例の同期分離回路は、第２図に示すように、複
合映像信号20の同期信号t11と他の期間t12に於て、期間
t11にコンデンサ２を充電する電荷と、期間t12にコンデ
ンサ２を放電する電荷とが等しいときに、正常な同期分
離動作をする。即ち、定電流源６の電流値をI6、定電流
源９の電流値をI9としたとき、t11:t12＝I9:I6に設定す
る事により、同期分離動作をする。ここで、従来回路で
問題となった映像信号20が白のときと黒のときとでも、
I9は一定の電流値であり、コンデンサ２を放電する電荷
に差異は無く、出力パルス幅変動のない同期分離出力が
得られる。Sync separation circuit of this embodiment, as shown in FIG. 2, At a synchronizing signal t 11 and another period t 12 of the composite video signal 20, the period
a charge to charge the capacitor 2 to t 11, when are equal and charges discharging the capacitor 2 during the period t 12, a normal sync separation operation. That is, when the current value of the constant current source 6 is I 6 and the current value of the constant current source 9 is I 9 , the synchronous separation operation is performed by setting t 11 : t 12 = I 9 : I 6 . Here, even when the video signal 20 which is a problem in the conventional circuit is white and black,
I 9 is a constant current value, a difference in charge of discharging the capacitor 2 is not, the sync separator output without output pulse width variation is obtained.
以上説明したように、本発明は、コンパレータの反転
入力をバイアス電源に接続し、非反転入力にはコンデン
サを介して複合映像信号を入力すると同時に、互いに相
補なるMOSトランジスタと第1,第２の定電流源とを直列
接続し、前記MOSトランジスタのゲートをコンパレータ
の出力に接続し、MOSトランジスタの共通接続点をコン
パレータの入力に接続しているから、複合映像信号が、
白，黒に変化しても、出力パルス幅が変化しない同期分
離出力が得られる効果がある。As described above, the present invention connects the inverting input of the comparator to the bias power supply, inputs the composite video signal to the non-inverting input via the capacitor, and simultaneously sets the complementary MOS transistors and the first and second MOS transistors. A constant current source is connected in series, the gate of the MOS transistor is connected to the output of the comparator, and the common connection point of the MOS transistor is connected to the input of the comparator.
Even if the output pulse width changes to white or black, there is an effect that a sync separation output in which the output pulse width does not change can be obtained.
第１図は本発明の一実施例の同期分離回路の回路図、第
２図は第１図の動作を示す波形図、第３図は従来の同期
分離回路図、第４図は第３図の動作を示す波形図であ
る。 1,51……複合映像信号入力端子、2,52……コンデンサ、
3,53……コンパレータ、4,61……バイアス電源（VB）、
5,54……同期分離出力端子、6,9……定電流源、57,58…
…抵抗、7,8,56,59……MOSトランジスタ、10,55……電
源（VDD）、20,21……複合映像信号、11,60……グラン
ド（GND）。FIG. 1 is a circuit diagram of a sync separation circuit according to one embodiment of the present invention, FIG. 2 is a waveform diagram showing the operation of FIG. 1, FIG. 3 is a diagram of a conventional sync separation circuit, and FIG. FIG. 6 is a waveform chart showing the operation of FIG. 1,51: Composite video signal input terminal, 2,52: Capacitor,
3,53… Comparator, 4,61… Bias power supply (VB),
5,54: Synchronous separation output terminal, 6,9: Constant current source, 57,58
... resistance, 7,8,56,59 ... MOS transistor, 10,55 ... power (V DD ), 20,21 ... composite video signal, 11,60 ... ground (GND).
Claims (1)
ンデンサを介してコンパレータの−入力に接続され、前
記コンパレータの他入力はバイアス電源に接続され、相
補なるMOSトランジスタの直列体を設け、前記直列体の
両端にそれぞれ第1,第２の定電流源を直列接続し、前記
MOSトランジスタの共通接続点を前記コンパレータの−
入力に接続し、前記MOSトランジスタのゲートを互いに
接続して前記コンパレータの出力に接続したことを特徴
とする同期分離回路。An input terminal to which a composite video signal is input is connected to a negative input of a comparator via a capacitor, and the other input of the comparator is connected to a bias power supply, and a series body of complementary MOS transistors is provided. First and second constant current sources are connected in series to both ends of the series body,
The common connection point of the MOS transistors is
A sync separation circuit connected to an input, the gates of the MOS transistors connected to each other, and connected to an output of the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23212490A JP2613964B2 (en) | 1990-08-31 | 1990-08-31 | Sync separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23212490A JP2613964B2 (en) | 1990-08-31 | 1990-08-31 | Sync separation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04117074A JPH04117074A (en) | 1992-04-17 |
| JP2613964B2 true JP2613964B2 (en) | 1997-05-28 |
Family
ID=16934381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23212490A Expired - Lifetime JP2613964B2 (en) | 1990-08-31 | 1990-08-31 | Sync separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2613964B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5410366A (en) * | 1993-11-01 | 1995-04-25 | Motorola, Inc. | Circuit and method of clamping a video signal with first and second current sources |
| KR20200021888A (en) | 2018-08-21 | 2020-03-02 | 토토 가부시키가이샤 | Deodorizing equipment for toilet space, and sanitary washing apparatus |
-
1990
- 1990-08-31 JP JP23212490A patent/JP2613964B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04117074A (en) | 1992-04-17 |
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