JPH04116938A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPH04116938A JPH04116938A JP2238097A JP23809790A JPH04116938A JP H04116938 A JPH04116938 A JP H04116938A JP 2238097 A JP2238097 A JP 2238097A JP 23809790 A JP23809790 A JP 23809790A JP H04116938 A JPH04116938 A JP H04116938A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- compound semiconductor
- iii
- group
- atoms
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 230000005669 field effect Effects 0.000 title claims description 3
- 239000004065 semiconductor Substances 0.000 claims abstract description 25
- 150000001875 compounds Chemical class 0.000 claims abstract description 23
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 abstract description 10
- 238000012545 processing Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 229910021478 group 5 element Inorganic materials 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 6
- 125000004429 atom Chemical group 0.000 description 6
- 238000012546 transfer Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004943 liquid phase epitaxy Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 101000960224 Clarkia breweri (Iso)eugenol O-methyltransferase Proteins 0.000 description 1
- -1 GaAs compound Chemical class 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 125000002346 iodo group Chemical group I* 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電界効果トランジスタ（ＦＥＴ）特に■−Ｖ
族化合物半導体、例えばＭｔＧａＡｓ／ ＩｎＧａＡｓ
／ＧａＡｓによる歪層を有するモジニレ−ジョンドープ
構造の高電子移動度トランジスタ（ＨＥＭＴ）の製法に
係わる。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to field effect transistors (FETs), particularly ■-V
Group compound semiconductors, such as MtGaAs/InGaAs
The present invention relates to a method for manufacturing a high electron mobility transistor (HEMT) having a modinilation doped structure having a strained layer made of /GaAs.
本発明はＦＥＴの製法に関わり、■−Ｖ族化合物半導体
基体上に、■−■族化合物半導体より成るチャンネル形
成層と、これに比しバンドギャップの大きい１の導電型
を有する■−ｖ族化合物半導体より成るバリア層とをエ
ピタキシャル成長し、後の工程でＶ族の原子を含む雰囲
気中で６５０℃〜８５０℃の熱処理を行うことにより広
範囲のゲート電圧に対し伝達コンダクタンス９ｍの向上
をはかる。The present invention relates to a method for manufacturing an FET, and includes a channel forming layer made of a ■-V group compound semiconductor on a ■-V group compound semiconductor substrate, and a ■-V group compound semiconductor having a conductivity type 1 having a larger band gap compared to the channel forming layer. By epitaxially growing a barrier layer made of a compound semiconductor and performing heat treatment at 650° C. to 850° C. in an atmosphere containing group V atoms in a later step, the transfer conductance is improved to 9 m over a wide range of gate voltages.
従来、超高周波用ＦＥＴとしては、低雑音特性を生かし
たモジユレーション・ドープ構造のＨＥＭＴの検討が活
発に行われている。Conventionally, as ultra-high frequency FETs, HEMTs with a modulation doped structure that take advantage of low noise characteristics have been actively studied.
第１図は、歪層を有するＨＥＭＴ （いわゆるＰｓｕｄ
。Figure 1 shows a HEMT with a strained layer (so-called Psud
.
ｍｏｒｐｈｉｃ ＨＥＭＴ） の路線的断面図で、例
えばＧａＡｓサブストレイト（２）上に超格子構造のバ
ッファＭ （３） ’Ｅ−介して半絶縁性の例えばＧａ
Ａｓ化合物半導体層（４）がエビタキーされて成る■−
ｖ族化合物半導体装置（１）上に続いてこれに比しエネ
ルギーバンドギャップが小さいノンドープのＩｎＧａＡ
Ｓより成る歪層によるチャンネル形成層（５）と、極薄
のノンドープのスペーサ層（６）と、１の導電型一般に
はＳｉがドープされたｎ型を有し、歪層によるチアンネ
ル層（５）に比しエネルギーバンドギャップが大きいＭ
Ｉ Ｇ ａ Ａ ｓによるバリア層（７）が連続的にエ
ピタキンーされる。そしてこのバリア層（７）上にこれ
に対しンヨットキー接合を形成するショットキー金属ゲ
ート電極（８）が被着され、これを挟んでその両側にソ
ース及びドレイン電極（９）及び（１０）が例えばアロ
イによってチャンネル形成層（５）に達する深さに形成
される。This is a cross-sectional view of a semi-insulating, e.g. GaAs substrate (2) with a superlattice structure buffer M (3)
The As compound semiconductor layer (4) is evita-keyed ■-
Next to the V-group compound semiconductor device (1) is non-doped InGaA, which has a smaller energy bandgap than this.
A channel forming layer (5) made of a strained layer made of S, an ultra-thin non-doped spacer layer (6), and a channel layer (5) made of a strained layer having the conductivity type 1, which is generally an n-type doped with Si. ) has a larger energy bandgap than M
A barrier layer (7) of IGaAs is successively epitakinized. A Schottky metal gate electrode (8) forming a Njotky junction is deposited on this barrier layer (7), and source and drain electrodes (9) and (10) are placed on both sides of the barrier layer (7), for example. It is formed by the alloy to a depth that reaches the channel forming layer (5).
この構成によるＨＩＪＩＴは、ＧａＡｓ上にこれより格
子定数の大きいＩｎＧａＡｓ層を堆積させるものである
が、その厚さを、転位の発生が生じる膜［（これを臨界
膜厚という）より小に選定させれば、第９図にそのバン
ドモデル図を示すように、その伝導帯に、大きなオフセ
ット電圧ΔＥｃ を有するチャンネルを形成することが
できることから、歪層によらない通常の２次元電子ガス
（２０ＥＧ）チャンネルによるＨＥＭＴに比し、電荷量
を大きくすることができ、これによって伝達コンダクタ
ンス９ｍを高めることができるという特徴を有する。第
９図においてＥ。HIJIT with this configuration deposits an InGaAs layer with a larger lattice constant on GaAs, but its thickness is selected to be smaller than the film at which dislocations occur (this is called the critical film thickness). If so, as shown in the band model diagram in Figure 9, a channel with a large offset voltage ΔEc can be formed in the conduction band. Compared to a HEMT using a channel, this has the feature that the amount of charge can be increased, and thereby the transfer conductance can be increased by 9m. E in FIG.
はフエミレベルを示す。indicates the feminine level.
ところがこの歪層を有するＨＥＭＴは第１０図にそのゲ
ート電圧ｖ０ に対する ＣＫ＜ ｒ ａ −：ソース
・ドレイン間電流）と９ｍ（ミリシーメンス／ｍｍ）を
曲線（１０１） 及び（１０２） で示すように、
ＶＧ が高くなると９ｍが低下するという特性を示し。However, in the HEMT having this strained layer, the curves (101) and (102) show CK< r a -: source-drain current) and 9 m (mS/mm) with respect to the gate voltage v0 in Fig. 10. ,
It exhibits a characteristic that as VG increases, 9m decreases.
これは、歪層における本来のチャンネルとは別にこれと
平行に、ＶＣを上げることによって第９図に鎖線ａで示
すように、バリア層（７）中にチャンネルいわゆるパラ
レル・コンダクタンスが生じて来ることに因ると思われ
る。This is due to the fact that, apart from and parallel to the original channel in the strained layer, by increasing VC, a so-called parallel conductance channel is generated in the barrier layer (7), as shown by the chain line a in Figure 9. This seems to be due to.
上述したように、歪層を有するＦＥＴ例えば１１ＥＭＴ
は、超高周波用としての利点を有するものの、ゲート電
圧ＶＧ に対する伝達コンダクタンス９ｍ点がある。し
たがってこの種のＦＥＴをリニアＩＣ等に応用する場合
、動作点でゲインが低下してしまうという課題がある゛
。As mentioned above, a FET with a strained layer, e.g. 11EMT
Although it has an advantage for ultra-high frequency applications, it has a transfer conductance of 9m with respect to the gate voltage VG. Therefore, when this type of FET is applied to a linear IC or the like, there is a problem that the gain decreases at the operating point.
本発明はこのような課題の解決をはかる。 The present invention aims to solve such problems.
すなわち、本発明においては、伝達コンダクタンス９ｍ
の向上をはかると同時にそのゲート電圧依存性が平坦な
特性を有するＦＥＴ、例えば歪層を有するＨＥＭＴを得
ることができるようにする。That is, in the present invention, the transfer conductance is 9 m.
It is thus possible to obtain an FET, for example, a HEMT having a strained layer, which has a flat gate voltage dependence.
本発明は、例えば第１図でその一例の路線的断面図を示
すように、■−ｖ族化合物半導体基体（１）上に、これ
に比しバンドギャップの小さいＩＩ［−Ｖ族化合物半導
体より成るチャンネル形成１１（５）と、このチャンネ
ル形成層（５）に比しバンドギャップの大きい■−■族
化合物半導体より成るバリア層（７）を、必要に応じて
アンドープの極薄のスペーサ層（６）を介してエピタキ
シャル成長してその後の工程で、これら■−Ｖ族化合物
半導体の■族の原子を含む雰囲気中でｆｌｉ５０℃〜８
５０℃の熱処理を行う。For example, as shown in FIG. 1, which shows an example of the cross-sectional view, the present invention is based on a compound semiconductor substrate (1) of a group II-V compound semiconductor having a smaller bandgap than that of a group II[-V compound semiconductor substrate (1). A barrier layer (7) made of a ■-■ group compound semiconductor having a larger band gap than this channel forming layer (5) is optionally coated with an undoped ultra-thin spacer layer ( 6), and in the subsequent process, fli50℃~8.
Heat treatment is performed at 50°C.
上述した熱処理を行った歪層を有するＦＥＴは、９ｍの
向上と、ゲート電圧Ｖ、に対する９ｍの変化の改善をは
かることができた。The FET having the strained layer subjected to the heat treatment described above was able to achieve an improvement of 9 m and a change in gate voltage V of 9 m.
これは、第１＋、：Ｖ族の過剰蒸気圧雰囲気中での熱処
理によって、■族原子の拡散が助長されること（Ｉｎｓ
ｔ、 Ｐｈｙｓ、 Ｃｏｎｆ、 Ｓｅｒ、Ｎｏ ９６；
１９８８ Ｐ３９３〜Ｐ３９６参照）から、例えば第
２図に示すように、加熱前で実線図示のモデルが加熱後
に破線すで示すように緩やかになることによって、バリ
ア層（７）の厚みが減少し、又チャンネル層の厚みが増
加すること。This is because the heat treatment in the excess vapor pressure atmosphere of the 1+, :V groups promotes the diffusion of group Ⅰ atoms (Ins.
t, Phys, Conf, Ser, No 96;
1988 P393-P396), for example, as shown in FIG. 2, the model shown by the solid line before heating becomes gentler as shown by the broken line after heating, so that the thickness of the barrier layer (7) decreases, Also, the thickness of the channel layer increases.
第２にこのような■族原子の相互拡散により、界面での
結晶性、例えば界面の組成のゆらぎや、格子不整合に起
因する欠陥が減少すること。Second, such interdiffusion of group III atoms reduces crystallinity at the interface, such as fluctuations in composition at the interface and defects caused by lattice mismatch.
第３に、熱処理によってドーパントのＳｉもチャンネル
側に拡散することからチャンネル中でＳｉが活性化して
、いわゆるＭＥＳ（金属−半導体装置ＥＴ、接合ＦＥＴ
などのドープト・チャンネル型のＦＥＴに特性が近づく
ことによってバリア層におけるチャンネルの発生、すな
わちパラレル・コンダクタンスの発生が抑制され、なお
かつ、チャンネルとゲート電極が近づくことにより、ゲ
ートとチャンネルの容量結合が大きくなることに因ると
思われる。Thirdly, as the dopant Si also diffuses to the channel side by heat treatment, Si is activated in the channel, resulting in so-called MES (metal-semiconductor devices ET, junction FETs).
By bringing the characteristics closer to those of doped channel type FETs, the generation of a channel in the barrier layer, that is, the generation of parallel conductance, is suppressed, and by bringing the channel and gate electrode closer together, capacitive coupling between the gate and channel is increased. This seems to be due to the fact that
第１図を参照して本発明を歪層を有するＨ Ｅ ！Ｊ
Ｔ、特にｎ −Ａｊｉ！ｙＧａＡｓ ＋ −ｙＡｓ／
ＩｎｘＧａ ＋−ｘＡｓ／ＧａＡｓによるＭＥＭＴを得
る場合の一実施例を説明する。Referring to FIG. 1, the present invention will be described with reference to FIG. J
T, especially n-Aji! yGaAs + −yAs/
An example of obtaining MEMT using InxGa + -xAs/GaAs will be described.
この場合例えばＧａＡｓサブストレイト（２）上に超格
子構造のバッファ層（３）を介して半絶縁性の例えばＧ
ａＡｓ化合物半導体層（４）がエピタキシーされた■−
■族のＧａＡｓ化合物半導体基体（１）上に、続いてＧ
ａＡｓ基体〔１）に比しエネルギーバンドギャップが小
さいノンドープのｒｎｘＧａ＋−ｘより成る歪層すなわ
ちチャンネル形成層（５）と、厚さｔが０〜ＩＯＡ程度
の極薄のノンドープのスペーサ層（６）と、１の導電型
例えばＳｉがドープされたｎ型を有し、チャンネル形成
層（５）に比しエネルギーバンドギャップが大きいＡｊ
２ｙＧａｌ−ｙＡＳによるバリア層（７）を連続的にＭ
ＯＣＶＤ （有機金属化学的気相成長法）、ＭＢＥ（分
子線エピタキシ）、ＬＰＥ（液相エピタキシ）等によっ
て成長させる。In this case, for example, a semi-insulating layer of, for example, G
- The aAs compound semiconductor layer (4) is epitaxyed.
On the group III GaAs compound semiconductor substrate (1),
A strained layer or channel forming layer (5) made of non-doped rnxGa+-x with a smaller energy bandgap than the aAs substrate [1), and an extremely thin non-doped spacer layer (6) with a thickness t of about 0 to IOA. Aj has a conductivity type 1, for example, an n-type doped with Si, and has a larger energy band gap than the channel forming layer (5).
The barrier layer (7) made of 2yGal-yAS is continuously coated with M
The growth is performed by OCVD (metal-organic chemical vapor deposition), MBE (molecular beam epitaxy), LPE (liquid phase epitaxy), or the like.
その後、その■族原子のＡｓ圧下、具体的にはＡｓｔｌ
、のオーバープレッシャ（過剰蒸気圧雰囲気）下でのラ
ンプアニール等のＲＴ Ａ （Ｒａｐｉｄ Ｔｈｅｒｍ
ａｌＡｎｎｅａｌ）で６５０℃〜８５０℃の加熱を行う
。この場合の＾Ｓ分圧は、熱処理温度におけるＡｓ蒸気
圧より高い例えば１００倍程度の＾Ｓ分圧とする。After that, the As compression of the group III atoms, specifically Astl
RT A (Rapid Thermal) such as lamp annealing under overpressure (excess vapor pressure atmosphere) of
heating at 650°C to 850°C. The ^S partial pressure in this case is set to be, for example, about 100 times higher than the As vapor pressure at the heat treatment temperature.
そしてバリア層（７）上にこれに対し、ショットキー接
合を形成するショットキー金属ゲート電極（８）を被着
し、これを挟んでその両側にソース及びドレイン電極（
９）及び（１０）を例えばアロイによってチャンネル形
成層（５）に達する深さに形成する。In contrast, a Schottky metal gate electrode (8) forming a Schottky junction is deposited on the barrier layer (7), with source and drain electrodes (
9) and (10) are formed by, for example, an alloy to a depth that reaches the channel forming layer (5).
このようにして得たＨＥＭＴにおいて、バリア層（７）
のＡＪｌｙ＝０．３ 、チャンネル形成層（５）のＩｎ
１ｘ＝０．２ とし、チャンネル形成層（５）の厚さＤ
を１５０人とし、ゲート長Ｌｇ及びＷｇを、Ｌｇ＝１μ
ｍ、Ｗｇ＝１００μｍとしたときの、その熱処理を７５
０℃、１０秒間行った場合と、８５０℃、１０秒間行っ
た場合の、それぞれのＶｇ に対する９ｍ及び Ｊπを
第３図及び第４図に示す。曲線（３１）及び（４１）は
９ｍ−Ｖｇｇｍ、（３２） 及ヒ＜４２＞ ＋ｔ ｆ「
＝−Ｖｇ 曲ｗｓ ヲ示す。前述の第１１図中曲線（１
１）及び（１２）はそれぞれこのＨＥ Ｍ Ｔの熱処理
前の同様の９ｍ−Ｖｇ及びＥ’：”、−ｖｇ曲線で、こ
れらを比較して明らかなように、熱処理を行う本発明方
法によって得られたＨＥＭＴによる場合、Ｖｇを上げて
行ったときの’Ｊｔｎの低下を格段に小さく抑えること
ができた。In the HEMT thus obtained, the barrier layer (7)
AJly=0.3, In of the channel forming layer (5)
1x=0.2, and the thickness D of the channel forming layer (5)
150 people, gate length Lg and Wg, Lg=1μ
m, Wg = 100 μm, the heat treatment is 75
Figures 3 and 4 show 9m and Jπ for Vg when the test was carried out at 0°C for 10 seconds and when the test was carried out at 850°C for 10 seconds, respectively. Curves (31) and (41) are 9m-Vggm, (32)
=-Vg Indicates the song ws. The curve (1
1) and (12) are similar 9m-Vg, E':'', -vg curves of this HEMT before heat treatment, and as is clear from comparing these, the curves obtained by the heat treatment method of the present invention are In the case of the HEMT, the decrease in 'Jtn when Vg was increased could be suppressed to a much smaller level.
また、第５図はこの熱処理（アニール）温度と９ｆｆｌ
の関係の測定結果を、ｌｎｏ、 ２゜Ｇａｏｌ。＾Ｓの
歪層（５）の厚さＤをそれぞれ５０Ａ（Ｘ印でプロット
）、１５０人（ム印でプロット）、について示したもの
で、熱処理によってｇｍの向上がみられる。Also, Figure 5 shows this heat treatment (annealing) temperature and 9ffl.
The measurement result of the relationship is lno, 2°Gaol. The thickness D of the strained layer (5) of ^S is shown for 50A (plotted with an X mark) and 150 people (plotted with a mu mark), respectively, and it can be seen that gm is improved by heat treatment.
更に、ｌｎｏ、 ２Ｇａ０１ＡＳによる歪層（５）の厚
さＤを変化させたときの歪層（５）からＡｊ’ｏ、 ３
Ｇｌｏ、 ＪＳバリア層（７）へのＩｎの拡散と、同様
のバリア層（７）から歪層（５〕へのＭの拡散と熱処理
温度との関係の測定結果を第６図及び第７図にそれぞれ
Ｄ ＝３００人をＥ印、Ｄ＝２００人をΔ印、Ｄ＝１０
０人をＯで示す。これらによれば処理温度を上げるほど
拡散定数は大きくなるるが、同時に膜厚が大となるにつ
れその拡散が大きくなっている。つまりこれら拡散は膜
厚に依存していて、この膜厚が完全に転位が発生して歪
が開放される厚さ以下、つまり臨界膜厚以下で、その厚
さが厚いほどＩｎ及びＭの拡散が良好に行われることに
なって、このＨＥＭＴが第２図で説明したようにバンド
ギャップのオフセット部でなだらかに、云い換えれば通
常のドープト・チャンネルＦＥＴの特性に近づくと考え
られる。つまり、パラレル・コンダクタンスの発生が回
避されゲート電圧Ｖｇ に対する伝達コンダクタンス９
ｍの依存性を良好に改善できることになる。Furthermore, Aj'o, 3 from the strained layer (5) when the thickness D of the strained layer (5) made of lno, 2Ga01AS is changed.
Figures 6 and 7 show the measurement results of the relationship between the diffusion of In into the Glo, JS barrier layer (7), the diffusion of M from the similar barrier layer (7) to the strained layer (5), and the heat treatment temperature. D = 300 people are marked E, D = 200 people are marked Δ, and D = 10.
0 people are indicated by O. According to these, the diffusion constant increases as the processing temperature increases, but at the same time, as the film thickness increases, the diffusion increases. In other words, these diffusions depend on the film thickness, and when this film thickness is below the thickness at which dislocations are completely generated and strain is released, that is, below the critical film thickness, the thicker the film thickness, the more In and M will diffuse. It is considered that this HEMT is smoothly performed in the bandgap offset portion as explained in FIG. 2, or in other words, approaches the characteristics of a normal doped channel FET. In other words, the generation of parallel conductance is avoided and the transfer conductance 9 with respect to the gate voltage Vg
This means that the dependence of m can be favorably improved.
尚、この歪層（５）の転位が生じる臨界膜厚は実際には
、成る膜厚で急激に転位が発生するという明確なもので
はなく、徐々に転位の発生が見られるという類いのもの
であって、更にこの歪層（５）の発生は、ＩｎＧａＡｓ
ｘＡｓにおいてＸの値がｘ＝ｏ、２程度に小さいものに
おいても、２００Ａ〜２５０人から幾分の転位の発生が
みられる。The critical film thickness at which dislocations occur in this strained layer (5) is not actually a clear film thickness at which dislocations occur suddenly, but rather a film thickness at which dislocations occur gradually. Moreover, the generation of this strained layer (5) is caused by InGaAs
Even in xAs, where the value of X is as small as x=o, about 2, some dislocations occur from 200A to 250A.
今Ｘの値が０．２に選ばれると、計算上では、チャンネ
ルを形成する量子井戸の電子が最大に蓄えられる幅りは
、１５０人となるが＜１９８７１ＥＤＭ（Ｉｎｔｅｒｎ
ａｔｉｏｒ＋ａｌεＩｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｍ
ｅｅｔｉｒ＋ｇ）Ｐ４１８〜Ｐ４２８参照）、実際上は
、電子移動度等の特性を勘案して、Ｘ及びＤの選定がな
される。しかしながら第９図にそのＩｎの含有量Ｘ及び
歪（Δａ ／ ａ：ａはＧａＡｓの格子定数、ΔａはＧ
ａＡｓとＩｎＧａＡｓの各格定数の差）と、臨界膜厚の
関係を示すように、斜線を付した部分が転位の発生が殆
どみられない領域でしたがって歪層を有するＨＥＭＴに
おいては、この斜線範囲でなおかつ歪（ｓｔｒａｉｎ）
が４％以下に選ばれる。If the value of
atior+alεIectron Device M
(see P418 to P428), in practice, X and D are selected in consideration of characteristics such as electron mobility. However, Fig. 9 shows the In content X and the strain (Δa/a: a is the lattice constant of GaAs, Δa is the G
As shown in the figure, the shaded area is a region where almost no dislocations occur, and therefore in a HEMT with a strained layer, the shaded area is Strain
is selected to be 4% or less.
上述の本発明方法によるＦＥＴ、例えばＩｎＧａＡｓに
よる）ＩＥＭＴは、これが歪層を有する）ｌ Ｅ Ｍ
Ｔであることから上述したギャップのΔＥｃ が大で、
その２次元電子ガス濃度を高めることができると共に、
電子輸送特性にすぐれたＩｎＧａＡｓを用いたことによ
る高伝達コンダクタンス９１Ｉｌが得られ、これによっ
てｆ Ｔ （ｆ ｔ＝ ９ｍ／２ πＣｇｓ、ここで口
ｇｓ はゲート・ソース間容量）の向上、したがって
高速性、高性能性を有するが、加えて本発明方法ではそ
のチャンネル形成歪層（５）の厚さの選定及び熱処理に
よってゲート電圧Ｖｇ に対する９ｍの変化を抑制する
ことができたのである。The FET according to the method of the invention described above, for example an IEMT (made of InGaAs), which has a strained layer) l E M
Since T, the above-mentioned gap ΔEc is large,
The two-dimensional electron gas concentration can be increased, and
By using InGaAs, which has excellent electron transport properties, a high transfer conductance of 91Il is obtained, which improves f T (f t = 9m/2 πCgs, where gs is the gate-source capacitance), and therefore improves high speed. In addition, the method of the present invention was able to suppress a change of 9 m with respect to the gate voltage Vg by selecting the thickness of the channel forming strained layer (5) and heat treatment.
尚、上述した例ではｎ −ＡＡ’ＧａＡｓ／ＩｎＧａＡ
ｓ／ＧａＡｓの歪層を宥するＨＥＭＴに本発明を適用し
た場合であるが、他の■−ｖ族化合物半導体の歪層を有
する、もしくは有しない通常のＨＥ ！Ｊ Ｔ等のＦＥ
Ｔに適用することができる。In the above example, n -AA'GaAs/InGaA
This is a case in which the present invention is applied to a HEMT with a strained layer of s/GaAs, but it can be applied to a normal HEMT with or without a strained layer of other ■-v group compound semiconductors! FE such as J.T.
It can be applied to T.
また上述した例では、各層（３）〜（７）のエピタキシ
ー後に■族原子を含む雰囲気中での熱処理を施した場合
であるが、これら層の形成後の例えばソース・ドレイン
部にゲート電極をマスクとして低抵抗化のためのイオン
注入を行う場合のアニール処理時に行うこともできるな
ど、他の熱処理工程と兼ねしめることもできる。Furthermore, in the above example, after epitaxy of each layer (3) to (7), heat treatment is performed in an atmosphere containing group III atoms. It can also be used as a mask during annealing when performing ion implantation to lower resistance, and can also be used in combination with other heat treatment steps.
上述の本発明方法によれば、高い’ｊｍ ％ ｆ、が得
られると共に、Ｖ族原子を含む雰囲気中での熱処理を行
ったことによって■族原子の移動を活性にし、例えばｎ
−ＡＡ’ＧａＡｓ／ＩｎＧａＡｓ／ＧａＡｓ系のＨＥ
ＭＴに右いて、そのＡ４５Ｉｎの拡散を高め、更にその
熱処理によって例えばｎ−ＡＡＩＧａＡｓ中のドーパン
トとしてのＳｉの拡散によって、ドープト・チャンネル
様の特性を示し、パラレルコンダクタンス発生の抑制を
行うことができゲート電圧Ｖｇ に対する９ｍの変化を
抑制できることから、リニアＩＣ等に適用して動作点で
ゲインの低下を来すなどの不都合を回避でき、実用上大
きな利点をもたらすことができる。According to the above-mentioned method of the present invention, a high 'jm % f can be obtained, and the heat treatment in an atmosphere containing group V atoms activates the movement of group II atoms, for example, n
-AA'GaAs/InGaAs/GaAs-based HE
By increasing the diffusion of A45In in the MT and further by heat treatment, for example, by diffusing Si as a dopant in n-AAIGaAs, the gate exhibits doped channel-like characteristics and suppresses the generation of parallel conductance. Since the variation of 9 m with respect to the voltage Vg can be suppressed, it is possible to avoid problems such as a decrease in gain at the operating point when applied to a linear IC, etc., and it is possible to bring about a great practical advantage.
第１図は本発明を適用する一例の歪層を有するＨＥＭＴ
の断面図、第２図はその歪層近傍のバンドモデル図、第
３図及び第４図は本発明方法によって得たＨＥＭＴのゲ
ート電圧に対する９ｍ及び 飼の関係を示す図、第５図
は熱処理温度と９ｍの関係を示す図、第６図及び第７図
はそれぞれ熱処理温度とＭ及びＩｎの拡散定数の関係を
示す図、第８図はＩｎ１Ｘ及び歪と臨界膜厚の関係を示
す図、第９図は従来方法によって得た歪層を有するＨＥ
ＭＴノバンドモデル図、第１０図はそのゲート電圧Ｖｇ
に対する９ｍ及びＪ「ニーの関係を示す図である。
（１）は■−ｖ族化合物半導体基体、（２）はサブスト
レイト、（３）はバッファ層、（４）は基体層、（５）
は歪層、（６）はスペーサ、（７）はバリア層である。FIG. 1 shows an example of a HEMT with a strained layer to which the present invention is applied.
2 is a band model diagram near the strained layer, FIGS. 3 and 4 are diagrams showing the relationship between 9m and 9m with respect to the gate voltage of the HEMT obtained by the method of the present invention, and FIG. A diagram showing the relationship between temperature and 9m, Figures 6 and 7 are diagrams each showing the relationship between heat treatment temperature and the diffusion constants of M and In, and Figure 8 is a diagram showing the relationship between In1X and strain and critical film thickness. Figure 9 shows an HE with a strained layer obtained by the conventional method.
MT band model diagram, Figure 10 shows its gate voltage Vg
FIG. 9 is a diagram showing the relationship between 9m and J'knee. (1) is a ■-v group compound semiconductor substrate, (2) is a substrate, (3) is a buffer layer, (4) is a base layer, (5)
is a strained layer, (6) is a spacer, and (7) is a barrier layer.
Claims (1)
族化合物半導体より成る１の導電型を有するバリア層と
をエピタキシャル成長し、 その後の工程で上記Ｖ族原子を含む雰囲気中で６５０℃
〜８５０℃の熱処理を行うことを特徴とする歪層を有す
る電界効果トランジスタの製法。[Claims] A channel forming layer made of a III-V compound semiconductor on a III-V compound semiconductor substrate;
A barrier layer having conductivity type 1 made of a group compound semiconductor is epitaxially grown, and in a subsequent step, the layer is grown at 650°C in an atmosphere containing the group V atoms.
A method for manufacturing a field effect transistor having a strained layer, characterized by performing heat treatment at ~850°C.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2238097A JPH04116938A (en) | 1990-09-07 | 1990-09-07 | Manufacture of field effect transistor |
| KR1019910015541A KR100217710B1 (en) | 1990-09-07 | 1991-09-06 | Manufacturing method of a field efect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2238097A JPH04116938A (en) | 1990-09-07 | 1990-09-07 | Manufacture of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04116938A true JPH04116938A (en) | 1992-04-17 |
Family
ID=17025128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2238097A Pending JPH04116938A (en) | 1990-09-07 | 1990-09-07 | Manufacture of field effect transistor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH04116938A (en) |
| KR (1) | KR100217710B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016195287A (en) * | 2009-12-23 | 2016-11-17 | インテル コーポレイション | Improvement in conductivity of group iii-v semiconductor device |
-
1990
- 1990-09-07 JP JP2238097A patent/JPH04116938A/en active Pending
-
1991
- 1991-09-06 KR KR1019910015541A patent/KR100217710B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016195287A (en) * | 2009-12-23 | 2016-11-17 | インテル コーポレイション | Improvement in conductivity of group iii-v semiconductor device |
| US9899505B2 (en) | 2009-12-23 | 2018-02-20 | Intel Corporation | Conductivity improvements for III-V semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| KR920007237A (en) | 1992-04-28 |
| KR100217710B1 (en) | 1999-09-01 |
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