JPH0410217B2 - - Google Patents
Info
- Publication number
- JPH0410217B2 JPH0410217B2 JP57228716A JP22871682A JPH0410217B2 JP H0410217 B2 JPH0410217 B2 JP H0410217B2 JP 57228716 A JP57228716 A JP 57228716A JP 22871682 A JP22871682 A JP 22871682A JP H0410217 B2 JPH0410217 B2 JP H0410217B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- layer
- metal layer
- wiring metal
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
- 238000005224 laser annealing Methods 0.000 description 7
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は半導体装置の製造方法に係り、特にレ
ーザアニール等の熱処理方法を用いてアルミニウ
ムの如き配線金属層のステツプカバーレツジの改
善を行なう半導体装置の製造方法に関する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to improving the step coverage of a wiring metal layer such as aluminum using a heat treatment method such as laser annealing. The present invention relates to a method for manufacturing a semiconductor device.
(2) 技術の背景
近年、LSI技術は著しく発展している。これは
例えば微細加工技術の進歩と共にゲート当りの占
有面積の少ない、工程が簡単なMOS型半導体装
置がLSI化に適しておりこの発展に大きな貢献を
なしている。(2) Technology background LSI technology has developed significantly in recent years. For example, with advances in microfabrication technology, MOS type semiconductor devices, which occupy a small area per gate and are easy to process, are suitable for LSI implementation, making a major contribution to this development.
係るMOS型半導体装置の高密度化に際して例
えばその寸法がホトレジスト工程に用いる露光光
源の波長に近づくにつれ光よりも短い波長を有す
る電子ビーム或いはＸ線等による集積回路のパタ
ーン形成及び転写の方式が種々開発されている。
このため加工技術にも各種微細化技術の開発要請
がおきている。 When increasing the density of such MOS type semiconductor devices, for example, as the dimensions of the device approach the wavelength of the exposure light source used in the photoresist process, various methods of pattern formation and transfer of integrated circuits using electron beams or X-rays having a shorter wavelength than light have become available. being developed.
For this reason, there is a demand for the development of various miniaturization technologies in processing technology.
(3) 従来技術と問題点
半導体基板上に絶縁層を形成してこの絶縁層に
コンタクトホールをあけ、表面にアルミニウム配
線を行う際に、コンタクトホールの近傍における
アルミニウム配線の段部におけるステツプカバレ
ツジを改善し、微細化加工技術を進展させるため
に、レーザーアニールの適用が考えられている。(3) Prior art and problems When an insulating layer is formed on a semiconductor substrate, a contact hole is made in this insulating layer, and an aluminum wiring is formed on the surface, step coverage of the stepped portion of the aluminum wiring near the contact hole is difficult. The application of laser annealing is being considered to improve this and advance microfabrication technology.
係るレーザーアニールは、アルミニウムへ直接
レーザ照射しても吸収率が低いため、アルミニウ
ム配線のパターニングが終了した後で、表面全体
にPSG（リンシリケートガラス）等の絶縁膜を形
成しこのPSGの表面からレーザを照射し、アル
ミニウム配線層を若干溶解させコンタクトホール
近傍においてアルミニウム配線の段部を緩かにす
ることによりステツプカバレツジを向上させるも
のである。 In such laser annealing, since the absorption rate is low even if the laser is irradiated directly onto aluminum, after the patterning of the aluminum wiring is completed, an insulating film such as PSG (phosphosilicate glass) is formed on the entire surface, and from the surface of this PSG. The step coverage is improved by irradiating a laser to slightly melt the aluminum wiring layer and making the stepped portion of the aluminum wiring loose in the vicinity of the contact hole.
しかしながら、従来のレーザ照射は、全面に形
成されたPSG層の上からなされるために、アル
ミニウム配線層以外の部分も加熱し、これによつ
て半導体基板に形成された半導体素子の例えば拡
散深さなどに影響を与えてしまい、半導体素子の
特性を劣化させしまうという欠点があつた。 However, since conventional laser irradiation is performed from above the PSG layer formed on the entire surface, parts other than the aluminum wiring layer are also heated, thereby increasing the diffusion depth of semiconductor elements formed on the semiconductor substrate. This has the disadvantage that it affects the characteristics of the semiconductor element and deteriorates the characteristics of the semiconductor element.
また、レーザアニールによる加熱が半導体素子
に影響を及ぼさないようにするため、全面に形成
される絶縁膜を予め厚く形成すると、半導体装置
の微細化には適さなくなつてしまう。 Moreover, if the insulating film formed over the entire surface is formed thick in advance in order to prevent the heating by laser annealing from affecting the semiconductor element, it becomes unsuitable for miniaturization of the semiconductor device.
４ 発明の目的
本発明の目的は上記従来の欠点に鑑み全面に
Al等の金属配線層を形成した状態でその上の絶
縁膜を所要の金属配線のパターンに形成して、上
方からレーザアニールすることによつて、絶縁膜
により形成された配線パターン部分のみ選択的に
加熱処理を行ない半導体素子の特性を劣化させる
ことなく段部でのカバーレツジの改善を行う半導
体装置の製造方法を提供することにある。4. Purpose of the invention The purpose of the present invention is to completely solve the above-mentioned drawbacks of the conventional technology.
After forming a metal wiring layer such as Al, an insulating film on top of it is formed into the desired metal wiring pattern, and by laser annealing from above, only the wiring pattern portion formed by the insulating film can be selectively removed. An object of the present invention is to provide a method for manufacturing a semiconductor device that improves coverage at a stepped portion without deteriorating the characteristics of a semiconductor element by performing heat treatment.
(5) 発明の構成
そして、この目的は本発明によれば段部を有す
る半導体基板表面上に配線金属層を形成し、該配
線金属層の上に所望の配線金属層パターンと同一
パターンの絶縁膜を形成した後、その全面にわた
つてレーザ照射することで前記絶縁膜下の配線金
属層のみに熱処理を加え、その後、前記絶縁膜を
マスクとして前記配線金属層を選択的にエツチン
グ除去して前記配線金属層パターンだけを残すこ
とを特徴とする半導体装置の製造方法を提供する
ことによつて達成される。(5) Structure of the Invention According to the present invention, the object is to form a wiring metal layer on the surface of a semiconductor substrate having a stepped portion, and to form an insulating layer on the wiring metal layer in the same pattern as a desired wiring metal layer pattern. After forming the film, heat treatment is applied only to the wiring metal layer under the insulating film by irradiating the entire surface with a laser, and then selectively etching away the wiring metal layer using the insulating film as a mask. This is achieved by providing a method for manufacturing a semiconductor device characterized in that only the wiring metal layer pattern is left.
(6) 発明の実施例
次に、本発明の一実施例について図面を参照し
ながら説明する。(6) Embodiment of the Invention Next, an embodiment of the present invention will be described with reference to the drawings.
第１図ａ乃至ｃは、本発明の製造工程を示す概
略的断面図である。 FIGS. 1a to 1c are schematic cross-sectional views showing the manufacturing process of the present invention.
シリコン基板１上に所定のパターニングにてコ
ンタクトホール２を有する絶縁層例えばSiO2層
３を略1μｍ厚形成し、更にAl配線を行うためAl
層４を全面に亘り略1μｍ厚形成するとAl層４は
コンタクトホール２の近傍に段部５を有する。
（同図ａ）次に、Al層４に絶縁膜６例えばPSG膜
若しくはSiO2等を2000〓程度の厚さに被着し、
形成すべき所定のアルミニウム配線パターンと同
一パターンを有するようにパターニングする。
（同図ｂ）
更に、例えばCO2レーザにより全面に亘つて走
査を行い、すなわちレーザアニールの熱処理を行
う。（同図ｃ）尚、第１図ａ〜ｃにおいて、シリ
コン基板１に形成される半導体素子は図示を省略
してある。レーザ光線照射時は、パターニングさ
れた絶縁膜６を介してのみAl層４が昇温され、
従つてAl層４の段部５も加熱され、若干溶解す
るのでそのステツプカバーレツジは第１図ｃに示
すように改善されてくる。また、例えば段部以外
の部分のように絶縁膜６のパターンが形成されて
ない領域では、Al層４がむき出しの状態で残つ
ているためレーザ照射を受けても全面的に反射さ
れて、シリコン基板１に形成された半導体素子を
加熱しない。 An insulating layer, for example, a SiO 2 layer 3 having a contact hole 2 is formed approximately 1 μm thick on a silicon substrate 1 by predetermined patterning, and an Al layer 3 is further formed in order to perform Al wiring.
When the layer 4 is formed to have a thickness of approximately 1 μm over the entire surface, the Al layer 4 has a stepped portion 5 near the contact hole 2.
(Figure a) Next, an insulating film 6 such as a PSG film or SiO 2 is deposited on the Al layer 4 to a thickness of about 2000 mm.
Patterning is performed to have the same pattern as a predetermined aluminum wiring pattern to be formed.
(Figure b) Furthermore, the entire surface is scanned using, for example, a CO 2 laser, that is, a heat treatment of laser annealing is performed. (FIG. 1C) Note that in FIGS. 1A to 1C, the semiconductor elements formed on the silicon substrate 1 are not shown. During laser beam irradiation, the temperature of the Al layer 4 is increased only through the patterned insulating film 6,
Therefore, the step portion 5 of the Al layer 4 is also heated and slightly melted, so that the step coverage is improved as shown in FIG. 1c. Furthermore, in areas where the pattern of the insulating film 6 is not formed, such as areas other than the stepped portions, the Al layer 4 remains exposed, so even if the laser is irradiated, it will be completely reflected and the silicon The semiconductor element formed on the substrate 1 is not heated.
次に、Al層４を三塩化硼素（BCl3）等を用い
て絶縁膜６をマスクとし選択的にドライエツチン
グして、アルミニウム配線パターンだけを残す。
そして、表面全面に保護用のカバーPSGを形成
する。 Next, the Al layer 4 is selectively dry-etched using boron trichloride (BCl 3 ) or the like using the insulating film 6 as a mask, leaving only the aluminum wiring pattern.
Then, a protective cover PSG is formed over the entire surface.
(7) 発明の効果
以上述べて来たように、本発明を用いればAl
層を全面に亘つて形成して所定の領域にのみ絶縁
膜を設けてレーザアニール等の熱処理を行うた
め、熱が基板に達することが少なく従つて半導体
素子の拡散深さ等に与えるダメージが阻止できる
効果を有する。(7) Effects of the invention As stated above, if the present invention is used, Al
Since the layer is formed over the entire surface and the insulating film is provided only in designated areas, heat treatment such as laser annealing is performed, so less heat reaches the substrate, thus preventing damage to the diffusion depth of the semiconductor element, etc. It has the effect of
また、本発明を用いると、Al層と絶縁層との
エツチング選択性が大なるため、絶縁膜及び絶縁
膜をパターニングするレジストが薄くてすみ微細
化に適した効果を有する。 Further, when the present invention is used, the etching selectivity between the Al layer and the insulating layer is increased, so that the insulating film and the resist for patterning the insulating film can be made thinner, which is suitable for miniaturization.
第１図は、本発明を用いた半導体装置の製造方
法を説明する概略的工程断面図である。
１……シリコン基板、２……コンタクトホー
ル、３……絶縁膜、４……アルミニウム層、５…
…段部、６……絶縁膜。
FIG. 1 is a schematic process cross-sectional view illustrating a method of manufacturing a semiconductor device using the present invention. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...Contact hole, 3...Insulating film, 4...Aluminum layer, 5...
...Stepped portion, 6...Insulating film.
Claims (1)
を形成し、該配線金属層の上に所望の配線金属層
パターンと同一パターンの絶縁膜を形成した後、
その全面にわたつてレーザ照射することで前記絶
縁膜下の配線金属層のみに熱処理を加え、その
後、前記絶縁膜をマスクとして前記配線金属層を
選択的にエツチング除去して前記配線金属層パタ
ーンだけを残すことを特徴とする半導体装置の製
造方法。1. After forming a wiring metal layer on the surface of a semiconductor substrate having a stepped portion and forming an insulating film in the same pattern as the desired wiring metal layer pattern on the wiring metal layer,
By irradiating the entire surface with a laser, heat treatment is applied only to the wiring metal layer under the insulating film, and then, using the insulating film as a mask, the wiring metal layer is selectively etched away to remove only the wiring metal layer pattern. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22871682A JPS59121923A (en) | 1982-12-28 | 1982-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22871682A JPS59121923A (en) | 1982-12-28 | 1982-12-28 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59121923A JPS59121923A (en) | 1984-07-14 |
| JPH0410217B2 true JPH0410217B2 (en) | 1992-02-24 |
Family
ID=16880690
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22871682A Granted JPS59121923A (en) | 1982-12-28 | 1982-12-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59121923A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4674176A (en) * | 1985-06-24 | 1987-06-23 | The United States Of America As Represented By The United States Department Of Energy | Planarization of metal films for multilevel interconnects by pulsed laser heating |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797647A (en) * | 1980-12-10 | 1982-06-17 | Toshiba Corp | Forming of electrode wiring in semiconductor device |
| JPS57210624A (en) * | 1981-02-09 | 1982-12-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1982
- 1982-12-28 JP JP22871682A patent/JPS59121923A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797647A (en) * | 1980-12-10 | 1982-06-17 | Toshiba Corp | Forming of electrode wiring in semiconductor device |
| JPS57210624A (en) * | 1981-02-09 | 1982-12-24 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59121923A (en) | 1984-07-14 |
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