JPH0396075U - - Google Patents

Info

Publication number
JPH0396075U
JPH0396075U JP470190U JP470190U JPH0396075U JP H0396075 U JPH0396075 U JP H0396075U JP 470190 U JP470190 U JP 470190U JP 470190 U JP470190 U JP 470190U JP H0396075 U JPH0396075 U JP H0396075U
Authority
JP
Japan
Prior art keywords
integrated circuit
surface pattern
multilayer printed
back surface
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP470190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP470190U priority Critical patent/JPH0396075U/ja
Publication of JPH0396075U publication Critical patent/JPH0396075U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案の一実施例を示す断面図、第
2図は従来例を示す断面図である。 1……集積回路、2……集積回路ハンダ付け部
分、3……部品面パターン、4……セラミツク基
板、5……筺体、6……固定金具、7……プリン
ト基板、8……導体孔、9……裏面パターン、1
0……内層パターン。
FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional example. DESCRIPTION OF SYMBOLS 1... Integrated circuit, 2... Integrated circuit soldering part, 3... Component surface pattern, 4... Ceramic board, 5... Housing, 6... Fixing metal fittings, 7... Printed circuit board, 8... Conductor hole , 9... Back pattern, 1
0...Inner layer pattern.

Claims (1)

【実用新案登録請求の範囲】 1 集積回路と、前記集積回路を搭載する多層プ
リント基板と、前記多層プリント基板の部品面パ
ターンと裏面パターンに接続する導体孔とを含み
、前記集積回路が前記部品面パターンに実装され
、前記集積回路より発生する熱が前記導体孔を通
し前記多層プリント基板の内層パターン及び前記
裏面パターンから放熱されることを特徴とする集
積回路放熱実装構造。 2 前記導体孔は前記部品面パターンと前記裏面
パターンとの間に複数本設けられている実用新案
登録請求の範囲第1項記載の集積回路放熱実装構
造。
[Claims for Utility Model Registration] 1. The integrated circuit includes an integrated circuit, a multilayer printed circuit board on which the integrated circuit is mounted, and conductor holes connected to a component surface pattern and a back surface pattern of the multilayer printed circuit board, 1. An integrated circuit heat dissipation mounting structure, characterized in that the integrated circuit is mounted on a surface pattern, and heat generated by the integrated circuit is radiated from the inner layer pattern and the back surface pattern of the multilayer printed circuit board through the conductor hole. 2. The integrated circuit heat dissipation mounting structure according to claim 1, wherein a plurality of the conductor holes are provided between the component surface pattern and the back surface pattern.
JP470190U 1990-01-22 1990-01-22 Pending JPH0396075U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP470190U JPH0396075U (en) 1990-01-22 1990-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP470190U JPH0396075U (en) 1990-01-22 1990-01-22

Publications (1)

Publication Number Publication Date
JPH0396075U true JPH0396075U (en) 1991-10-01

Family

ID=31508435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP470190U Pending JPH0396075U (en) 1990-01-22 1990-01-22

Country Status (1)

Country Link
JP (1) JPH0396075U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023556A1 (en) * 1993-03-31 1994-10-13 Fanuc Ltd Multilayer printed board
JPH08148839A (en) * 1994-11-21 1996-06-07 Nippondenso Co Ltd Hybrid integrated circuit device
JP2007036050A (en) * 2005-07-28 2007-02-08 Shin Kobe Electric Mach Co Ltd Process for producing multilayer circuit board
JP2013518443A (en) * 2010-01-26 2013-05-20 クアルコム,インコーポレイテッド Micromachined pillar fins for thermal management

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158297A (en) * 1984-08-29 1986-03-25 沖電気工業株式会社 Multilayer printed circuit board
JPS63314858A (en) * 1987-06-18 1988-12-22 Ibiden Co Ltd Package for surface packaging component

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158297A (en) * 1984-08-29 1986-03-25 沖電気工業株式会社 Multilayer printed circuit board
JPS63314858A (en) * 1987-06-18 1988-12-22 Ibiden Co Ltd Package for surface packaging component

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023556A1 (en) * 1993-03-31 1994-10-13 Fanuc Ltd Multilayer printed board
JPH08148839A (en) * 1994-11-21 1996-06-07 Nippondenso Co Ltd Hybrid integrated circuit device
JP2007036050A (en) * 2005-07-28 2007-02-08 Shin Kobe Electric Mach Co Ltd Process for producing multilayer circuit board
JP2013518443A (en) * 2010-01-26 2013-05-20 クアルコム,インコーポレイテッド Micromachined pillar fins for thermal management
US8877563B2 (en) 2010-01-26 2014-11-04 Qualcomm Incorporated Microfabricated pillar fins for thermal management

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