JPH0395929A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0395929A JPH0395929A JP23313589A JP23313589A JPH0395929A JP H0395929 A JPH0395929 A JP H0395929A JP 23313589 A JP23313589 A JP 23313589A JP 23313589 A JP23313589 A JP 23313589A JP H0395929 A JPH0395929 A JP H0395929A
- Authority
- JP
- Japan
- Prior art keywords
- film
- amorphous silicon
- junction
- passivation film
- covering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 239000012212 insulator Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 10
- 230000007613 environmental effect Effects 0.000 abstract description 3
- 239000000356 contaminant Substances 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の構造に関するものであり、特に表
面安定化処理（バシベーション）に関するものである．
ダイオード、トランジスタ等の半導体装置においては、
外部環境に対して敏感であるので、特にその表面保護処
理（パシベーション）が重要である．これらの保護膜と
はシリコン系酸化物（８１０■等）リンガラス、或いは
窒化膜（８１３Ｎ，）が知られている．又、シリコン酸
化膜（Ｓｉ○２）は膜質の良さからプレナ−面のＰＮ接
合を直接覆い、更に耐温、耐汚染等耐環境面から該Ｓｉ
ｎ２膜上に上記のＳｉ，Ｎいリンガラス或いはポリシリ
コン等を積層することが行われている。然し乍らこれら
の膜は１０００℃前後の高温処理を要するため工程管理
に工数を要し、又、ＰＮ接合特性にしばしば悪影響を及
ぼす重金層汚染を受けることがある．本発明を係る点を
鑑み、Ｓｉ○２膜の長所を 生がし、第２バシペーショ
ン膜として、上記Ｓｉ○２の短所を補うと共に４００℃
以下の低温処理により容易に形或できるアモルファスシ
リコン系絶縁膜（以下ａ−ＳｉＸ）（ＸはＨ，Ｆ，Ｎ，
Ｏ、Ｃの少なくとも１つ以上の原子組成を指す）を設け
て、上記の問題点を解消した半導体装置を提供するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a semiconductor device, and particularly to surface stabilization treatment (vasivation). In semiconductor devices such as diodes and transistors,
Since it is sensitive to the external environment, surface protection treatment (passivation) is particularly important. These protective films are known to be silicon-based oxides (810, etc.), phosphorous glass, or nitride films (813N, etc.). In addition, the silicon oxide film (Si○2) directly covers the PN junction on the planar surface due to its good film quality, and is also suitable for environmental resistance such as temperature resistance and pollution resistance.
The above-mentioned Si, N phosphorus glass, polysilicon, etc. are laminated on the n2 film. However, these films require high-temperature treatment at around 1000°C, which requires a lot of man-hours for process control, and they are also subject to heavy metal layer contamination, which often has an adverse effect on PN junction properties. In view of the points related to the present invention, the advantages of the Si○2 film are utilized, and the second vacillation film is used to compensate for the disadvantages of the Si○2 and to
Amorphous silicon-based insulating film (hereinafter a-SiX) (X is H, F, N,
The present invention provides a semiconductor device which solves the above-mentioned problems by providing an atomic composition of at least one of O and C).
以下図面を参照して説明する．第１図（ａ）（ｂ）及び
（ｃ）は本発明の一実施例構造を示す平面図及び断面図
で、第１図（ａ）はａ−ＳｉＸ膜の形或前の平面図、（
ｂ）はａ−ＳｉＸ膜形成後の平面図、（ｃ）は同（ａ）
図Ａ−Ａ’断面図である．第１図においては、バイボー
ラ型のパワートランジスタの例を示し、１はシリコン半
導体基板、２はベース拡散領域、３はエミッタ拡散領域
、４はＰ−Ｎ接合（Ｊ）を覆うシリコン酸化物（ＳｉＯ
２）、Ｂ及びＥはベース及びエミッタ電極（ＡＭ）、５
はａ−ＳｉＸ膜である．
エミッター電極Ｅの広い部分及びベース電極Ｂの広い部
分に一般にはＡｆｌ線がボンデイングされてて使用され
る．第１図（ａ）の部分４には一般には８１０２等の薄
いパッシベーション膜が施されている．このバッシペー
ション膜は薄いので、その表面にイオン性の汚れが付着
すると膜とＳｉの界面に電子あるいは正孔が誘起され、
半導体の特性を悪くしてしまう。そこでａ−ＳｉＸ膜５
を厚く一つけて表面にイオン性の汚れがついても膜とシ
リコンの界面に誘起される電子あるいは正孔を極端に少
なくして、半導゛チップの組立以降の工程を簡単な汚染
対策のみで行う様にすることができる．具体的には次の
様になる。第１図に示したセルが多数あるウェファ−の
状態でアモルファスシリコン系絶縁層を全面に１００〜
３００℃程度の温度で数ミクロン形成させる。アモルフ
ァスシリコン系絶縁物は一般に知られている方法例えば
シランをマイクロ波ＣＶＤ装置中でプラズマ化して形成
させることが出来る。全面にａ−ＳｉＸを形戒後、通常
の写真技術とエッチング技術により前述のボンデイング
ランド上のａ−ＳｉＸのみを除去する、第１図（ｂ）及
び（Ｃ）はその平面図と断面を示す，ａ−ＳｉＸは厚い
のでこの上にイオン性の汚染が付着してもシリコン面上
に形成されているＰＮ接合の特性は殆んど影響を受ける
ことがない。This will be explained below with reference to the drawings. FIGS. 1(a), 1(b) and 1(c) are a plan view and a sectional view showing the structure of an embodiment of the present invention. FIG.
b) is a plan view after forming the a-SiX film, (c) is the same as (a)
It is a sectional view taken along the line A-A'. FIG. 1 shows an example of a bipolar type power transistor, where 1 is a silicon semiconductor substrate, 2 is a base diffusion region, 3 is an emitter diffusion region, and 4 is a silicon oxide (SiO
2), B and E are base and emitter electrodes (AM), 5
is an a-SiX film. Generally, Afl wires are bonded to the wide part of the emitter electrode E and the wide part of the base electrode B. Generally, a thin passivation film such as 8102 is applied to portion 4 in FIG. 1(a). This bacsipation film is thin, so when ionic dirt adheres to its surface, electrons or holes are induced at the interface between the film and Si.
It deteriorates the characteristics of semiconductors. Therefore, a-SiX film 5
Even if the surface is covered with ionic contaminants, the number of electrons or holes induced at the interface between the film and silicon can be extremely reduced, making it possible to perform processes after semiconductor chip assembly with only simple contamination countermeasures. You can do as you like. Specifically, it is as follows. A wafer with a large number of cells as shown in Figure 1 is coated with an amorphous silicon insulating layer on the entire surface.
A few microns are formed at a temperature of about 300°C. The amorphous silicon-based insulator can be formed by a generally known method, for example, by converting silane into plasma in a microwave CVD apparatus. After applying a-SiX to the entire surface, only the a-SiX on the bonding land mentioned above is removed using normal photography and etching techniques. Figures 1(b) and 1(c) show the plan view and cross section. , a-SiX is thick, so even if ionic contamination adheres thereon, the characteristics of the PN junction formed on the silicon surface are hardly affected.
実験によれば５００Ｖ耐圧の半導体の場合、膜厚５μ程
度以上の絶縁物で保護されていれば問題はない．但しバ
ッシベーション膜４がＳｉ表面のＰＮ接合に対してよい
パッシベーション膜であることが一般には必要である．
実験によれば次のように構成することによりａ−ＳｉＸ
ｉｌ［を形成できた。第２図は本発明に適用するａ−Ｓ
ｉＸ形成のためのＣＶＤ装置の概略構或図である。図中
（６）は真空反応室、（７）はマイクロ波（２．４５Ｇ
Ｈ７．）電源、（８）はマイクロ波発振器、（９）はマ
グネトロン、（１０）は矩形導波管、（１１）は石英窓
、（１０″）は内部導波管、（１２）はガス導入パイプ
、（１３）は加熱手段を含む支持台、（１４）はシリコ
ンウェハ、（ｌ５）は真空回転ボンブ、（ｌ６）はブー
スタボンブ、（１７）は拡散ボンブである．上記の装置
により第一表の堆積条件の下にａ−Ｓｉ膜の堆積が行わ
れた。Experiments have shown that in the case of a semiconductor with a withstand voltage of 500V, there is no problem as long as it is protected with an insulator with a thickness of about 5μ or more. However, it is generally necessary that the passivation film 4 is a good passivation film for the PN junction on the Si surface. According to experiments, a-SiX can be produced by the following configuration.
il[ could be formed. Figure 2 shows a-S applied to the present invention.
1 is a schematic diagram of a CVD apparatus for forming iX. In the figure, (6) is a vacuum reaction chamber, and (7) is a microwave (2.45G
H7. ) Power source, (8) is microwave oscillator, (9) is magnetron, (10) is rectangular waveguide, (11) is quartz window, (10″) is internal waveguide, (12) is gas introduction pipe , (13) is a support table including a heating means, (14) is a silicon wafer, (l5) is a vacuum rotary bomb, (l6) is a booster bomb, and (17) is a diffusion bomb. The a-Si film was deposited under the following deposition conditions.
く第一表〉
又、上記の条件の他、導入ガス中に水素（Ｆ｛）、フッ
素（Ｆ）、窒素（Ｎ）、炭素（Ｃ）、酸素（Ｏ）等の１
つ又は複数を同時に導入することにより、光感度を持た
ない、絶縁物として更に優れたａ−ＳｉＸ膜（例ａ−Ｓ
ｉ Ｈ， ａ−Ｓ ｉ ＦＨ、ａ−Ｓ ｉ． ＮＨ％
ａ−Ｓ ｉ ＣＨ， ａ−Ｓ ｉ ＯＨ，ａ−Ｓｉ○Ｎ
Ｈ）を得ることができる。Table 1> In addition to the above conditions, hydrogen (F{), fluorine (F), nitrogen (N), carbon (C), oxygen (O), etc.
By introducing one or more at the same time, an a-SiX film that has no photosensitivity and is even better as an insulator (e.g. a-SiX
i H, a-S i FH, a-S i. NH%
a-S i CH, a-S i OH, a-Si○N
H) can be obtained.
以上は実施の１例であり、具体的な実施法は多数考える
ことが出来る。半導体バッシベーションの専門家であれ
ば第一表に示したアモルファスシリコン系絶縁物は半導
体のバッシベーション膜として極めてすぐれていること
を理解することが出来る。The above is one example of implementation, and many specific implementation methods can be considered. Experts in semiconductor passivation will understand that the amorphous silicon-based insulators shown in Table 1 are extremely excellent as semiconductor passivation films.
以上のように本発明によれば低温処理により容易に第二
バシベーション膜が形成できるので製造工程が簡易であ
り、しかも耐湿特性等の耐環境面から第１パシベーショ
ン膜を保護できる等高信頼度半導体装置用としてその効
果は大きい．図中ｌはシリコン半導体基板、２はペース
領域３はエミッタ領域、４はシリコン酸化膜（ＳｉＯｚ
）、５はアモルファスシリコン系絶縁（ａ−ＳｉＸ）膜
、Ｂばベース電極、Ｅはエミッタ電極、ＪはＰＮ接合で
ある。As described above, according to the present invention, the second passivation film can be easily formed by low-temperature treatment, so the manufacturing process is simple, and the first passivation film can be protected from environmental resistance such as moisture resistance, resulting in high reliability. This is highly effective for semiconductor devices. In the figure, l is a silicon semiconductor substrate, 2 is a space region 3 is an emitter region, and 4 is a silicon oxide film (SiOz
), 5 is an amorphous silicon-based insulating (a-SiX) film, B is a base electrode, E is an emitter electrode, and J is a PN junction.
Claims (1)
導体装置において、前記ＰＮ接合を覆うシリコン酸化物
と、前記シリコン酸化物の少なくとも一部に接する４０
０℃以下の基板温度で形成したアモルファスシリコン系
絶縁物の第２層を備えたことを特徴とする半導体装置。In a semiconductor device in which at least one or more PN junctions are exposed on the surface, a silicon oxide covering the PN junction and a silicon oxide layer contacting at least a portion of the silicon oxide
A semiconductor device comprising a second layer of an amorphous silicon-based insulator formed at a substrate temperature of 0° C. or lower.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23313589A JPH0395929A (en) | 1989-09-08 | 1989-09-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23313589A JPH0395929A (en) | 1989-09-08 | 1989-09-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0395929A true JPH0395929A (en) | 1991-04-22 |
Family
ID=16950284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23313589A Pending JPH0395929A (en) | 1989-09-08 | 1989-09-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0395929A (en) |
-
1989
- 1989-09-08 JP JP23313589A patent/JPH0395929A/en active Pending
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