JPS62115868A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62115868A JPS62115868A JP25691985A JP25691985A JPS62115868A JP S62115868 A JPS62115868 A JP S62115868A JP 25691985 A JP25691985 A JP 25691985A JP 25691985 A JP25691985 A JP 25691985A JP S62115868 A JPS62115868 A JP S62115868A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon
- impurity
- silicide
- selectively
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は非晶質あるいは多結晶シリコンを主成分とする
薄膜を用いた半導体装置の製造方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a thin film mainly composed of amorphous or polycrystalline silicon.
従来の技術
従来、非単結晶シリコンを主成分とする薄膜を用いた半
導体装置、具体的にはダイオード、トランジスタ等で良
好なオーミック接触を得るために第2図に示すような構
造が必要であった。即ち非単結晶シリコン11と電極層
12の間に非単結晶シリコンのn+層(又はp+層)の
中間層を形成する必要であった。より具体的に薄膜電界
効果トランジスタを用いた例で説明する。Conventional Technology Conventionally, semiconductor devices using thin films mainly composed of non-monocrystalline silicon, specifically diodes, transistors, etc., have required a structure as shown in Figure 2 to obtain good ohmic contact. Ta. That is, it was necessary to form an intermediate layer of n+ layer (or p+ layer) of non-single crystal silicon between non-single crystal silicon 11 and electrode layer 12. A more specific explanation will be given using an example using a thin film field effect transistor.
第3図は非単結晶シリコンを用いたTPTの工程断面図
である。まず、第3図乙に示すように絶縁性基板例えば
ガラス板21上にゲート電極となる第1の金属層2また
とえばNiCrを選択的に被着形成する。次いで全面に
ゲート絶縁層23、たとえばンリコン窒化膜、不純物を
含まない非晶質シリコン層24、そして非晶質シリコン
層24を保護する層25、たとえばシリコン窒化膜を被
着形成する。次に第3図すに示すように保護層25をチ
ャンネル部上のみを選択的に残し島状の層251Lを形
成する。その後、第3図すに示す非晶質シリコン層24
を選択的に除去して島状の非晶質シリコン層24&を形
成する。FIG. 3 is a process cross-sectional view of TPT using non-single crystal silicon. First, as shown in FIG. 3B, a first metal layer 2, such as NiCr, which will become a gate electrode, is selectively deposited on an insulating substrate, such as a glass plate 21. Next, a gate insulating layer 23 such as a silicon nitride film, an amorphous silicon layer 24 containing no impurities, and a layer 25 for protecting the amorphous silicon layer 24, such as a silicon nitride film, are then deposited on the entire surface. Next, as shown in FIG. 3, the protective layer 25 is selectively left only on the channel portion to form an island-shaped layer 251L. After that, the amorphous silicon layer 24 shown in FIG.
is selectively removed to form an island-shaped amorphous silicon layer 24&.
次に第3図Cに示すように不純物を含む非晶質シリコン
層26、例えばリンをドープしたn型非晶質7977層
を被着形成する。不純物としてリンをドープした非晶質
シリコンをもちいた場合電気伝導度は1o−2〜1o−
5(Ω/口)−1必要である。さらに第3図では図示し
でいないが第1の金属層22の上のゲート絶縁層23に
開口部を形成して第1の金属層22を一部露出する。こ
の工程の後、第2のソースドレーンとなる金属層27を
被着形成する。Next, as shown in FIG. 3C, an amorphous silicon layer 26 containing impurities, for example, an n-type amorphous 7977 layer doped with phosphorus, is deposited. When using amorphous silicon doped with phosphorus as an impurity, the electrical conductivity is 1o-2 to 1o-
5(Ω/mouth)-1 is required. Further, although not shown in FIG. 3, an opening is formed in the gate insulating layer 23 above the first metal layer 22 to partially expose the first metal layer 22. After this step, a metal layer 27 that will become the second source/drain is deposited.
次に第3図dのようにオフセットゲート構造にならぬよ
うに第1の金属層22と一部重なり合うように第2の金
属層27及び不純物を含む非晶質シリコン層26を選択
的にエツチングして1対のソース・ドレーン配線27?
L、27bが形成される。このエツチングの際、チャン
ネル部上の保護層25aによって半導体活性層24&は
エツチングされることなく、チャンネル部上の不純物を
含む非晶質シリコン26は完全に除去される。このよう
にしてTPTが完成する。Next, as shown in FIG. 3d, the second metal layer 27 and the amorphous silicon layer 26 containing impurities are selectively etched so as to partially overlap the first metal layer 22 to avoid an offset gate structure. And a pair of source/drain wiring 27?
L, 27b is formed. During this etching, the semiconductor active layer 24& is not etched by the protective layer 25a on the channel portion, and the amorphous silicon 26 containing impurities on the channel portion is completely removed. In this way, TPT is completed.
ここで半導体の活性領域とソース・ドレーン電極とのオ
ーミック接触が良好でチャンネル幅Wとチャンネル長り
との比W / Lが1のTPTではゲート電圧VG=1
2 V 、 トV−7電圧”/、=12V。Here, in a TPT where the ohmic contact between the semiconductor active region and the source/drain electrode is good and the ratio of channel width W to channel length W/L is 1, the gate voltage VG=1.
2 V, V-7 voltage/, = 12V.
ソース接地の条件で3 X 10−6A程度の電流が流
れる。ところが半導体活性領域なる層24aとの間にオ
ーミック接触になるように設けられたはずの層26Δの
電気伝導度が1(r6〜to−’(Ω/口)−1と悪い
TPTでは、前記と同じ条件(Vc−”Vp=12v、
ソース接地)下でI X 10−8A以下の電流しか流
れず良好なオーミック接触が得られない。A current of approximately 3 x 10-6 A flows under the condition that the source is grounded. However, in TPT, where the electrical conductivity of the layer 26Δ, which is supposed to be provided in ohmic contact with the semiconductor active region layer 24a, is 1 (r6~to-'(Ω/gate)-1), the above-mentioned problem occurs. Same conditions (Vc-”Vp=12v,
When the source is grounded, only a current of less than I x 10-8 A flows, and good ohmic contact cannot be obtained.
発明が解決しようとする問題点
非単結晶シリコンを主成分とする半導体活性領域と良好
なオーミック接触を示す不純物を含む、非単結晶シリコ
/層25&は省くことができず工程が増加した。Problems to be Solved by the Invention The non-single-crystal silicon/layer 25&, which contains impurities that exhibit good ohmic contact with the semiconductor active region mainly composed of non-single-crystal silicon, cannot be omitted, resulting in an increase in the number of steps.
問題点を解決する為の手段
本発明は非単結晶シリコンを主成分とする半導体層と接
触するオーミック層として不純物元素を含むシリサイド
を形成することを特徴とする半導体装置の製造方法を提
供する。Means for Solving the Problems The present invention provides a method for manufacturing a semiconductor device characterized by forming a silicide containing an impurity element as an ohmic layer in contact with a semiconductor layer mainly composed of non-single crystal silicon.
作用
第1図に示すように、シリコンを主成分とする非単結晶
半導体たとえば非単結晶シリコン1上に不純物を含むシ
リサイド2を形成するあるいは不純物を含むノリサイド
上2に非単結晶シリコン1を形成すると、基板温度にも
よるが非単結晶シリコン中にシリサイド中の不純物が拡
散しn層(あるいはp層)が形成され、オーミック接触
となる。As shown in FIG. 1, a non-single-crystal semiconductor whose main component is silicon, for example, a silicide 2 containing impurities is formed on a non-single-crystal silicon 1, or a non-single-crystal silicon 1 is formed on a silicide 2 containing an impurity. Then, depending on the substrate temperature, impurities in the silicide diffuse into the non-single crystal silicon to form an n layer (or p layer), resulting in ohmic contact.
さらに熱処理の工程を追加することによりさらに良いオ
ーミック接触が得られる。Even better ohmic contact can be obtained by adding a heat treatment step.
実施例
本実施例は本発明半導体装置の製造方法を非晶質/リコ
ンTPTに適用した例である。第4図に工程を示す断面
図を示す。なお同一機能の各部については同一番号を付
す。Embodiment This embodiment is an example in which the method for manufacturing a semiconductor device of the present invention is applied to an amorphous/licon TPT. FIG. 4 shows a sectional view showing the process. The parts with the same function are given the same number.
1ず、第4図乙に示すように絶縁性基板、例えばガラス
基板21上にゲート電極となる第1の金属層2またとえ
ばOrを選択的に被着形成する。1. First, as shown in FIG. 4B, a first metal layer 2, such as Or, which will become a gate electrode, is selectively deposited on an insulating substrate, such as a glass substrate 21.
次に全面に、たとえば窒化シリコン層よりなる絶縁層2
3、不純物たとえば■族、■族を含まない非m結晶シリ
コン層としてたとえば非晶質水素化シリコン層24、さ
らに層24を保護する層たとえばノリコン窒化膜層25
を被着する。これらの被着方法は、ゲート電極としてC
rを形成するにはDCスパッタ法により形成できる。ゲ
ート絶縁層23、不純物を含まない半導体層24及び保
護層26は7ラン系のガスのグロー放電分解により得ら
れる。ゲート絶縁膜及び保護層として窒化シリコンを形
成する場合にはシラン(SiH4)、アンモニア(NH
3)、窒素(N2)を混合し放電分解すれば得られる。Next, an insulating layer 2 made of, for example, a silicon nitride layer is applied to the entire surface.
3. For example, an amorphous hydrogenated silicon layer 24 as a non-m-crystalline silicon layer that does not contain impurities such as group Ⅰ or group ①, and a layer that protects the layer 24, such as a noricon nitride film layer 25.
be coated with. These deposition methods use C as the gate electrode.
r can be formed by DC sputtering. The gate insulating layer 23, the impurity-free semiconductor layer 24, and the protective layer 26 are obtained by glow discharge decomposition of a 7 run gas. When forming silicon nitride as the gate insulating film and protective layer, silane (SiH4), ammonia (NH
3), obtained by mixing nitrogen (N2) and subjecting it to discharge decomposition.
その後、第4図すに示すごとく保護層25及び非晶質シ
リコン層24を選択的に除去し、層24a、25&より
なる島領域を形成する。さらに第4図では図示していな
いが第1の金属層22上のゲート絶縁層23に開口部を
形成した後に第4図Cに示すようにオフセットゲート構
造にならぬよう第1の金属層2と一部重なり合った不純
物を含むシリサイド層よりなる1対のソース、ドレーン
電%28,29が選択的に被着形成される。このソリサ
イドはMoSi□・/リサイドをターゲントとし、′D
Cマグネトロンスハノタ装置で、ArとPH,をそれぞ
れ3 X 10−’ Torr導入してパワー200W
で形成した。基板温度は室温から250’Cで形成した
。さらにN2雰囲気で250〜350°C30分間以上
熱処理をするこトに、l: り、W/Lが1でゲート電
圧v、=12v。Thereafter, as shown in FIG. 4, the protective layer 25 and the amorphous silicon layer 24 are selectively removed to form an island region consisting of the layers 24a, 25&. Furthermore, although not shown in FIG. 4, after forming an opening in the gate insulating layer 23 on the first metal layer 22, the first metal layer 2 is removed to avoid an offset gate structure as shown in FIG. 4C. A pair of source and drain electric currents 28 and 29 made of silicide layers containing impurities are selectively deposited and partially overlapped with each other. This solicide uses MoSi□・/recide as the target, and 'D
Using a C magnetron Hanota device, Ar and PH were introduced at 3 x 10-' Torr each to generate a power of 200 W.
It was formed with. The substrate temperature was from room temperature to 250'C. Further, heat treatment was performed at 250 to 350°C for 30 minutes or more in an N2 atmosphere, so that the gate voltage v was 12v at W/L of 1.
ドレーン電圧VD=12v、ソース接地の条件で2・6
×10−6人の電流が得られ、不純物を含むn型の非晶
質シリコン層を介在させた場合と同等の値が得られた。Drain voltage VD = 12v, 2.6 with source common condition
A current of ×10 −6 was obtained, and a value equivalent to that obtained when an n-type amorphous silicon layer containing impurities was interposed.
上記実施例では非晶質シリコンを用いたTPTのソース
ドレーン部のオーミック接触を得る例を示したが、半導
体デバイス、例えばダイオード。In the above embodiment, an example of obtaining ohmic contact between the source and drain portions of a TPT using amorphous silicon was shown, but it is also applicable to semiconductor devices such as diodes.
太陽電池、電子写真感光体、イメージセンナ等において
もオーミック接触を必要とするものに適用できる。さら
に非晶質シリコンのみならず、多結晶シリコンにおいて
も適用できるのはいうまでもない。It can also be applied to solar cells, electrophotographic photoreceptors, image sensors, etc. that require ohmic contact. Furthermore, it goes without saying that the present invention can be applied not only to amorphous silicon but also to polycrystalline silicon.
発明の効果
従来、多結晶や非晶質の非単結晶シリコンを主成分とす
る半導体層と金属とのオーミック接触を得るためには、
不純物を含むn型(又はp型の)非単結晶シリコンを介
在させることが必要であったが金属電極として不純物を
含むシリサイドを用いることにより容易にオーミック接
触が得られ、介在層を被着形成する工程を減らすことが
できた。Effects of the Invention Conventionally, in order to obtain ohmic contact between a semiconductor layer mainly composed of polycrystalline or amorphous non-single crystal silicon and a metal,
Although it was necessary to interpose n-type (or p-type) non-single crystal silicon containing impurities, ohmic contact can be easily obtained by using silicide containing impurities as the metal electrode, and the intervening layer can be formed by adhesion. We were able to reduce the number of steps required.
第1図は本発明に、かかる構造の断面図、第2図は従来
のオーミック接触を得る構成の断面図、第3図は従来の
TPTの工程断面図、第4図は本発明の製造方法を用い
たTPTの工程断面図である。
1・・・・・シリコンを主成分とする非単結晶半導体、
2・・・・・・不純物を含むシリサイド、21 ・・・
・ガラス基板、22・・・・・・ゲート電極、23・・
・・・・ゲート絶縁物、24&・・・・・非単結晶半導
体、26・−・・・・不純物を含む非単結晶半導体。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名お3
図
(α)
zz(C)
q
第3図
(d−)
??
第4図
(ユ2FIG. 1 is a sectional view of a structure according to the present invention, FIG. 2 is a sectional view of a conventional structure for obtaining ohmic contact, FIG. 3 is a sectional view of a conventional TPT process, and FIG. 4 is a manufacturing method of the present invention. It is a process sectional view of TPT using. 1...Non-single crystal semiconductor whose main component is silicon,
2... Silicide containing impurities, 21...
・Glass substrate, 22...Gate electrode, 23...
. . . Gate insulator, 24 & . . . Non-single crystal semiconductor, 26 . . . Non-single crystal semiconductor containing impurities. Name of agent: Patent attorney Toshio Nakao and 1 other person
Figure (α) zz (C) q Figure 3 (d-)? ? Figure 4 (U2
Claims (1)
ーミック層として、不純物元素を含むシリサイドを形成
することを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising forming a silicide containing an impurity element as an ohmic layer in contact with a semiconductor layer mainly composed of non-single crystal silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25691985A JPS62115868A (en) | 1985-11-15 | 1985-11-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25691985A JPS62115868A (en) | 1985-11-15 | 1985-11-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62115868A true JPS62115868A (en) | 1987-05-27 |
Family
ID=17299198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25691985A Pending JPS62115868A (en) | 1985-11-15 | 1985-11-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62115868A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02188928A (en) * | 1989-01-17 | 1990-07-25 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US5053347A (en) * | 1989-08-03 | 1991-10-01 | Industrial Technology Research Institute | Amorphous silicon thin film transistor with a depletion gate |
US5091337A (en) * | 1987-12-26 | 1992-02-25 | Seikosha Co., Ltd. | Method of manufacturing amorphous-silicon thin-film transistors |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57197860A (en) * | 1981-05-29 | 1982-12-04 | Toshiba Corp | Semiconductor device |
JPS5832010A (en) * | 1981-08-20 | 1983-02-24 | Fujitsu Ltd | Method for forming metal silicide film |
JPS58184182A (en) * | 1982-04-22 | 1983-10-27 | セイコーエプソン株式会社 | Liquid crystal display body apparatus |
JPS61184882A (en) * | 1985-02-12 | 1986-08-18 | Seiko Instr & Electronics Ltd | Thin film transistor |
-
1985
- 1985-11-15 JP JP25691985A patent/JPS62115868A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57197860A (en) * | 1981-05-29 | 1982-12-04 | Toshiba Corp | Semiconductor device |
JPS5832010A (en) * | 1981-08-20 | 1983-02-24 | Fujitsu Ltd | Method for forming metal silicide film |
JPS58184182A (en) * | 1982-04-22 | 1983-10-27 | セイコーエプソン株式会社 | Liquid crystal display body apparatus |
JPS61184882A (en) * | 1985-02-12 | 1986-08-18 | Seiko Instr & Electronics Ltd | Thin film transistor |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5091337A (en) * | 1987-12-26 | 1992-02-25 | Seikosha Co., Ltd. | Method of manufacturing amorphous-silicon thin-film transistors |
JPH02188928A (en) * | 1989-01-17 | 1990-07-25 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
US5053347A (en) * | 1989-08-03 | 1991-10-01 | Industrial Technology Research Institute | Amorphous silicon thin film transistor with a depletion gate |
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