JPH0393947U - - Google Patents
Info
- Publication number
- JPH0393947U JPH0393947U JP291590U JP291590U JPH0393947U JP H0393947 U JPH0393947 U JP H0393947U JP 291590 U JP291590 U JP 291590U JP 291590 U JP291590 U JP 291590U JP H0393947 U JPH0393947 U JP H0393947U
- Authority
- JP
- Japan
- Prior art keywords
- error
- cpu
- emergency
- memory
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Detection And Correction Of Errors (AREA)
- Hardware Redundancy (AREA)
Description
第１図はこの考案の一実施例を示す図、第２図
は従来の実施例を示す図である。
１……ＣＰＵ、２……主メモリ、３……リード
信号、４……データバス、５……アドレスバス、
６……データバス、７……パリテイー符号、８…
…エラー訂正回路、９……ダブルエラー信号、１
０……エラー検出回路、１３……緊急処理メモリ
、１４……緊急データバス、１５……データセレ
クタ。なお、図中、同一符号は同一、又は相当部
分を示す。
FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional embodiment. 1...CPU, 2...Main memory, 3...Read signal, 4...Data bus, 5...Address bus,
6...Data bus, 7...Parity code, 8...
...Error correction circuit, 9...Double error signal, 1
0...Error detection circuit, 13...Emergency processing memory, 14...Emergency data bus, 15...Data selector. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
正用のパリテイー符号付きで記憶する主メモリ、
この主メモリから出力されるプログラムとパリテ
イー符号とからプログラムに誤りがないかを検出
し１ビツトの誤りの場合は訂正してＣＰＵに転送
し２ビツトの誤りの場合はエラーとして検出する
エラー訂正回路、２ビツトの誤りの場合にエラー
訂正回路からのダブルエラー信号を検出してエラ
ー信号を出力するエラー検出回路、エラー検出回
路からのエラー信号を受けてエラー処理用の緊急
命令群をＣＰＵからのリード信号に従つて順次に
ＣＰＵに出力するフアーストイン・フアーストア
ウトメモリで構成される緊急処理メモリ、主メモ
リから出力されたプログラムに誤りがない場合は
エラー訂正回路からのプログラムをＣＰＵに転送
しダブルエラーが発生した場合は緊急処理メモリ
からの緊急命令群をＣＰＵに転送するように切り
換えを行うデータセレクタから構成され、主メモ
リからのプログラムにダブルエラーが検出された
場合、データセレクタで緊急処理メモリに切り換
えて緊急命令群をエラー訂正回路を経由しないで
ＣＰＵに転送し、処理を継続することができるこ
とを特徴とするエラー処理回路。 A CPU that executes calculations, a main memory that stores programs with parity codes for error correction,
An error correction circuit detects whether there is an error in the program from the program output from the main memory and the parity code, and if it is a 1-bit error, it is corrected and transferred to the CPU, and if it is a 2-bit error, it is detected as an error. , an error detection circuit that detects a double error signal from the error correction circuit and outputs an error signal in the case of a 2-bit error, and an error detection circuit that receives the error signal from the error detection circuit and sends a group of emergency instructions for error processing from the CPU. An emergency processing memory consisting of first-in/first-out memory that sequentially outputs to the CPU according to read signals, and if there is no error in the program output from the main memory, the program from the error correction circuit is transferred to the CPU and double It consists of a data selector that switches to transfer emergency instructions from the emergency processing memory to the CPU when an error occurs.If a double error is detected in the program from the main memory, the data selector transfers the emergency instructions from the emergency processing memory to the CPU. An error processing circuit characterized in that it is possible to transfer an emergency command group to a CPU without passing through an error correction circuit by switching to a CPU, and to continue processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP291590U JPH0393947U (en) | 1990-01-17 | 1990-01-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP291590U JPH0393947U (en) | 1990-01-17 | 1990-01-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0393947U true JPH0393947U (en) | 1991-09-25 |
Family
ID=31506760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP291590U Pending JPH0393947U (en) | 1990-01-17 | 1990-01-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0393947U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007319178A (en) * | 2006-05-30 | 2007-12-13 | Sml Ltd | Hair-dressing, beauty or medical washing device and structure for disposing the same |
-
1990
- 1990-01-17 JP JP291590U patent/JPH0393947U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007319178A (en) * | 2006-05-30 | 2007-12-13 | Sml Ltd | Hair-dressing, beauty or medical washing device and structure for disposing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61166653A (en) | Processing system for address conversion error | |
| JPH0393947U (en) | ||
| JPH0397743U (en) | ||
| JPH0397742U (en) | ||
| AU4939990A (en) | Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature | |
| JPH0474342U (en) | ||
| JPH03107748U (en) | ||
| JPS5617417A (en) | Common bus supervisory system | |
| JPH01160547U (en) | ||
| JPS53122340A (en) | Check system for read-in data | |
| JP2888654B2 (en) | Data input control method | |
| JPS5576454A (en) | Announcement system for error detection information | |
| JPS5387642A (en) | Memory retry system | |
| JPS55146682A (en) | Data transfer system | |
| JPH0397747U (en) | ||
| JPS58170099U (en) | memory device | |
| JPH0256662A (en) | Memory protecting system | |
| JPS6476335A (en) | Data processing system | |
| JPH0482728U (en) | ||
| JPH03110542U (en) | ||
| JPS62293439A (en) | Error correcting mechanism | |
| JPS6368049U (en) | ||
| JPS62121648U (en) | ||
| JPS5619596A (en) | Parity error processing system | |
| JPS6239778B2 (en) |