JPH0389717A - Fault detection circuit - Google Patents
Fault detection circuitInfo
- Publication number
- JPH0389717A JPH0389717A JP1226796A JP22679689A JPH0389717A JP H0389717 A JPH0389717 A JP H0389717A JP 1226796 A JP1226796 A JP 1226796A JP 22679689 A JP22679689 A JP 22679689A JP H0389717 A JPH0389717 A JP H0389717A
- Authority
- JP
- Japan
- Prior art keywords
- converters
- converter
- control
- signals
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 title claims description 15
- 230000002238 attenuated effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Testing And Monitoring For Control Systems (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は故障検出回路に関し、特に制御系のＤ／Ａ変換
器の故障を検出する故障検出回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure detection circuit, and more particularly to a failure detection circuit that detects a failure in a D/A converter in a control system.
従来、この種の故障検出回路は、第２図に示すように、
制御部１は、制御部１の制御のもとに動作する被制御機
器３に供給すべき制御信号としてディジタル信号、たと
えば３種類のディジタル信号をＤ／Ａ変換器２−１〜２
−３へ出力する。Conventionally, this type of failure detection circuit, as shown in Figure 2,
The control unit 1 sends digital signals, for example, three types of digital signals, to the D/A converters 2-1 to 2-2 as control signals to be supplied to the controlled equipment 3 operating under the control of the control unit 1.
Output to -3.
Ｄ／Ａ変換器２−１〜２−３はディジタル信号をアナロ
グ信号に変換して、被制御機器６へ出力する。The D/A converters 2-1 to 2-3 convert digital signals into analog signals and output them to the controlled device 6.
一方、故障検出のために、Ｄ／Ａ変換器の出力信号をそ
のままＡ／Ｄ変換器６−１〜６−３にも供給し、再度デ
ィジタル化して制御部１へ入力する。制御部１ではＤ／
Ａ変換器２−１〜２−３へ出力したディジタル信号とＡ
／Ｄ変換器６−１〜６−３の出力信号を比較して故障を
検出していた。On the other hand, for failure detection, the output signals of the D/A converters are also supplied as they are to the A/D converters 6-1 to 6-3, digitized again, and input to the control section 1. In the control section 1, D/
Digital signals output to A converters 2-1 to 2-3 and A
A failure was detected by comparing the output signals of the /D converters 6-1 to 6-3.
上述した従来の制御系の故障検出回路は、制御器から出
力されるディジタル信号のＤ／Ａ変換器の出力信号の正
常性を監視するために、出力信号の数と同数のＡ／Ｄ変
換器を必要とし、回路が複雑化するという欠点がある。The conventional control system failure detection circuit described above uses the same number of A/D converters as the number of output signals in order to monitor the normality of the output signal of the D/A converter of the digital signal output from the controller. The disadvantage is that the circuit is complicated.
本発明の故障検出回路は、ディジタル形式の制御信号を
アナログ化して被制御機器に供給するＤ／Ａ変換器の故
障を検出する故障検出回路において、複数の前記制御信
号をアナログ信号に変換する複数のＤ／Ａ変換器と、前
記複数のＤ／Ａ変換器の出力する複数のアナログ信号を
前記Ｄ／Ａ変換器の数の逆数を減衰比としてそれぞれ減
衰する減衰器と、前記減衰器で減衰したアナログ信号を
加算出力する加算器と、前記加算器で加算した信号をデ
ィジタル信号に変換するＡ／Ｄ変換器と、前記複数の制
御信号を出力するとともにこれら複数の制御信号の制御
値の加算値と前記Ａ／Ｄ変換器の出力値とを比較し前記
Ｄ／Ａ変換器の故障の有無を検出する制御部とを備えて
構成される。The failure detection circuit of the present invention is a failure detection circuit that detects a failure of a D/A converter that converts a digital control signal into an analog signal and supplies it to a controlled device. a D/A converter, an attenuator that attenuates each of the plurality of analog signals output from the plurality of D/A converters using an attenuation ratio of the reciprocal of the number of the D/A converters, and attenuation by the attenuator. an adder that adds and outputs the analog signals added by the adder; an A/D converter that converts the signals added by the adder into digital signals; and an A/D converter that outputs the plurality of control signals and adds control values of the plurality of control signals. and a control unit that compares the output value of the A/D converter with the output value of the A/D converter to detect whether or not there is a failure in the D/A converter.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の構成図である。制御部°１
はマイクロプロセッサ等を使用し、制御信号の発生に必
要な制御演算を行ない、得られた制御信号のディジタル
信号をＤ／Ａ変換器２−１〜２−３へ出力する。Ｄ／Ａ
変換器２−１〜２−３はディジタル信号をアナログ信号
に変換して被制御機器６へ出力すると同時に、減衰器３
へも出力する。FIG. 1 is a block diagram of an embodiment of the present invention. Control part °1
uses a microprocessor or the like to perform control calculations necessary for generating control signals, and outputs the obtained digital signals of the control signals to the D/A converters 2-1 to 2-3. D/A
The converters 2-1 to 2-3 convert the digital signal into an analog signal and output it to the controlled device 6, and at the same time, the attenuator 3
Also output to.
減衰器３は、後述する加算器４の入力範囲を調整するも
のであって、Ｄ／Ａ変換器２−１〜２−３のチャンネル
数３の逆数で表現される減衰比が設定されている。減衰
器３はＤ／Ａ変換器２−１〜２−３の出力信号を上述し
た減衰比に対応させて減衰し、加算器４へ出力する。The attenuator 3 adjusts the input range of the adder 4, which will be described later, and has an attenuation ratio expressed as the reciprocal of the number of channels 3 of the D/A converters 2-1 to 2-3. . The attenuator 3 attenuates the output signals of the D/A converters 2-1 to 2-3 in accordance with the above-mentioned attenuation ratio, and outputs the attenuated signals to the adder 4.
加算器４は減衰器３により減衰したそれぞれの制御信号
を加算してＡ／Ｄ変換器５へ出力する。Adder 4 adds the respective control signals attenuated by attenuator 3 and outputs the result to A/D converter 5 .
Ａ／Ｄ変換器５は加算された複数の制御信号をディジタ
ル信号に変換して制御部ｌへ出力する。The A/D converter 5 converts the added plurality of control signals into digital signals and outputs the digital signals to the control section l.
制御部１はＤ／Ａ変換器２−１〜２−３へ出力した制御
信号の制御値を加算し、これとＡ／Ｄ変換器５からの入
力値とを減衰器３の減衰比の逆数倍して比較する。比較
した結果に予め設定した判定基準値以上の差が生じた場
合はＡ／Ｄ変換器２−１〜２−３の故障と判定する。The control unit 1 adds the control values of the control signals output to the D/A converters 2-1 to 2-3, and adds this and the input value from the A/D converter 5 to the inverse of the attenuation ratio of the attenuator 3. Multiply and compare. If the comparison result shows a difference greater than a preset determination reference value, it is determined that the A/D converters 2-1 to 2-3 are malfunctioning.
以上説明したように本発明は、被制御機器を制御する制
御部のディジタル制御出力をアナログ化するＤ／Ａ変換
器の故障を検出する故障検出回路において、Ｄ／Ａ変換
器の出力をＤ／Ａ変換器の数に反比例する減衰比で減衰
したうえ加算したものを加算し、Ａ／Ｄ変換したものを
制御部で減衰を復元するように増幅してから予め設定し
た判定基準値と比較することにより、故障検出のための
Ｄ／Ａ変換器を大幅に減少するとこができる効果がある
。As explained above, the present invention provides a failure detection circuit that detects a failure of a D/A converter that converts the digital control output of a control unit that controls a controlled device into an analog signal. Attenuate with an attenuation ratio that is inversely proportional to the number of A converters, add the added values, and amplify the A/D converted result to restore the attenuation in the control unit, and then compare it with a preset judgment reference value. This has the effect that the number of D/A converters for failure detection can be significantly reduced.
第１図は本発明の故障検出回路の一実施例の構成図、第
２図は従来の故障検出回路の構成図である。
１・・・制御部、２−１〜２−３・・・Ｄ／Ａ変換器、
３・・・減衰器、４・・・加算器、５・・・Ａ／Ｄ変換
器、６−１〜６−３・・・Ａ／Ｄ変換器。FIG. 1 is a block diagram of an embodiment of the failure detection circuit of the present invention, and FIG. 2 is a block diagram of a conventional failure detection circuit. 1... Control unit, 2-1 to 2-3... D/A converter,
3... Attenuator, 4... Adder, 5... A/D converter, 6-1 to 6-3... A/D converter.
Claims (1)
に供給するＤ／Ａ変換器の故障を検出する故障検出回路
において、複数の前記制御信号をアナログ信号に変換す
る複数のＤ／Ａ変換器と、前記複数のＤ／Ａ変換器の出
力する複数のアナログ信号を前記Ｄ／Ａ変換器の数の逆
数を減衰比としてそれぞれ減衰する減衰器と、前記減衰
器で減衰したアナログ信号を加算出力する加算器と、前
記加算器で加算した信号をディジタル信号に変換するＡ
／Ｄ変換器と、前記複数の制御信号を出力するとともに
これら複数の制御信号の制御値の加算値と前記Ａ／Ｄ変
換器の出力値とを比較し前記Ｄ／Ａ変換器の故障の有無
を検出する制御部とを備えて成ることを特徴とする故障
検出回路。In a failure detection circuit that detects a failure of a D/A converter that converts a digital control signal into an analog signal and supplies it to a controlled device, a plurality of D/A converters that convert the plurality of control signals into analog signals; an attenuator that attenuates each of the plurality of analog signals output from the plurality of D/A converters using an attenuation ratio of the reciprocal of the number of the D/A converters; and an addition that adds and outputs the analog signals attenuated by the attenuator. and A for converting the signal added by the adder into a digital signal.
/D converter, and outputs the plurality of control signals, and compares the sum of the control values of the plurality of control signals and the output value of the A/D converter to determine whether or not there is a failure in the D/A converter. A failure detection circuit comprising: a control section for detecting a failure detection circuit;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1226796A JPH0389717A (en) | 1989-09-01 | 1989-09-01 | Fault detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1226796A JPH0389717A (en) | 1989-09-01 | 1989-09-01 | Fault detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0389717A true JPH0389717A (en) | 1991-04-15 |
Family
ID=16850752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1226796A Pending JPH0389717A (en) | 1989-09-01 | 1989-09-01 | Fault detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0389717A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001211074A (en) * | 1999-11-19 | 2001-08-03 | Abb Power Automation Ag | Apparatus and method for monitoring converter operation |
-
1989
- 1989-09-01 JP JP1226796A patent/JPH0389717A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001211074A (en) * | 1999-11-19 | 2001-08-03 | Abb Power Automation Ag | Apparatus and method for monitoring converter operation |
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