JPH0383351A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPH0383351A
JPH0383351A JP1221214A JP22121489A JPH0383351A JP H0383351 A JPH0383351 A JP H0383351A JP 1221214 A JP1221214 A JP 1221214A JP 22121489 A JP22121489 A JP 22121489A JP H0383351 A JPH0383351 A JP H0383351A
Authority
JP
Japan
Prior art keywords
film
electronic component
chip
pad
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1221214A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP1221214A priority Critical patent/JPH0383351A/en
Publication of JPH0383351A publication Critical patent/JPH0383351A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/01082—Lead [Pb]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To enhance a blocking effect to water which may intrude along the surfaces of leads by a method wherein a multilayer film consisting of a silicon nitride film, a silicon oxynitride film or a silicon carbide film and a diamondlike carbon film is formed on an electronic component, bonding parts and the peripheries of the bonding parts as protective film. CONSTITUTION:An electronic component chip 28 attached on a metal die 35' is coupled with a pad 38' of a stem 35 for coupling a metal pad of this chip, such as an Al pad 38, with an electronic component chip of a lead frame using a conductor 37, such as by a wire bonding of fine gold wires. Moreover, a protective film for deterioration prevention use, in particular a multilayer film 27 consisting of a base film, which consists of a silicon nitride film, a silicon oxy nitride film or a silicon carbide film, and a diamondlike carbon film is applied on the surface of this chip 28, the surface, which is exposed without being subjected to bonding, of the pad 38, the coupling wires 39 and the rear and the side surface of the die 35'. A protective film consisting of the base film like this silicon nitride film and a DLC film thereon is formed by a plasma vapor growth method.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は半導体装置等の電子部品をより小型化し、よ
り高信頼性化する手段を提供することに関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to providing means for making electronic components such as semiconductor devices smaller and more reliable.

「従来の技術」 従来、電子部品チップの保護膜形成用のファイナル・コ
ーティングは、ウェハ・レベルにて行っていた。このた
め、その後工程にくるワイヤ・ボンディング用のパッド
部のボンディングされていない他部のアルミニューム（
一般には１００　μｍ×１００μ１１１）はエポキシ・
モールド一部に露呈してしまっていた。"Conventional Technology" Conventionally, final coating for forming a protective film on electronic component chips was performed at the wafer level. For this reason, the aluminum (
In general, 100 μm x 100 μm (111) is an epoxy
Part of the mold was exposed.

このためアルミニューム・パッドはコロージョンを起こ
しやすく、半導体装置の特性劣化、信頼性低下を誘発し
てしまっていた。For this reason, aluminum pads are prone to corrosion, leading to deterioration of the characteristics and reliability of semiconductor devices.

本発明はかかる従来の有機樹脂封止を施す電子部品にお
きる信頼性の低下を防ぐための保護膜形成方法に関する
ものである。The present invention relates to a method for forming a protective film to prevent a decrease in reliability that occurs in such conventional electronic components sealed with organic resin.

従来、本発明人による特許側（半導体装置作製方法　昭
和５８年特許願第１０６４５２号　昭和５８年６月１４
日出願）が知られている。Previously, the patent side by the present inventor (Semiconductor device manufacturing method, Patent Application No. 106452, June 14, 1982)
(application filed in Japan) is known.

本発明人の上記提案は、パッドがコロ−ジョンをおこす
ことを防ぐのには有効であるが、長期間湿度のある雰囲
気に保持し、これに半田付を行うとすると、半田付の２
６０°Ｃの急激な温度変化で有機樹脂中の水分が急激に
気化し、プラスチックパッケージにクランクを誘発して
しまった。特に電子部品チップの裏側にあるダイの部分
での有機樹脂との剥離によるものが多かった。これはこ
のダイか金属であり、有機樹脂との熱膨張係数の差によ
る歪エネルギの発生によるものと推定される。The above proposal by the present inventor is effective in preventing corrosion of the pad, but if the pad is kept in a humid atmosphere for a long period of time and soldered to it, the soldering
Due to the sudden temperature change of 60°C, the moisture in the organic resin suddenly vaporized, causing the plastic package to crack. In particular, most of the problems were due to separation from the organic resin at the die part on the back side of the electronic component chip. This is thought to be due to the generation of strain energy due to the difference in thermal expansion coefficient between the die and the organic resin.

かかる信頼性の低下を補う電子部品の構造およびその対
策が求められていた。There has been a need for a structure of electronic components that can compensate for such a decrease in reliability, and for countermeasures therefor.

「目的」 この発明は、プラスチック・モールド（有機樹脂）封止
に関し、ファイナルコーティング用保護膜形成を半導体
チップ（トランジスタまたはそれが複数個集積化された
半導体装置等の電子部品を以下電子部品チップまたは単
にチップという）の表面のみならず、リードフレーム（
全面の最終的に電子部品のリードを構成するための集合
体をいう）及びその連結部（電子部品チップのパッドと
リードフレームのステム部のパッドとを連結する半田バ
ンブまたは細線による連結領域のすべて）を覆って保護
膜を設けることにより、高信頼性の電子装置を形成する
ことを目的としている。"Purpose" This invention relates to plastic mold (organic resin) encapsulation, and the formation of a protective film for final coating on semiconductor chips (hereinafter referred to as electronic component chips or electronic components such as transistors or semiconductor devices in which multiple transistors are integrated) Not only the surface of the chip (simply called a chip), but also the surface of the lead frame (
refers to the assembly that ultimately constitutes the lead of an electronic component on the entire surface) and its connection portion (all connection areas by solder bumps or thin wires that connect the pad of the electronic component chip and the pad of the stem portion of the lead frame) ) by providing a protective film to form a highly reliable electronic device.

この発明は、プラスチック・モールド・パッケージにお
いて、信頼性を低下する水等の湿度が単にプラスチック
・パンケージのバルク（内部）のみならず、リードの表
面（プラスチックモールドとの界面が密着性が悪く、こ
の境界）を伝わって侵入する水に対しても、ブロッキン
グ効果を有した高信頼性の電子装置、特に半導体装置を
設けたことを特徴としている。This invention is designed to reduce the reliability of a plastic mold package by reducing moisture such as water, which reduces reliability, not only in the bulk (inside) of the plastic pancage, but also on the surface of the leads (at the interface with the plastic mold, which has poor adhesion). It is characterized by the provision of highly reliable electronic devices, particularly semiconductor devices, that have a blocking effect against water that enters through the boundary).

「発明の構成」 第１図（Ａ）　、　（Ｂ）は本発明構造の有機樹脂封止
を施した電子部品の縦断面図の部品を示す。"Structure of the Invention" FIGS. 1A and 1B show a vertical cross-sectional view of an electronic component sealed with an organic resin having the structure of the present invention.

第１図（Ａ）は金属ダイ（３５”）上にアタッチされた
電子部品チップ（２８）と、このチップの金属バンド、
例えばアルミニュームパッド（３８）とリードフレーム
の電子部品チップとの連結のためのステム（３５）のバ
ンド（３８’）　との間に導体（３７）例えば金の細線
のワイヤポンディングによる連結を行い、さらにこのチ
ップ（２８）表面、パッド（３８）のボンディングされ
ずに露呈した表面、連結ワイヤ（３９）、金属ダイ（３
５’　）の裏面および側面に対し、劣化防止用保護膜、
特に窒化珪素膜、酸窒化珪素膜、炭化珪素膜の下地膜と
ダイヤモンド状炭素（ＤＬＣという）との多層膜（２７
）（図面では図示しにくいため１層膜として示す）のコ
ーティングを行う。FIG. 1(A) shows an electronic component chip (28) attached on a metal die (35"), a metal band of this chip,
For example, a conductor (37), such as a thin gold wire, is connected by wire bonding between the aluminum pad (38) and the band (38') of the stem (35) for connecting the electronic component chip of the lead frame. In addition, the chip (28) surface, the unbonded and exposed surface of the pad (38), the connecting wire (39), and the metal die (3
5' ) on the back and side surfaces of the
In particular, a multilayer film (27
) (shown as a single layer film because it is difficult to illustrate in the drawings) is applied.

この窒化珪素膜の如き下地膜とその上のＤＬＣ膜よりな
る保護膜は、室温またはその近傍の温度において、反応
性気体を反応炉に導入し、そこに電気エネルギを供給す
るいわゆるプラズマ気相法により形成せしめた。This protective film consisting of a base film such as a silicon nitride film and a DLC film thereon is produced using the so-called plasma vapor phase method, in which a reactive gas is introduced into a reactor at room temperature or a temperature close to it, and electrical energy is supplied thereto. It was formed by

かくの如くして、劣化防止用保護膜を下地膜を２００〜
３０００人、一般には約１０００人の厚さに形成した後
、さらにこの上にＤＬＣ膜を３００〜５０００人の厚さ
に形成する。この後、公知のインジェクション・モール
ド法によりエポキシ樹脂（３３）を注入・封止させた。In this way, the protective film for preventing deterioration and the base film are coated with 200~
After forming the film to a thickness of 3,000, generally about 1,000, a DLC film is further formed thereon to a thickness of 300 to 5,000. Thereafter, an epoxy resin (33) was injected and sealed using a known injection molding method.

さらにタイバー（リードフレームのリード間がばらつか
ないように一時的に連結しているもの）を切断するとと
もにフレームをリード部（３７）にて曲げ、さらにリー
ド部を酸洗いした後、リード（３７）にハンダメツキを
行った。Furthermore, the tie bars (those that temporarily connect the leads of the lead frame to prevent them from dispersing) are cut, the frame is bent at the lead part (37), and the lead part is pickled, and then the leads (37 ) was soldered.

かかる本発明の半導体装置の構造においては、例え信頼
性を低下させる水がモールド材を含侵し、チップ（２８
）、パッド（３８）、ステム（３５）のパッド（３８”
）の表面に集合してもこの水に対しこれらの水が電子部
品チップ等に直接接触しないようにして高信頼性化を図
っている。In the structure of the semiconductor device of the present invention, even if water, which reduces reliability, impregnates the molding material, the chip (28
), pad (38), stem (35) pad (38”
) Even if this water collects on the surface of the chip, high reliability is achieved by preventing this water from coming into direct contact with electronic component chips, etc.

また第１図（Ｂ）は電子部品チップ（２８）とリードフ
レームのステム（３５〉との間に細線のワイヤボンドを
行わず、直接半田等の導体にて連結したものである。こ
のためには第１図（Ｂ）において、例えば電子部品チッ
プ（２８）のパッド（３８）をアル短ニウムとその上に
金の２層膜とする。リードフレームのステム（３５）の
パッド（３８′）をニッケルとし、ここに半田バンブを
作り、このバンブをチップのパッド（３８）と位置合わ
せをするとともに、加熱圧着をして連結（３９’）をす
る。すると第１図（Ｂ）に示す如く、電子部品チップの
下に第１図（Ａ）のようなダイ（３５’）がなく、かつ
ボンディングワイヤ（３９）も省略され小型化されたも
のとなる。Moreover, in FIG. 1(B), the electronic component chip (28) and the stem (35) of the lead frame are not connected with a thin wire bond, but are directly connected with a conductor such as solder. In Fig. 1(B), for example, the pad (38) of the electronic component chip (28) is a two-layer film of aluminum and gold on top of it.The pad (38') of the stem (35) of the lead frame is is made of nickel, a solder bump is made here, this bump is aligned with the pad (38) of the chip, and the connection (39') is made by heat-pressing.Then, as shown in Fig. 1 (B). , there is no die (35') like that shown in FIG. 1(A) under the electronic component chip, and the bonding wire (39) is also omitted, resulting in a smaller size.

さらに第１図（Ａ）　、　（Ｂ）においては、ＰＣＢ　
（プリント回路基板）への電子部品（２９）の密接はダ
イの内側で行っている。このため、半田付の時の２６０
°Ｃ１１０秒の急激な熱上昇に対し、万が−の有機樹脂
中に含浸している水の膨張によるパッケージのクランク
の発生をさらに防ぐ。Furthermore, in Figures 1 (A) and (B), the PCB
The electronic component (29) is closely attached to the (printed circuit board) inside the die. For this reason, when soldering, 260
This further prevents the package from cranking due to expansion of the water impregnated in the organic resin in the event of a rapid heat rise of 110 seconds at °C.

第２図は本発明の電子部品チップがリードフレームにボ
ンディングまたはマウントされた構造、即ち基板（２′
）を複数個ホルダに装着して集合さ廿た基体（２）を複
数配設させ、プラズマＣＶＤ法により窒化珪素膜等の下
地膜とＤＬＣとの多層の保護膜のコーティングを行うた
めのプラズマＣＶＤ装置の概要を示す。FIG. 2 shows a structure in which the electronic component chip of the present invention is bonded or mounted on a lead frame, that is, a substrate (2'
) is attached to a holder and a plurality of aggregated substrates (2) are arranged, and a plasma CVD method is used to coat a multilayer protective film of a base film such as a silicon nitride film and DLC using a plasma CVD method. An overview of the device is shown.

図面において、反応系（６）、ドーピング系（５）を有
している。In the drawing, it has a reaction system (6) and a doping system (5).

反応系（６）は、反応空間を有する反応室（１）と予備
室（７）とを有し、ゲート弁（８）　、　（９）とを有
している。反応室（１）は内側に供給側フード（１３）
を有し、フード（１３）は入口側ノズル（３）より反応
性気体を下方向に吹き出し、プラズマ反応をさせ、基板
または基体上に多層の保護膜形成を行った。The reaction system (6) has a reaction chamber (1) having a reaction space, a preliminary chamber (7), and gate valves (8) and (9). The reaction chamber (1) has a supply hood (13) inside.
The hood (13) blows reactive gas downward from the inlet nozzle (3) to cause a plasma reaction and form a multilayer protective film on the substrate or substrate.

反応後は排出側フード（１３”）より排気口（４）を経
てバルブ（２１）、真空ポンプ（２０）に至る。高周波
電源（１０）よりの電気エネルギはマツチングトランス
（２６）をへて、５０にＨｚ　〜５０ＭＩＩｚ例えば１
３．５６ＭＨｚの周波数を上下間の一対の同じ大きさの
網状電極（１１）（１１’）に加える。マツチングトラ
ンスの中点（２５゜）は接地レベル（２５）とし、この
接地レベルと基体（２）との間にはバイアス（Ｉ２）を
ＯＣまたはＡＣバイアス（１〜５００ＫＨｚ例えば５０
ＫＨ２）として加えた。また周辺の反応性気体を反応室
の内壁にまで広がらないようにした。枠構造のホルダ（
４０）は導体の場合は浮いたレベルとし、また絶縁体で
あってもよい。After the reaction, the gas flows from the exhaust side hood (13") through the exhaust port (4) to the valve (21) and vacuum pump (20). Electrical energy from the high frequency power source (10) passes through the matching transformer (26). , 50Hz ~ 50MIIz e.g. 1
A frequency of 3.56 MHz is applied to a pair of equally sized mesh electrodes (11) (11') between the upper and lower sides. The center point (25°) of the matching transformer is set at the ground level (25), and a bias (I2) is applied between this ground level and the substrate (2) using an OC or AC bias (1 to 500 KHz, e.g. 50
KH2). Additionally, the surrounding reactive gas was prevented from spreading to the inner wall of the reaction chamber. Frame structure holder (
40) may be a floating level if it is a conductor, or it may be an insulator.

反応性気体は一対の電極（１１）、　（１１’）により
供給された高周波エネルギにより励起され、また低周波
バイアスエネルギにより被形成面を有する電子部品がバ
イアス印加され、ワイヤボンドがなされ、この電子部品
チップ、このチップにポンディングされたステムまたは
リードフレーム上にコーティングされるようにした。こ
のプラズマＣＶＤ法において、被膜の被形成体（２）（
以下基体（２）という）はサポータ（４０’）上に配設
された枠構造のホルダ（４０）内に一対の電極間の電界
の方向に平行にし、さらにいずれの電極（１１）、（１
１’）からも離間させている。複数の基板は互いに一定
の間隔（３〜１３ｃｍ例えば８ｃ＋ｎ　）または概略一
定の間隔を有して配設されている。この多数の基体（２
）は、グロー放電により作られるプラズマ中の陽光柱内
に配設される。The reactive gas is excited by high frequency energy supplied by a pair of electrodes (11) and (11'), and low frequency bias energy applies a bias to the electronic component having the surface to be formed, wire bonding is performed, and this electron The component chip was bonded to this chip to be coated onto the stem or lead frame. In this plasma CVD method, the object (2) on which the film is formed (
The base (2) (hereinafter referred to as the base body (2)) is placed in a frame-structured holder (40) disposed on a supporter (40') parallel to the direction of the electric field between a pair of electrodes, and furthermore, either of the electrodes (11), (1
1'). The plurality of substrates are arranged at regular intervals (3 to 13 cm, for example 8c+n) or approximately at regular intervals. This large number of substrates (2
) is placed in a positive column in the plasma created by glow discharge.

第３図（Ａ）は基体（２）の部品を拡大したものである
。即ち第２図の基体（２）は電子部品チップをり〜ドフ
レームに５〜ＩＯケマウントした基板（２”）を示す。FIG. 3(A) is an enlarged view of the parts of the base body (2). That is, the base body (2) in FIG. 2 shows a board (2'') on which 5 to 100 pieces of electronic component chips are mounted on a board frame.

電子部品チップ（２８）を第３図（Ａ）で口型で略記し
ている。リードフレームのリードを一時的に固定してい
る上下の補助バー（４１）、（４１’）を第３図（Ａ）
で直線で示している。第３図（Ａ）のＡ−Ａ’の縦断面
図を（Ｂ）に示している。第３図（Ｂ）ではそれぞれの
電子部品（２９−１）　、　（２９−２）　　・・（２
９−ｎ）即ち（２９）に対応して、補助バー（４１）　
、　（４１’）、　　リード（３７）　、パッド（３８
）　、　（３８’）、電子部品チップ（２８）で示して
いる。The electronic component chip (28) is abbreviated as a mouth shape in FIG. 3(A). Figure 3 (A) shows the upper and lower auxiliary bars (41) and (41') that temporarily fix the leads of the lead frame.
is shown as a straight line. A vertical cross-sectional view taken along line AA' in FIG. 3(A) is shown in FIG. 3(B). In Figure 3 (B), each electronic component (29-1), (29-2), (29-2)
9-n), that is, corresponding to (29), the auxiliary bar (41)
, (41'), lead (37), pad (38
), (38') and an electronic component chip (28).

第３図（Ｃ）はリードフレーム（２“）に電子部品チッ
プ（２８）がマウントされた一部の拡大図である。FIG. 3(C) is an enlarged view of a part of the electronic component chip (28) mounted on the lead frame (2'').

リードフレームの補助バー（４１）　、　（４１’）は
開穴（４３）（４３”）が設けられ、これを利用してホ
ルダのつめにかけて第３図（Ａ）の基体を構成させてい
る。第３図（Ｃ）にはリード（３７）およびその先端部
のステム（３５）が示され、このリードのバラツキを防
ぐタイバー（４２）　、　（４２”）が示されている。The auxiliary bars (41) and (41') of the lead frame are provided with openings (43) (43''), which are used to hang the bars of the holder to form the base shown in FIG. 3(A). FIG. 3(C) shows a lead (37) and a stem (35) at its distal end, and also shows tie bars (42) and (42'') that prevent the lead from varying.

第１図の構造とするには、このタイバー（４２）　、　
（４２°）と補助バー（４１）　、　（４１’　）は有
機樹脂モールド後除去される。To achieve the structure shown in Figure 1, this tie bar (42),
(42°) and auxiliary bars (41) and (41') are removed after molding with organic resin.

以下に第２図、第３図に示したプラズマＣＶＤ装置を用
いた本発明の２層の保護膜形成の実施例を示す。「実施
例１」 第１図（Ａ）に示した如く、リードフレームのダイ（３
５’）に電子部品チップ（２８）をアタッチし、このチ
ップのパッド（３８）とステムのパッド（３８”）との
間にワイヤボンドを行った。An example of forming a two-layer protective film of the present invention using the plasma CVD apparatus shown in FIGS. 2 and 3 will be shown below. “Example 1” As shown in FIG. 1(A), the lead frame die (3
An electronic component chip (28) was attached to 5'), and wire bonding was performed between the pad (38) of this chip and the pad (38'') of the stem.

第３図に示す如く、基体に電子部品チップをマウントし
たリードフレーム（２９−１）　、　（２９−２）　　
・・・（２９−ｎ）即ち（２９）を配設したものである
。このジグのＡ−Ａ”の断面図を（Ｂ）に示す。チップ
（２８）はパッド（３８）　、　（３８’）を含む連結
部でステム（３５）に連結してあり、これらが複数ケフ
レーム上に配設されている。As shown in Fig. 3, lead frames (29-1) and (29-2) on which electronic component chips are mounted on the base.
...(29-n), that is, (29) is arranged. A cross-sectional view of this jig taken along line A-A'' is shown in (B). The chip (28) is connected to the stem (35) at a connecting portion including pads (38) and (38'), and these are connected to the stem (35). placed on the frame.

リードフレーム部はこの実施例では８０ビンの例を示し
ている。そして４２７０イまたは銅フレームのステム（
３５）と、ダイ（３５’）上の電子部品チップ（２８）
めポンディングパッドとの間に直接的にボンディングを
している。しかしこの形状以外の任意のピン数、形状を
も同様に有せしめることが可能であることはいうまでも
ない。In this embodiment, the lead frame section has 80 bins. and 4270 i or copper frame stem (
35) and the electronic component chip (28) on the die (35')
It is directly bonded to the bonding pad. However, it goes without saying that it is also possible to have any number and shape of pins other than this shape.

第２図に示した基体を配設させたプラズマＣＶＤ装置に
おいて、ドーピング系は珪化物気体であるジシラン（Ｓ
ｉ、Ｈ，）を（１７）より、また窒化物気体である窒素
を（１４）より、反応室等のエツチング気体例えば弗化
窒素を（１６）より、またエチレン（Ｃ２Ｈ４）を（１
５）より供給している。それらは流量計（１８）　。In the plasma CVD apparatus equipped with the substrate shown in FIG. 2, the doping system is disilane (S), which is a silicide gas.
i, H, ) from (17), nitrogen as a nitride gas from (14), etching gas such as nitrogen fluoride in the reaction chamber from (16), and ethylene (C2H4) from (1).
5) Supplied from They are flowmeters (18).

バルブ（１９）により制御されている。It is controlled by a valve (19).

例えば、下地膜である窒化珪素を作らんとする場合、基
板温度は外部加熱を特に積極的に行わない室温（プラズ
マによる自己加熱を含む）またはその近傍の温度（３０
０’Ｃまでの温度範囲）とし、反応性基体は反応室に５
ｉｚＨ６／Ｎｚ　＝　１／３として反応室の圧力０．０
１〜０．１ｔｏｒｒ　、例えば０．０５ｔｏｒｒを保持
しつつ供給した。さらに１３．５６ＭＨｚの周波数の高
周波エネルギをＩＫ−の出力で一対の電極（１１）、（
１１′）に供給した。ＡＣバイアス用の５０　Ｋ　ｔｌ
　ｚの周波数の電気エネルギ（２４）を基体（２）に１
００〜５００−の出力で加える。かくして平均５００人
（５００人±１００人）に約３分（平均速度３人／秒）
の被膜形成を行った。For example, when making silicon nitride as a base film, the substrate temperature should be at room temperature (including self-heating by plasma) without any active external heating, or a temperature close to that temperature (30°C).
temperature range up to 0'C), and the reactive substrate was placed in the reaction chamber at 5°C.
The pressure in the reaction chamber is 0.0 as izH6/Nz = 1/3
The pressure was maintained at 1 to 0.1 torr, for example, 0.05 torr. Furthermore, high frequency energy with a frequency of 13.56 MHz is applied to a pair of electrodes (11), (
11'). 50 K tl for AC bias
Electrical energy (24) with a frequency of z is applied to the base (2) at 1
Add with an output of 00 to 500-. Thus, it takes about 3 minutes for an average of 500 people (500 people ± 100 people) (average speed of 3 people/second)
A film was formed.

窒化珪素膜はその絶縁耐圧３　Ｘ１０６Ｖ／ｃｍ以上を
有し、比抵抗は２Ｘ１０”０ｃｍであった。赤外線吸収
スペクトルでは８６４ｃｍ　−’の５ｔ−Ｎ結合の吸収
ピークを有し、屈折率は１．７〜１．８であった。The silicon nitride film had a dielectric strength voltage of 3 x 106 V/cm or more, and a specific resistance of 2 x 10''0 cm.The infrared absorption spectrum had an absorption peak of 5t-N bond at 864 cm -', and the refractive index was 1. It was 7-1.8.

下地膜として酸窒化珪素を作ろうとする時は、このジシ
ラン、窒素に加えてＳｉ２Ｆ６を５ｉＪｈの５〜１０％
を添加した。すると残留酸素が繰り込まれて酸窒化珪素
を作ることができた。When trying to make silicon oxynitride as a base film, in addition to this disilane and nitrogen, Si2F6 is added at 5 to 10% of 5iJh.
was added. Residual oxygen was then incorporated to form silicon oxynitride.

また炭化珪素はシランとエチレンとを混合してプラズマ
ＣＶＤ法により形成した。Further, silicon carbide was formed by mixing silane and ethylene and using a plasma CVD method.

更にこの上にＤＬＣ膜を同一反応系で形成した。Further, a DLC film was formed thereon using the same reaction system.

即ち下地膜を形成した後、これら全体を真空引きし、１
０１〜ｔｏ−’ｔｏｒｒとした。この系にエチレンを１
００χの濃度で反応室（１）に反応空間の圧力０．０１
〜Ｑ、５ｔｏｒｒ例えばＱ、Ｑ５ｔｏｒｒを保持しつつ
供給した。That is, after forming the base film, the whole is evacuated, and 1
01~to-'torr. Add 1 ethylene to this system
At a concentration of 00χ, the reaction space pressure is 0.01 in the reaction chamber (1).
~Q, 5 torr, for example, Q, Q5 torr was maintained and supplied.

高周波バイアスエネルギは同様とした。すると２人／秒
の成長速度でＤＬＣ膜を３００〜３０００人例えば１０
００入の厚さに形成することができた。The high frequency bias energy was the same. Then, at a growth rate of 2 people/second, 300 to 3000 people, for example 10
It was possible to form the film to a thickness of 0.00.

ＤＬＣは金属および酸化物上には密着しにくいため、金
属のリードフレーム、電子部品チップに対しても密着性
のよい下地膜を形成した。特にまず窒化珪素膜を２００
〜２０００大形成し、さらにその上に窒化珪素膜と密着
性のよいＤＬＣを３００〜３０００人の厚さに形成した
。このＤＬＣはすべての酸に対して耐久性を有していて
、超高信頼性の電子部品を作るのに優れていた。Since DLC has difficulty adhering to metals and oxides, a base film with good adhesion to metal lead frames and electronic component chips was formed. In particular, first the silicon nitride film is
2,000 thick was formed, and DLC having good adhesion to the silicon nitride film was formed thereon to a thickness of 300 to 3,000 thick. This DLC was resistant to all acids and was excellent for making ultra-reliable electronic components.

このため、アルミニウムのコロ−ジョンをおさえ、さら
に有機樹脂と密着性がよいため、きわめて好ましい。ま
たこのＤＬＣは固有抵抗１０１０〜１０Ｉ２ΩｃＩ１１
を有しているため有効である。Therefore, it is extremely preferable because it suppresses corrosion of aluminum and has good adhesion to organic resins. Also, this DLC has a specific resistance of 1010 to 10I2ΩcI11
It is effective because it has

第２図におけるホルダ（４０）は枠の内側の大きさ６０
ｃｍ　Ｘ　６０ｃｍを有し、電極間距離は３０ｃｍ　（
有効２０ｃｍ　）としている。The holder (40) in Fig. 2 has an inner size of 60 mm.
cm x 60 cm, and the distance between the electrodes is 30 cm (
The effective distance is 20cm).

即ち、本発明は、下地膜として窒化珪素、酸窒化珪素（
反応ガスに積極的に酸素等の酸化物気体を用いていない
）、炭化珪素に加えて、この上にＤＬＣ膜を形成した多
層膜を電子部品チップとりドフレームとそれらの間の連
結部でそれぞれを互いに連結した後に保護膜としてコー
ティングしている。これらはパッド、チップの露呈した
表面に対しても均一な膜厚で保護膜をコーティングする
ことができる。特に本発明においては、被膜形成の時、
高周波プラズマ発生と同時にＤＣまたはＡＣのバイアス
をリードフレームに印加している。即ち、基体（２）に
印加されたＡＣバイアスを成膜中にすべてのフレームに
同じく加えることができるため、きわめて緻密なりＬＣ
（ＳＰ”結合手を有するダイヤモンド状炭素）膜を作る
ことができる。また反応性気体の活性化は高周波を用い
るため活性化率を高くすることができた。That is, the present invention uses silicon nitride, silicon oxynitride (
In addition to silicon carbide, a multilayer film with a DLC film formed thereon is applied to the electronic component chip frame and the connecting parts between them. After they are connected to each other, they are coated as a protective film. These can coat the exposed surfaces of pads and chips with a protective film with a uniform thickness. In particular, in the present invention, when forming a film,
A DC or AC bias is applied to the lead frame at the same time as high frequency plasma is generated. That is, since the AC bias applied to the substrate (2) can be applied to all frames in the same manner during film formation, extremely dense LC
(diamond-like carbon having SP" bonds) film can be produced. Also, since high frequency is used to activate the reactive gas, the activation rate can be increased.

なお本発明においては、ｐｃｖｏ法において、電気エネ
ルギのみならず、１０〜１５μの波長の遠赤外線または
３００ｎｍ以下の紫外光を同時に加えた光エネルギを用
いるフォトＣＶＤ（またはフォトＦＰＣＶＤ）法を併用
することは有効である。In addition, in the present invention, in the PCVO method, a photoCVD (or photoFPCVD) method that uses not only electrical energy but also optical energy in which far infrared rays with a wavelength of 10 to 15 μ or ultraviolet light of 300 nm or less is simultaneously applied is used in combination. is valid.

「効果」 本発明により、金属のリード、電子部品チップ、連結部
と異なる材料は一般に有機樹脂と密着性が悪い。しかし
これらを密着性のよい下地膜を形威し、かつその上にＤ
ＬＣを形成した２層の保護膜とし、このＤＬＣと密着性
のよい有機樹脂で封止することにより高信頼性化を図る
ことができた。特にリードと電子部品チップとを機械的
に有機樹脂で固定保護し、かつこの樹脂の耐水性、耐熱
衝撃性（半田付の際の）に弱いという欠点を保護膜で補
った。"Effects" According to the present invention, materials different from metal leads, electronic component chips, and connecting parts generally have poor adhesion to organic resins. However, these are formed with a base film with good adhesion, and D
High reliability could be achieved by forming a two-layer protective film with LC and sealing it with an organic resin that has good adhesion to the DLC. In particular, the leads and electronic component chips are mechanically fixed and protected using an organic resin, and the disadvantages of this resin's poor water resistance and thermal shock resistance (during soldering) are compensated for with a protective film.

さらに第１図（Ｂ）に示されている如く、第１図（Ａ）
の従来用いられていた構造のグイとワイヤとを除去する
ことにより超小型化を図ることができる。Furthermore, as shown in FIG. 1(B), FIG. 1(A)
By removing the gouers and wires of the conventionally used structure, it is possible to achieve ultra-miniaturization.

第１図（Ｂ）の構造に関しても、下地膜とＤＬＣ膜とよ
りなる２層膜（２７〉を形成することができる。Regarding the structure shown in FIG. 1(B), a two-layer film (27>) consisting of a base film and a DLC film can also be formed.

加えて窒化珪素等下地膜とＤＬＣ膜との多層の保護膜は
水、塩素に対するブロッキング効果（マスク効果）が大
きい。このため本発明構造の半導体において、ＰＣＴ　
（プレッシャー・タンカー・テスト）１０ａｔｏＩｌ、
　１００時間、１５０°Ｃの条件下においても、まった
く不良が観察されず、従来のＩＣチップは５０〜ｌＯＯ
フイツトの不良率を有していたが、５〜１０フイツトに
までその不良率を下げることが可能になった。In addition, a multilayer protective film including a base film such as silicon nitride and a DLC film has a large blocking effect (mask effect) against water and chlorine. Therefore, in the semiconductor having the structure of the present invention, PCT
(Pressure Tanker Test) 10atoIl,
Even under conditions of 150°C for 100 hours, no defects were observed, and conventional IC chips were
The defective rate was 5-10 fits, but it has become possible to lower that rate to 5 to 10 fits.

本発明における保護膜は主として窒化珪素膜とＤＬＣ（
ダイヤモンド・ライク・カーボン）膜との多層膜とした
。しかしこのＤＬＣ膜と密着性のよい膜をその他の絶縁
膜とし、この上にＤＬＣ膜を形成する多層膜であっても
よい。The protective film in the present invention is mainly a silicon nitride film and a DLC (
It is a multilayer film with diamond-like carbon) film. However, a multilayer film may be used in which a film that has good adhesion to the DLC film is used as another insulating film, and the DLC film is formed thereon.

さらに本発明において、電子部品チップは半導体集積回
路として示したが、その他、抵抗、コンデンサであって
もよく、ボンディングもワイヤボンディングのみならず
フリップチップボンディング、ハンダバンプボンディン
グでもよい。Further, in the present invention, the electronic component chip is shown as a semiconductor integrated circuit, but it may also be a resistor or a capacitor, and the bonding may be not only wire bonding but also flip chip bonding or solder bump bonding.

上述した説明においては、リードフレーム上に半導体チ
ップを載置した場合について述べているが、本発明は特
にリードフレームに限るものではなく、リードフレーム
と同様の機能を持つものであっても、同様の効果が期待
できるものである。Although the above description describes the case where a semiconductor chip is mounted on a lead frame, the present invention is not particularly limited to lead frames, and even if the semiconductor chip has the same function as a lead frame, it can be used in the same way. The effects can be expected.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の電子部品の縦断面図を示す。 第２図は本発明方法を実施するためのプラズマ気相反応
装置の概要を示す。 第３図は第２図の装置のうちの基体部の拡大図を示す。FIG. 1 shows a longitudinal sectional view of an electronic component of the present invention. FIG. 2 shows an outline of a plasma gas phase reactor for carrying out the method of the present invention. FIG. 3 shows an enlarged view of the base portion of the device of FIG.

Claims (1)

【特許請求の範囲】 １、フレーム上に電子部品チップを直接または間接的に
マウントまたはボンディングした電子部品を複数ケ配設
した基板または該基板を集合させた基体上に保護膜形成
を行うに際し、プラズマ空間内に前記基板を配設せしめ
、前記基板または基体上に窒化珪素、酸窒化珪素または
炭化珪素とダイヤモンド状炭素との多層膜を前記電子部
品、ボンディング部およびその周辺に前記保護膜として
形成することを特徴とする電子装置作製方法。 ２、特許請求の範囲第１項において、前記保護膜として
の窒化珪素、酸窒化珪素または炭化珪素とダイヤモンド
状炭素との多層膜は外部より加熱することなしに形成す
るとともに、該工程の後、樹脂封止処理を行うことを特
徴とする電子装置作製方法。 ３、特許請求の範囲第１項において、グロー放電プラズ
マは一対の電極間に１０ＫＨｚ〜５０ＭＨｚの周波数の
高周波電界を加えるとともに、前記電極の中間電位と基
板との間に１〜１００ＫＨｚの交流バイアスを加えるこ
とを特徴とする電子装置作製方法。[Claims] 1. When forming a protective film on a substrate on which a plurality of electronic components, each of which has an electronic component chip mounted or bonded directly or indirectly on a frame, or on a substrate that is a collection of such substrates, The substrate is disposed in a plasma space, and a multilayer film of silicon nitride, silicon oxynitride, or silicon carbide and diamond-like carbon is formed on the substrate or base as the protective film on the electronic component, the bonding portion, and the periphery thereof. A method for manufacturing an electronic device characterized by: 2. In claim 1, the multilayer film of silicon nitride, silicon oxynitride, or silicon carbide and diamond-like carbon as the protective film is formed without external heating, and after the step, A method for manufacturing an electronic device, the method comprising performing a resin sealing process. 3. In claim 1, the glow discharge plasma is generated by applying a high frequency electric field with a frequency of 10 KHz to 50 MHz between a pair of electrodes, and applying an alternating current bias of 1 to 100 KHz between the intermediate potential of the electrodes and the substrate. A method for manufacturing an electronic device, characterized by adding:
JP1221214A 1989-08-28 1989-08-28 Manufacture of electronic device Pending JPH0383351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1221214A JPH0383351A (en) 1989-08-28 1989-08-28 Manufacture of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1221214A JPH0383351A (en) 1989-08-28 1989-08-28 Manufacture of electronic device

Publications (1)

Publication Number Publication Date
JPH0383351A true JPH0383351A (en) 1991-04-09

Family

ID=16763254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1221214A Pending JPH0383351A (en) 1989-08-28 1989-08-28 Manufacture of electronic device

Country Status (1)

Country Link
JP (1) JPH0383351A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0652828A1 (en) * 1992-08-03 1995-05-17 Diamonex, Incorporated Abrasion wear resistant coated substrate product

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0652828A1 (en) * 1992-08-03 1995-05-17 Diamonex, Incorporated Abrasion wear resistant coated substrate product
EP0652828A4 (en) * 1992-08-03 1995-09-06 Diamonex Inc Abrasion wear resistant coated substrate product.

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