JPH01292849A - Manufacture of electronic device - Google Patents

Manufacture of electronic device

Info

Publication number
JPH01292849A
JPH01292849A JP63195684A JP19568488A JPH01292849A JP H01292849 A JPH01292849 A JP H01292849A JP 63195684 A JP63195684 A JP 63195684A JP 19568488 A JP19568488 A JP 19568488A JP H01292849 A JPH01292849 A JP H01292849A
Authority
JP
Japan
Prior art keywords
protective film
substrate
chip
silicon nitride
plasma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63195684A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Noriya Ishida
石田　典也
Mitsunori Sakama
坂間　光範
Mari Sasaki
麻理 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP63195684A priority Critical patent/JPH01292849A/en
Publication of JPH01292849A publication Critical patent/JPH01292849A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form a protective film at a room temperature by arranging a substrate or a base substrate inside a plasma produced by glow discharge between a pair of electrodes. CONSTITUTION:Wire bonding of a gold line 39 is applied to a chip 28 adhered to a die 35' of a lead frame and between an aluminum pad 38 and a stem 35 of the chip. Coating of a protective film for deterioration prevention, especially a silicon nitride film 27, is applied to the surface of the chip 28, the surface of the pad 38, the surface of the wire 39, and the rear of the die 35'. The silicon nitride film is formed by introducing silicide gas and ammonia or nitride into a plasma reaction furnace at a room temperature through a plasma vapor method to supply electric energy thereto. After forming a protective film for deterioration prevention such as a silicon nitride film to a thickness of about 1000Angstrom in this way, organic resin is injected and sealed by epoxy mild method, etc., through an injection mold method.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は半導体装置等の電子装置のワイヤボンディン
グ後の保護膜形成方法およびその後の封止に関する。DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention relates to a method for forming a protective film after wire bonding of an electronic device such as a semiconductor device, and to the subsequent sealing.

この発明は、プラスチック・モールド封止に関し、ファ
イナルコーティング用保護膜形成を半導体チップ（トラ
ンジスタまたはそれが複数個集積化された半導体装置を
以下チップという）の表面のみならず、ワイヤボンド用
パッドにボンディングされた金属細線（２５μφ）の少
なくともパッド近傍にコーティングすることにより、コ
ロ−ジョン（Ｔａ食）を防ぐことを目的としている。This invention relates to plastic mold sealing, and the formation of a protective film for final coating is performed not only on the surface of a semiconductor chip (a semiconductor device in which a plurality of transistors or transistors are integrated is hereinafter referred to as a chip), but also on bonding pads for wire bonding. The purpose is to prevent corrosion (Ta corrosion) by coating at least the vicinity of the pad on the thin metal wire (25 μΦ).

この発明は、プラスチック・モールド・パッケ−ジにお
いて、信軌性を低下する水等の湿度、即ち、単にプラス
チック・パッケージの有機樹脂のバルクのみならず、ワ
イヤを伝わり侵入する水、リードフレームの表面を伝わ
って侵入する水に対しても、ブロッキング効果を有した
、高信頼性の半導体装置を設けたことを特徴としている
。This invention is designed to prevent humidity such as water that degrades signal transmission characteristics in plastic molded packages, that is, not only the bulk of the organic resin of the plastic package, but also water that penetrates through the wires and the surface of the lead frame. The device is characterized by the provision of a highly reliable semiconductor device that has a blocking effect against water that penetrates through the air.

この発明は、窒化珪素等の劣化防止用の保護膜形成（フ
ァイナル・コーティング）をウェハ・レベルにて行うの
ではなく、チップをリードフレーム上にダイボンディン
グ（ダイアタッチともいう）し、さらにワイヤ・ボンデ
ィングを完了させる。This invention does not form a protective film (final coating) such as silicon nitride to prevent deterioration at the wafer level, but instead performs die bonding (also called die attach) of the chip onto the lead frame, and then attaches the wire to the lead frame. Complete the bonding.

かくして作られた電子装置はチップ表面のみならずリー
ドフレームのダイの裏面およびボンディングされたワイ
ヤおよびアルミニューム・パッドの露呈している部分に
対しても、同時に外部加熱をすることなく、好ましくは
室温（プラズマによる自己発熱は若干ある）でプラズマ
気相法により行うことにより、これら全ての表面に保護
膜コーティングが施される。その後にプラスチック・モ
ールド処理による封止を行うことを特徴としている。The electronic device thus produced is preferably kept at room temperature without external heating, not only on the chip surface but also on the backside of the die of the lead frame and the exposed parts of the bonded wires and aluminum pads. (There is some self-heating caused by the plasma.) By performing the plasma vapor phase method, a protective film coating is applied to all these surfaces. It is characterized in that it is then sealed by plastic molding.

「従来の技術」 従来、本発明人による特許側（半導体装置作製方法　昭
和５８年特許願第１０６４５２号　昭和５８年６月１４
日出願）が知られている。"Prior Art" Previously, the patent side by the present inventor (Semiconductor device manufacturing method, Patent Application No. 106452, 1982, June 14, 1982)
(application filed in Japan) is known.

チップのファイナル・コーティングは、ウェハ・レベル
にて行っていた。このため、その後工程にくるワイヤ・
ボンディング用のパッド部のアルミニューム（一般には
１００μＸ１００μ）はエポキシ・モールド一部に露呈
していた。Final coating of the chips was done at the wafer level. For this reason, the wire that comes in the subsequent process
The aluminum of the bonding pad (generally 100μ x 100μ) was exposed on a portion of the epoxy mold.

故に、アルミニューム・パッドはコロ−ジョンを起こし
やすく、半導体装置の特性劣化、信頬性低下を誘発して
しまっていた。Therefore, aluminum pads are prone to corrosion, leading to deterioration of the characteristics of semiconductor devices and deterioration of reliability.

本発明はかかる従来のＤＩＰにおきる信顛性の低下を防
ぐための保護膜形成方法に関するものである。The present invention relates to a method for forming a protective film to prevent the deterioration in reliability that occurs in conventional DIP.

「発明の構成」 第１図は本発明構造のプラスチックＤＴＰの縦断面図を
示す。"Structure of the Invention" FIG. 1 shows a longitudinal sectional view of a plastic DTP having the structure of the present invention.

図面において、リードフレームのダイ（３５”）に密着
させたチップ（２８）と、このチップのアルミニウム・
パッド（３８）とステム（３５）との間に金線（３９）
のワイヤボンドを行い、さらにこのチップ（２８）表面
、パッド（３８）表面、ワイヤ（３９）表面およびダイ
（３５’）の裏面に対し、劣化防止用保護膜、特に窒化
珪素膜（２７）のコーティングを行う。In the drawing, the chip (28) is shown in close contact with the die (35”) of the lead frame, and the aluminum
Gold wire (39) between pad (38) and stem (35)
The chip (28) surface, the pad (38) surface, the wire (39) surface, and the back surface of the die (35') are coated with a protective film for preventing deterioration, especially a silicon nitride film (27). Coating.

さらに好ましくは、ワイヤ全体のみならず、ステム（３
５）上面およびそこにボンディングされたワイヤの表面
および裏面に対しても、コーティング（２７’）をした
ものである。More preferably, not only the entire wire but also the stem (3
5) The upper surface and the front and back surfaces of the wires bonded thereto are also coated (27').

この窒化珪素膜の如き保護膜は、室温において、珪化物
気体とアンモニアまたは窒素とをプラズマ反応炉に導入
し、そこに電気エネルギを供給するいわゆるプラズマ気
相法により形成せしめた。This protective film such as a silicon nitride film was formed by a so-called plasma vapor phase method in which silicide gas and ammonia or nitrogen were introduced into a plasma reactor and electrical energy was supplied thereto at room temperature.

このようにして、窒化珪素膜の如き劣化防止用保護膜を
３００〜５０００人、一般には約１０００人の厚さに形
成した後、公知のインジェクション・モールド法により
有機樹脂例えばエポキシ（例えば４１０Ｂ）モールド法
により注入・封止させた。さらにフレームをリード部（
３７）にて曲げ、かつタイバーを切断する。さらにリー
ド部を酸洗いを行った後、リードにハンダメツキを行っ
た。After forming a protective film for preventing deterioration such as a silicon nitride film to a thickness of 300 to 5,000 layers, generally about 1,000 layers, an organic resin such as epoxy (for example, 410B) is molded using a known injection molding method. It was injected and sealed using the method. Furthermore, attach the frame to the lead part (
37) and cut the tie bar. Furthermore, after acid-washing the lead portion, the lead was solder-plated.

かかる本発明の半導体装置の構造において、信軌性が低
下をするモールドバルクからの水の侵入（３３）、ワイ
ヤ（３９）表面を伝わる水の侵入（３３°）、クラック
からの水の侵入（３３”　）、　（３３”’）のすべて
に対しコロ−ジョンを防ぐことができるようになった。In the structure of the semiconductor device of the present invention, water intrusion from the mold bulk (33), water intrusion through the surface of the wire (39) (33°), and water intrusion through cracks (33), which degrades the reliability, occur in the structure of the semiconductor device of the present invention. 33") and (33"'), corrosion can now be prevented.

特にアルミニューム・パッド（３８）の全ての表面が直
接モールド材に露呈・接触していす、加えて窒化珪素膜
は水、塩素に対するブロッキング効果（マスク効果）が
大きい。このため本発明構造の半導体においては、ＰＣ
Ｔ　　（プレッシャー・クツカー・テスト）　１０ａｔ
ｏｍ、１００時間、１５０°Ｃの条件下においても、ま
ったく不良が観察されず、従来の１ｃチツプは５０〜１
００フイツトの不良率を有していたが、５〜１０フイツ
トにまでその不良率を下げることが可能になった。In particular, the entire surface of the aluminum pad (38) is directly exposed and in contact with the molding material, and in addition, the silicon nitride film has a large blocking effect (mask effect) against water and chlorine. Therefore, in the semiconductor having the structure of the present invention, PC
T (Pressure Kutzker Test) 10at
om, no defects were observed even under the conditions of 150°C for 100 hours, and the conventional 1c chip
The defective rate was 0.00 fits, but now it has become possible to lower the defective rate to 5 to 10 fits.

第２図は本発明のチップがフレームにボンディングされ
た構造の基板およびそれを複数個集合させた基体（２）
（基板および基体をまとめて基体とも以下では略記する
）を複数配設させ、プラズマ活性状態により窒化珪素膜
のコーティングを行うための装置の概要を示す。Figure 2 shows a substrate with a structure in which the chip of the present invention is bonded to a frame, and a substrate (2) in which a plurality of chips are assembled.
An outline of an apparatus for coating a silicon nitride film in a plasma activated state by disposing a plurality of substrates (hereinafter collectively referred to as substrates) will be described.

図面において、反応系（６）、ドーピング系（５）を有
している。In the drawing, it has a reaction system (6) and a doping system (5).

反応系は、反応室（１）と予備室（７）とを有し、ゲー
ト弁（８）　、　（９）とを有している。反応室（１）
は内側に供給側フードを有し、フード（１３）のノズル
より入口側（３）よりの反応性気体を下方向に吹き出し
、プラズマ反応をさせ、基板または基体上に保護膜形成
を行った。反応後は排出側フード（１４）より、排気口
（４）を経てバルブ（２１）、真空ポンプ（２０）に至
る。高周波電源（１０）よりの電気エネルギは、マツチ
ングトランス（２３）をへて、１〜５００ＭＨｚ例えば
１３．５６ＭＨｚの周波数を上下間の一対の同じ大きさ
の網状電極（１１）　、　（１１’）に加える。さらに
マツチングトランスの中点（２５’）は接地レベル（２
５）とし、ここと基体（２）との間にはバイアス（１２
）、ＤＣまたはＡＣバイアス（１〜５００ＫＨｚ例えば
５０にｆｉｚ）を必要に応じて加えた。または基体を接
地レベルとした。The reaction system has a reaction chamber (1), a preliminary chamber (7), and gate valves (8) and (9). Reaction chamber (1)
had a supply side hood inside, and the reactive gas from the inlet side (3) was blown downward from the nozzle of the hood (13) to cause a plasma reaction and form a protective film on the substrate or substrate. After the reaction, the gas flows from the discharge side hood (14), through the exhaust port (4), to the valve (21), and to the vacuum pump (20). Electrical energy from the high frequency power source (10) passes through a matching transformer (23) and transmits a frequency of 1 to 500 MHz, for example 13.56 MHz, to a pair of mesh electrodes (11), (11') of the same size between the upper and lower sides. Add to. Furthermore, the middle point (25') of the matching transformer is at the ground level (25').
5), and a bias (12
), DC or AC bias (1-500 KHz e.g. 50 fiz) was applied as required. Or the base was at ground level.

周辺の枠構造のホルダ（４０）は導体の場合は接地レベ
ルとし、また絶縁体であってもよい。そして反応性気体
は一対の電極（１１）、　（１２）により供給された高
周波エネルギにより励起され、必要に応じて加えられた
低周波バイアスエネルギにより被形成面を有する電子部
品がバイアス印加され、ワイヤボンドがなされ、このチ
ップ、ボンディングワイヤおよびその近傍にコーティン
グされるようにした。このプラズマ活性状態において、
被膜の被形成体（２）（以下基体（２）という）は、サ
ポータ（４０°）上に配設された枠構造のホルダ（４０
）内に一対の電極間の電界の方向に平行に、さらにいず
れの電極（１１）　、　（１２）からも離間させている
。そして複数の基体は互いに一定の間隔（３〜１３ｃｍ
例えば８ｃｍ　）または概略一定の間隔を有して配設さ
れている。The peripheral frame structure holder (40) may be at ground level if it is a conductor, or may be an insulator. Then, the reactive gas is excited by high frequency energy supplied by a pair of electrodes (11) and (12), and the electronic component having the surface to be formed is biased by low frequency bias energy applied as necessary, and the wire Bonds were made and the chip, bonding wires and their vicinity were coated. In this plasma active state,
The body (2) on which the coating is formed (hereinafter referred to as the base body (2)) is a frame-structured holder (40°) disposed on a supporter (40°).
), parallel to the direction of the electric field between the pair of electrodes, and further spaced apart from any of the electrodes (11) and (12). The plurality of substrates are spaced apart from each other at regular intervals (3 to 13 cm).
For example, they are arranged at approximately constant intervals.

この多数の基体（２）は、グロー放電により作られるプ
ラズマ中の陽光柱内に配設される。さらにこの基体は第
３図（Ａ）に示す如く、その次工程の有機樹脂のトラン
スファモールド工程で一度に注入する手段、または基板
の配設手段用のジグと同一ジグを金属材料で作り、ここ
に電気的にへＣバイアスが加わるようになっている。This large number of substrates (2) is arranged in a positive column in plasma created by glow discharge. Furthermore, as shown in FIG. 3(A), this base body is made of a metal material and is made of the same jig as the means for injecting the organic resin at once in the next process of transfer molding or the means for arranging the substrate. A C bias is electrically applied to.

第３図（Ａ）は基体（２）においてリードフレーム上に
半導体装置（２８）がボンディングされた電子装置（２
９）を５〜２５ケ、ユニット化した基板（４１）を１０
〜５０ケ有する。そして複数の半導体チップがボンディ
ングされた１本のリードフレーム（４１）（基板）のＡ
−Ａ’の縦断面図を第３図（Ｂ）に示す。第３図（Ｂ）
において、ジグ（４４）はリードフレーム（３５）　、
半導体チップ（２８）、金属線（３９）よりなる。FIG. 3(A) shows an electronic device (2) in which a semiconductor device (28) is bonded onto a lead frame in a base (2).
9), 5 to 25 units, and 10 unitized boards (41)
There are ~50 pieces. A of one lead frame (41) (substrate) to which multiple semiconductor chips are bonded.
-A' is shown in FIG. 3(B). Figure 3 (B)
In the jig (44), the lead frame (35),
It consists of a semiconductor chip (28) and a metal wire (39).

第２図における反応性気体はフード（１３）より枠構造
のホルダ（４０）の内側およびフード（１４）により囲
まれた内側にてプラズマ活性状態で基板上に被膜形成が
なされ、フレークが反応室内で作られないようにしてい
る。以下に実施例に従って概略を示す。In FIG. 2, the reactive gas forms a film on the substrate in a plasma-activated state inside the frame-structured holder (40) from the hood (13) and inside surrounded by the hood (14), and flakes form inside the reaction chamber. I'm trying to prevent it from being made. An outline will be shown below according to examples.

第２図に示すごとき本発明方法におけるＰＣＶＤ法は、
基板にＡＣバイアスを加え、かつプラズマ陽光社内に保
持され、かつ窒化珪素膜を形成するに際し、外部より加
熱をしなくても充分に緻密な絶縁膜を作ることができる
という特徴を有する。The PCVD method in the method of the present invention as shown in FIG.
It is characterized by applying an AC bias to the substrate, maintaining it in a plasma solar in-house, and making it possible to form a sufficiently dense insulating film without external heating when forming a silicon nitride film.

そのプロセス上の１例を以下に示す。An example of this process is shown below.

「実施例１」 第２図のプラズマＣＶＤ装置において、ドーピング系は
珪化物気体であるジシラン（Ｓｉ２Ｈ６）を（１７）よ
り、また窒化物気体であるアンモニアまたは窒素を（１
６）より、スパッタ用の非生成物気体であるアルゴンを
（１５）より供給している。それらは流量計（１８）　
、バルブ（１９）により制御されている。``Example 1'' In the plasma CVD apparatus shown in FIG. 2, the doping system includes disilane (Si2H6), which is a silicide gas, from (17), and ammonia or nitrogen, which is a nitride gas, from (17).
From 6), argon, which is a non-product gas for sputtering, is supplied from (15). They are flow meters (18)
, and is controlled by a valve (19).

例えば、基板温度は外部加熱を特に積極的に行わない室
温（プラズマによる自己加熱を含む）とした。そしてま
ず反応空間（１）にアルゴンを導入し、基体（２）の表
面のプラズマ処理を行った。即ち、これらアルゴンに対
し、１３．５６　ＭＨｚの周波数によりＩＫＨの出力を
一対の電極（１１）、　（１１’）に供給した。またＡ
Ｃバイアス用の５０　Ｋ　ＩＩ　ｚの周波数の電気エネ
ルギ（２４）を基体（２）に１００〜５００　Ｈの出力
で加える。するとこのダイの裏面に付着している水分、
低級酸化物を除去することができ、成膜する被膜の密着
性を向上させることができた。For example, the substrate temperature was set to room temperature (including self-heating by plasma) without any active external heating. First, argon was introduced into the reaction space (1), and the surface of the substrate (2) was subjected to plasma treatment. That is, for these argon, IKH output was supplied to the pair of electrodes (11) and (11') at a frequency of 13.56 MHz. Also A
Electrical energy (24) with a frequency of 50 K II z for C bias is applied to the substrate (2) with a power of 100-500 H. Then, the moisture attached to the back side of this die,
Lower oxides could be removed and the adhesion of the deposited film could be improved.

次にこのプラズマ処理がなされた被形成面上に保護膜を
形成する。即ち窒化珪素膜を形成する場合、反応性気体
は例えば、Ｎｌｈ／ＳｉＪ、／Ｎｚ　＝　１／３１５と
した。即ちこれらアルゴンに対し、１３．５６　ＭＨｚ
の周波数によりＩＫ−の出力を一対の電極（１１）　、
　（１１’）に供給した。またＡＣバイアス用の５０Ｋ
Ｉｌｚの周波数の電気エネルギ（２４）を基体（２）に
１００〜５００−の出力で加える。かくして平均１００
０人（１０００人±２００人）に約１０分（平均速度３
Ａ／秒）の被膜形成を行った。Next, a protective film is formed on the surface to be formed which has been subjected to this plasma treatment. That is, when forming a silicon nitride film, the reactive gas was set to, for example, Nlh/SiJ, /Nz = 1/315. That is, for these argon, 13.56 MHz
The output of IK- is connected to a pair of electrodes (11) according to the frequency of
(11'). Also 50K for AC bias
Electrical energy (24) at a frequency of Ilz is applied to the substrate (2) with a power of 100 to 500-. Thus the average is 100
Approximately 10 minutes (average speed 3) to 0 people (1000 people ± 200 people)
A/sec) film formation was performed.

窒化珪素膜はその絶縁耐圧８　Ｘ１０”Ｖ／ｃｍ以上を
有し、比抵抗は２　ＸＩＯ”Ωｃ１１であった。赤外線
吸収スペクトルでは８６４ｃｍ　−’の５ｉ−Ｎ結合の
吸収ピークを有し、屈折率は２．０であった。The silicon nitride film had a dielectric strength voltage of 8.times.10"V/cm or more, and a specific resistance of 2.times.10".OMEGA.c11. The infrared absorption spectrum showed an absorption peak of 5i-N bond at 864 cm −' and a refractive index of 2.0.

５χＮａＣ１で溶解させた塩水中（９５°Ｃ）に保有し
てところ、２０時間を経ても何らの劣化も見られなかっ
た。このため、本発明が劣化防止用保護膜として用いる
ことを証明することができた。When kept in saline solution (95°C) in which 5χNaCl was dissolved, no deterioration was observed even after 20 hours. Therefore, it was possible to prove that the present invention can be used as a protective film for preventing deterioration.

ホルダ（４０）は枠の内側の大きさ６０ｃｍ　Ｘ　６０
ｃｍ＋を有し、電極間距離は３０ｃｍ　（有効２０ｃａ
＋　）としている。The holder (40) has an inside size of 60cm x 60cm.
cm+, and the distance between the electrodes is 30cm (effective 20ca
+ ).

また第２図の基体（２）の部分を拡大した図面を第３図
に示す。Further, FIG. 3 shows an enlarged view of the base body (2) in FIG. 2.

第３図において、（Ａ）はプレスモールド注入装置にお
けるリードフレームＩＯケ付の基体側のジグである。こ
のジグのＡ−Ａ’の断面図を（１３）に示す。In FIG. 3, (A) is a jig on the base side with a lead frame IO in the press mold injection device. A cross-sectional view of this jig along line AA' is shown in (13).

ダイ（３５′）上のチップ（２８）をワイヤ（３９）で
フレーム（３５）にボンディングをして基板を構成して
いる。そして、これらが複数ケリードフレーム上に配設
されて基体を構成している。この基体を構成するフレー
ムを１０ケ並べている他の基体のジグ（２）では樹脂モ
ールドされるべき基体は（４２）よりパス（４３）をへ
て領域（４１）を加熱加圧して注入するようになってい
る。このジグの大きさ、フレーム上でのチップの数は仕
様によって変更され得る。A chip (28) on a die (35') is bonded to a frame (35) with a wire (39) to form a substrate. A plurality of these components are arranged on the lead frame to constitute a base body. In another base jig (2) in which 10 frames constituting this base are arranged, the base to be resin molded passes through the path (43) from (42) and is injected by heating and pressurizing the area (41). It has become. The size of this jig and the number of chips on the frame can be changed depending on the specifications.

第３図（Ｃ）は、リード部の右側を省略した１６ピンの
例を示している。そして４２７０イまたは銅フレーム（
３５）のステムとダイ（３５’）上のチップ（２８）と
のポンディングパッドとの間に直接的にボンディングを
している。しかしこの形状以外の任意のピン数、形状を
も同様に有せしめ得ることはいうまでもない。FIG. 3(C) shows an example of 16 pins with the right side of the lead portion omitted. and 4270i or copper frame (
35) and the bonding pad of the chip (28) on the die (35') are directly bonded. However, it goes without saying that any number and shape of pins other than this shape may be similarly provided.

即ち本発明の作製方法は、単に保護膜を窒化珪素膜をワ
イヤボンドした後にチップ上、ダイ（３５°）の裏面に
コーティングするという特長を有するのみならず、パッ
ド、チップ表面、ダイの裏面に対しても均一な膜厚をコ
ーティングする。また反応性気体の活性化は高周波を用
いるため活性化率を高くすることができた。In other words, the manufacturing method of the present invention not only has the feature of simply coating the silicon nitride film on the chip and the back surface of the die (35°) after wire-bonding the silicon nitride film, but also coats the protective film on the pad, the chip surface, and the back surface of the die. It also coats the surface with a uniform thickness. Furthermore, since high frequency was used to activate the reactive gas, the activation rate could be increased.

なお本発明においては、ｐｃｖｏ法において、電気エネ
ルギのみならず、１０〜１５μの波長の遠赤外線または
３（１０ｎｍ以下の紫外光を同時に加えた光エネルギを
用いるフォトＣＶＤ　（またはフォトＦＰＣＶＤ）法を
併用することは有効である。In the present invention, the PCVO method uses not only electrical energy but also a photoCVD (or photoFPCVD) method that uses light energy to which far infrared rays with a wavelength of 10 to 15μ or ultraviolet light with a wavelength of 3 (10 nm or less) is simultaneously applied. It is valid to do so.

「効果」 本発明において、プラズマ処理を室温で行ったため、ダ
イにチップをアタッチした時に有機樹脂を加熱して劣化
させることがない。また加熱に必要な電力、時間が省け
、生産性に優れている。加えて、ダイの裏面に対しても
、チップの表面と同様に保護膜をコートしているため、
裏側での第１図の（３３”）の如きクランクを誘発させ
にくい。そして裏面からの水分の侵入を防ぐことができ
る。"Effects" In the present invention, since the plasma treatment is performed at room temperature, the organic resin is not heated and deteriorated when the chip is attached to the die. It also saves the electricity and time required for heating, resulting in excellent productivity. In addition, the back side of the die is coated with a protective film just like the front side of the chip.
It is difficult to cause a crank like the one shown in Fig. 1 (33'') on the back side, and it is possible to prevent moisture from entering from the back side.

またこの電子装置のＰＣＢへの半導体による装着の際、
モールド材が加熱により膨れてしまうことを防ぐことが
できた。Also, when mounting this electronic device on a PCB using a semiconductor,
It was possible to prevent the mold material from swelling due to heating.

本発明における保護膜は窒化珪素膜とした。しかしこれ
はＤＬＣ（ダイヤモンド・ライク・カーボン）膜、酸化
珪素膜、その他の絶縁膜の単層または多層膜であっても
よい。The protective film in the present invention was a silicon nitride film. However, this may be a single layer or multilayer film of a DLC (diamond-like carbon) film, a silicon oxide film, or other insulating film.

さらに本発明において、電子部品チップは半導体素子と
して示したが、その他、抵抗、コンデンサであってもよ
く、ボンディングもワイヤボンディングのみならずフリ
ップチップボンディング、ハンダバンプボンディングで
もよい。Further, in the present invention, the electronic component chip is shown as a semiconductor element, but it may also be a resistor or a capacitor, and the bonding may be not only wire bonding but also flip chip bonding or solder bump bonding.

本発明において、チップの大きさが大きくなってダイを
用いることなしにモールドする場合がある。しかしその
場合も基体としてのリードフレーム、チップのすべてを
覆って保護膜を設けることは有効である。In the present invention, there are cases where the size of the chip becomes large and it is molded without using a die. However, even in that case, it is effective to provide a protective film covering all of the lead frame as a base and the chip.

上述した説明においては、リードフレーム半導体チップ
を載置した場合について述べて・が、本発明は特にデュ
アルインライン型のりフレームに限るものではなく、フ
ラットバラのリードフレームおよびその他のリードフレ
に対しても同様の機能を持つものであっても様の効果が
期待できるものである。In the above explanation, the case where a semiconductor chip is mounted on a lead frame is described. However, the present invention is not limited to a dual in-line type glue frame, but can be similarly applied to a flat individual lead frame and other lead flexible frames. Similar effects can be expected even if the product has the following functions.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明のデュアル・イン・ラインラスチック・
パッケージ半導体装置を示す。 第２図は本発明方法を実施するためのプラ気相反応装置
の概要を示す。 第３図は第２図の装置のうちの基体部の拡を示す。Figure 1 shows the dual-in-line plastic of the present invention.
A packaged semiconductor device is shown. FIG. 2 shows an outline of a plastic gas phase reactor for carrying out the method of the present invention. FIG. 3 shows an enlarged view of the base portion of the device of FIG.

Claims (1)

【特許請求の範囲】 １、リードフレーム上に電子部品チップをボンディング
した電子装置を有する基板または該基板を集合させた基
体を覆って保護膜形成を行うに際し、一対の電極間にグ
ロー放電により作られたプラズマ内に前記基板または基
体を配設せしめ、前記基板または基体の裏面および前記
電子部品、ボンディング部およびその周辺の表面に前記
保護膜形成を行うことを特徴とする電子装置作製方法。 ２、リードフレーム上に電子部品チップをボンディング
した電子装置を有する基板または該基板を集合させた基
体上に保護膜形成を行うに際し、一対の電極間にグロー
放電により作られたプラズマ内に前記基板または基体を
配設せしめ、外部より加熱することなしに前記電子部品
、ボンディング部およびその周辺の表面に前記保護膜形
成を行うことを特徴とする電子装置作製方法。 ３、特許請求の範囲第１項において、基板または基体上
に保護膜形成を施す工程の後、樹脂封止処理を行うこと
を特徴とする電子装置作製方法。[Claims] 1. When forming a protective film over a substrate having an electronic device with an electronic component chip bonded to a lead frame or a base assembly of such substrates, a glow discharge is created between a pair of electrodes. 1. A method for manufacturing an electronic device, characterized in that the substrate or base body is disposed in the generated plasma, and the protective film is formed on the back surface of the substrate or base body, and on the surfaces of the electronic component, the bonding portion, and their surroundings. 2. When forming a protective film on a substrate having an electronic device with an electronic component chip bonded to a lead frame or on a base assembly of such substrates, the substrate is placed in plasma created by glow discharge between a pair of electrodes. Alternatively, a method for manufacturing an electronic device, characterized in that a substrate is provided and the protective film is formed on the surface of the electronic component, the bonding portion, and the surrounding area without heating from the outside. 3. A method for manufacturing an electronic device according to claim 1, characterized in that a resin sealing process is performed after the step of forming a protective film on the substrate or base body.
JP63195684A 1988-08-05 1988-08-05 Manufacture of electronic device Pending JPH01292849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63195684A JPH01292849A (en) 1988-08-05 1988-08-05 Manufacture of electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63195684A JPH01292849A (en) 1988-08-05 1988-08-05 Manufacture of electronic device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP63124360A Division JPH01292846A (en) 1988-05-19 1988-05-19 Manufacture of electronic device

Publications (1)

Publication Number Publication Date
JPH01292849A true JPH01292849A (en) 1989-11-27

Family

ID=16345279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63195684A Pending JPH01292849A (en) 1988-08-05 1988-08-05 Manufacture of electronic device

Country Status (1)

Country Link
JP (1) JPH01292849A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601323A1 (en) * 1992-12-10 1994-06-15 International Business Machines Corporation Integrated circuit chip composite
WO2004061959A1 (en) * 2002-12-18 2004-07-22 Freescale Semiconductor, Inc. Packaged ic using insulated wire
US7635664B2 (en) 2001-05-21 2009-12-22 Bayer Cropscience Ag Herbicidal substituted benzoylpyrazoles

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0601323A1 (en) * 1992-12-10 1994-06-15 International Business Machines Corporation Integrated circuit chip composite
US5656830A (en) * 1992-12-10 1997-08-12 International Business Machines Corp. Integrated circuit chip composite having a parylene coating
US7635664B2 (en) 2001-05-21 2009-12-22 Bayer Cropscience Ag Herbicidal substituted benzoylpyrazoles
WO2004061959A1 (en) * 2002-12-18 2004-07-22 Freescale Semiconductor, Inc. Packaged ic using insulated wire
US7138328B2 (en) 2002-12-18 2006-11-21 Freescale Semiconductor, Inc. Packaged IC using insulated wire

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