JPH0383331A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0383331A JPH0383331A JP22076189A JP22076189A JPH0383331A JP H0383331 A JPH0383331 A JP H0383331A JP 22076189 A JP22076189 A JP 22076189A JP 22076189 A JP22076189 A JP 22076189A JP H0383331 A JPH0383331 A JP H0383331A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- semiconductor device
- semiconductor
- electrode
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 abstract description 5
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- -1 arsenic ions Chemical class 0.000 abstract description 2
- 230000006378 damage Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000013078 crystal Substances 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体集積回路、特にＭＯ３構造の素子を有す
る半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor device having an element of MO3 structure.
従来の技術
従来、ＭＯ３構造素子と半導体装置内に形成する場合に
は、金属（電極）を半導体との間に電位差を設ける。電
位差がなければ素子としての機能を果たせないからであ
る。2. Description of the Related Art Conventionally, when forming an MO3 structure element in a semiconductor device, a potential difference is provided between a metal (electrode) and a semiconductor. This is because without a potential difference, the element cannot function.
発明が解決しようとする課題
素子の微細化に伴い、ＭＯＳ構造における絶縁膜も薄膜
化し、従来では問題とならなかったチャージアップ現象
により絶縁膜破壊が生じることが明らかとなった。Problems to be Solved by the Invention With the miniaturization of devices, the insulating film in the MOS structure has also become thinner, and it has become clear that the charge-up phenomenon, which has not been a problem in the past, causes breakdown of the insulating film.
このチャージアップ現象はプラズマ放電を利用した工程
においても発生するが、最も顕著に現れるのはイオン注
入工程である。イオン注入工程の中でも高ドーズ量や大
ビーム電流の条件の場合は、従来から問題となっており
電子シャワーを利用したチャージアップ防止策が採られ
ている。しかしながら、上記対策では微細化、薄膜化が
進んだ素子には対応できず、従来構造の半導体装置では
絶縁膜破壊が発生してしまう。This charge-up phenomenon also occurs in processes using plasma discharge, but it is most noticeable in the ion implantation process. Even in the ion implantation process, conditions such as high doses and large beam currents have long been a problem, and charge-up prevention measures using electron showers have been taken. However, the above-mentioned measures cannot cope with devices that are becoming smaller and thinner, and insulating film breakdown occurs in semiconductor devices with conventional structures.
課題を解決するための手段
上記問題点を解決するために、本発明では、ＭＯＳ （
金属−酸化シリコン−半導体）型素子を有する半導体装
置において、半導体装置内で最も広い面積の金属（電極
）で構成される素子の電極側と半導体側との電位を同等
とした。この場合、半導体装置内で最も広い面積の金属
（電極）と絶縁膜と半導体とで構成されるＭＯＳ構造に
おいて金属（電極）と半導体とを配線により連結させる
ことにより容易に同電位とすることができる。Means for Solving the Problems In order to solve the above problems, the present invention uses a MOS (
In a semiconductor device having a metal-silicon oxide-semiconductor (metal-silicon oxide-semiconductor) type element, the potentials on the electrode side and the semiconductor side of the element constituted by the metal (electrode) having the largest area in the semiconductor device were made equal. In this case, in a MOS structure consisting of a metal (electrode), an insulating film, and a semiconductor, which have the largest area in a semiconductor device, it is possible to easily make them at the same potential by connecting the metal (electrode) and the semiconductor with wiring. can.
作用
この構造をもつ半導体装置では、イオン注入工程でチャ
ージアップによる絶縁膜破壊が発生しても装置特性に影
響しない。チャージアップ現象は、半導体装置内の最も
面積の広い金属（電極）を有する素子でおこることが明
らかとなった。つまり、半導体装置内で最も広い面積の
金属（電極）で構成される素子の絶縁膜は破壊するが、
電極側と半導体側との電位を同等とすることにより絶縁
膜破壊を起こしても半導体装置が形成できることになる
。Function: In a semiconductor device having this structure, even if insulation film breakdown occurs due to charge-up during the ion implantation process, device characteristics are not affected. It has become clear that the charge-up phenomenon occurs in an element having the largest area of metal (electrode) in a semiconductor device. In other words, the insulating film of the element, which is made up of the metal (electrode) with the largest area in the semiconductor device, is destroyed;
By making the potentials on the electrode side and the semiconductor side the same, a semiconductor device can be formed even if insulation film breakdown occurs.
実施例 第１図により本発明の一実施例を説明する。Example An embodiment of the present invention will be explained with reference to FIG.
第１図（ａ）のように、Ｐ型車結晶シリコン基板１にＮ
型拡散層２および素子分離領域７を形成し、ＭＯ３型素
子の絶縁膜３，５、金属（電極）４゜６を形成する。金
属４はこの半導体装置内で最も面積の広いものである。As shown in FIG. 1(a), N
A type diffusion layer 2 and an element isolation region 7 are formed, and insulating films 3 and 5 and metal (electrodes) 4.6 of an MO3 type element are formed. The metal 4 has the largest area in this semiconductor device.
この状態で、砒素イオン８を注入する。この時Ｎ型拡散
層９を形成するが、第１図（ｂ）のように、チャージア
ップにより絶縁膜３が破壊し、ピンホール１０が生じる
。In this state, arsenic ions 8 are implanted. At this time, an N-type diffusion layer 9 is formed, but as shown in FIG. 1(b), the insulating film 3 is destroyed due to charge-up, and a pinhole 10 is generated.
本発明の構造によれば、第１図（Ｃ）に示すように、金
属（電極）４とＮ型拡散層２とは配線１１により連結さ
れるためピンホール１０によりリーク電流が発生するこ
とがない。According to the structure of the present invention, as shown in FIG. 1(C), since the metal (electrode) 4 and the N-type diffusion layer 2 are connected by the wiring 11, leakage current is not generated due to the pinhole 10. do not have.
発明の効果
本発明によれば、チャージアップによる絶縁膜の破壊や
劣化を半導体装置特性に無関係な素子でまかなうため、
従来の構造に比べ、絶縁膜の高信頼性や高歩留まりをも
たらすものである。Effects of the Invention According to the present invention, destruction and deterioration of the insulating film due to charge-up can be compensated for by elements unrelated to the characteristics of the semiconductor device.
Compared to conventional structures, this provides high reliability and high yield of insulating films.
第１図は本発明の一実施例を説明するための図である。
１・・・・・・Ｐ型シリコン基板、２，９・・・・・・
Ｎ型拡散層、３，５・・・・・・素子用絶縁膜、４，６
・・・・・・金属（電極）、７・・・・・・素子分離領
域、１０・・・・・・静電破壊により生じたピンホール
、１１・・・・・・配線、１２層間絶縁膜。FIG. 1 is a diagram for explaining one embodiment of the present invention. 1...P-type silicon substrate, 2,9...
N-type diffusion layer, 3, 5... Insulating film for element, 4, 6
...Metal (electrode), 7...Element isolation region, 10...Pinhole caused by electrostatic breakdown, 11...Wiring, 12 Interlayer insulation film.
Claims (1)
るＭＯＳ型素子の前記金属と前記金属下の素子用絶縁膜
を隔てた半導体との電位を同等とすることを特徴とする
半導体装置。1. A semiconductor device characterized in that the metal of a MOS type element constituted by a metal (electrode) having the largest area in the semiconductor device and a semiconductor separated by an element insulating film below the metal have the same potential.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22076189A JPH0383331A (en) | 1989-08-28 | 1989-08-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22076189A JPH0383331A (en) | 1989-08-28 | 1989-08-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0383331A true JPH0383331A (en) | 1991-04-09 |
Family
ID=16756134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22076189A Pending JPH0383331A (en) | 1989-08-28 | 1989-08-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0383331A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438945B1 (en) | 1998-08-10 | 2002-08-27 | Toyota Jidosha Kabushiki Kaisha | Evaporated fuel treatment device of an engine |
-
1989
- 1989-08-28 JP JP22076189A patent/JPH0383331A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6438945B1 (en) | 1998-08-10 | 2002-08-27 | Toyota Jidosha Kabushiki Kaisha | Evaporated fuel treatment device of an engine |
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