JPH0378012A - Reference voltage generating circuit - Google Patents
Reference voltage generating circuitInfo
- Publication number
- JPH0378012A JPH0378012A JP1215228A JP21522889A JPH0378012A JP H0378012 A JPH0378012 A JP H0378012A JP 1215228 A JP1215228 A JP 1215228A JP 21522889 A JP21522889 A JP 21522889A JP H0378012 A JPH0378012 A JP H0378012A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- source
- constant current
- reference voltage
- chtr
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Dram (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Control Of Electrical Variables (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体ＬＳＩ において外部電源電圧以外
の基準となる電圧を発生させる基準電圧発生回路に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit that generates a reference voltage other than an external power supply voltage in a semiconductor LSI.
第４図はＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ ５ｏｌｉｄ
−５ｔａｔｅ ｃｉｒｃｕｉｔＭｏｌ ５ｃ２２ Ｎｏ
、３． Ｔｕｎｅ １９８７の「Ａ Ｎｅｗ Ｏｕ −
ＣｈｉｐＶｏｌｔａｇ、 Ｃｏｎｖｅｒｔｅｒ ｆｏｒ
Ｓａｂｍｉｃｒｏｍｅｔｅｒ Ｈｉｇｈ−Ｄｅｎｓｉ
ｔｙＤＲＡＭ’ｓ Ｊに示された従来の基準電圧発生回
路を示す回路図である。図において（１）は定電流源発
生Ｐチャネルトランジスタ（以下チャネルをｃｈ、）ラ
ンジスタをＴｒで示す）、（２）はｐ−ｃｈ Ｔｒ 、
（３１は負荷Ｔｒ、（４）はノードＡ、［５）は出力端
子である。Figure 4 is from IEEE Journal of 5olid
-5tate circuitMol 5c22 No
, 3. Tune 1987's "A New Ou-"
Chip Voltag, Converter for
Sabmicrometer High-Densi
1 is a circuit diagram showing a conventional reference voltage generation circuit shown in tyDRAM's J. In the figure, (1) is a constant current source generating P-channel transistor (hereinafter the channel is referred to as ch, and the transistor is referred to as Tr), (2) is a p-ch Tr,
(31 is the load Tr, (4) is the node A, and [5] is the output terminal.
電源線とＧＮＤ線の間にｐ −ｃｈ Ｔｒ （２）を数
個と負荷Ｔｒ（３）が直列に接続されており、各ｐ−ｃ
ｈ Ｔｒ（２）はゲートとソースを短絡し、ｐ−ｃｈ
Ｔｒ（２）の最下段の端子ノードＡ、（４）に電源電圧
Ｖｃｃからｐ−ｃｈＴ ｒ （２）のしきい値電圧Ｖｔ
ｈＴｒの段数分だけ、減圧した電圧が発生する。ノード
Ａ１４）をゲートに接続した定電流源発生をＰ −ｃｈ
Ｔｒ （１）のソースを電流源に、ドレインを出力端
子（５）に接続する。出力端子（５）とＧＮＤ線間に負
荷Ｔｒ（３）を接続する。Several p-ch Tr (2) and load Tr (3) are connected in series between the power supply line and the GND line, and each p-ch
h Tr (2) shorts the gate and source, p-ch
From the power supply voltage Vcc to the lowest stage terminal node A of Tr (2), (4), the threshold voltage Vt of p-chTr (2)
A reduced voltage is generated by the number of hTr stages. Constant current source generation with node A14) connected to the gate is connected to P-ch
The source of Tr (1) is connected to a current source, and the drain is connected to an output terminal (5). A load Tr (3) is connected between the output terminal (5) and the GND line.
次に動作について説明する。電源電圧Ｖｃｃとノ−ドＡ
（４）間に数段直列に接続されたＰｃｈ−Ｔｒ（２１に
より、Ｐｃｈ Ｔｒ （２）のしきい値電圧ｖｔｈの段
数分だけの電圧が発生し、ノードＡ（４）をゲートに接
続した定電流源発生Ｐ−ｃｈＴｒ（１）のゲート・ソー
ス間にと配電圧が常に印加される。ここで上記電圧を定
電流源発生Ｐ−ｃｈ Ｔｒ（１１のソース・ドレイン間
にかかるドレイン電圧ＶＤＳにくらべ小さくなるように
設定すれば、定電流源発生Ｐ−ｃｈＴｒ（１）は常に飽
和領域で動作する。これにより電源電圧Ｖｃｃが数Ｖ程
度変動しても、定電流源発生Ｐ−ｃｈＴｒ（１１の飽和
領域の動作より、定電流源発生Ｐ−ｃｈＴｒ（１１に流
れる電流ＩＤＳはほとんど変動しない。第５図は上記ド
レイン電圧ＩＶＤｓＩに対する電流＋１ＤｓＩの変化を
示すグラフである。電流ＩＤＳを負荷Ｔｒ（３１に流し
て、所定の電圧が出力端子（５）とＧＮＤ線間に発生す
る。しかし、上記飽和領域において、ソース・ドレイン
間電圧ＶＤＳが増加する。すなわち電源電圧ＶＣＣが高
くなるにつれて、ソース・ドレイン間に流れる電流ＩＤ
Ｓはわずかながら増加してゆく。Next, the operation will be explained. Power supply voltage Vcc and node A
(4) The Pch-Tr (21) connected in series in several stages generates a voltage equal to the number of stages of the threshold voltage vth of Pch Tr (2), and the node A (4) is connected to the gate. A distribution voltage is always applied between the gate and source of the constant current source generated P-ch Tr (1).Here, the above voltage is applied as the drain voltage VDS applied between the source and drain of the constant current source generated P-ch Tr (11). If set to be smaller than the constant current source generated P-chTr(1), the constant current source generated P-chTr(1) always operates in the saturation region.As a result, even if the power supply voltage Vcc fluctuates by several volts, the constant current source generated P-chTr(1) always operates in the saturation region. 11, the current IDS flowing through the constant current source generated P-chTr (11) hardly changes. FIG. 5 is a graph showing the change in current +1DsI with respect to the drain voltage IVDsI. (31, a predetermined voltage is generated between the output terminal (5) and the GND line. However, in the saturation region, the source-drain voltage VDS increases. That is, as the power supply voltage VCC increases, the source・Current ID flowing between drains
S increases slightly.
これにより電源電流Ｖｃｃの変動により出力端子（５）
に発生する基準電圧は変動することになる。This causes the output terminal (5) to change due to fluctuations in the power supply current Vcc.
The reference voltage generated will vary.
従来の基準電圧発生回路は、飽和領域で動作させた定電
流源発生Ｐ−ｃｈＴｒ を定電流源として利用し、こ
れを所定の負荷に流して基準電圧を得るが、電源電圧の
変動により電流源が変動する。この電流源を従来の回路
ではＰ−ｃｈＴｒで構成しているため１つしか接続する
ことができず、ｗＬ沖電電圧変動に依存した基準電圧の
変動が大きいことが問題であった。Conventional reference voltage generation circuits use a constant current source generated P-chTr operated in the saturation region as a constant current source, and supply this to a predetermined load to obtain a reference voltage. However, due to fluctuations in the power supply voltage, the current source changes. In the conventional circuit, this current source is configured with a P-chTr, so only one can be connected, and the problem is that the reference voltage fluctuates greatly depending on the wL Oki electric voltage fluctuation.
この発明は上記のような問題点を解消するためになされ
たもので電流源となるｎ−ｃｈＴｒを数段直列に接続す
ることにより、飽和領域におけるソース・ドレイン間電
圧の変動（電源電圧の変動）に対する飽和電流の変動を
緩和させ、より安定な定電流源を作り、これを所定の負
荷に流して基準電圧を発生させることを目的とする。This invention was made to solve the above problems, and by connecting several stages of n-chTrs serving as current sources in series, fluctuations in source-drain voltage in the saturation region (fluctuations in power supply voltage) can be reduced. ), the purpose is to create a more stable constant current source, and to generate a reference voltage by passing this through a predetermined load.
この発明にかかる基準電圧発生回路は、ｂｉｏｓＴｒの
しきい値電圧を利用して、ソース電圧より数ｖｔｈ高い
ゲート電圧を常に印加し、飽和領域で動作させたｎ−ｃ
ｈＴｒを定電流源としこの定電流源を数段直列に接続し
、ソース・ドレイン電圧に対する飽和電流の変動を緩和
させ、より安定な定電流椋を作り、基準電圧を発生させ
るものである。The reference voltage generation circuit according to the present invention uses the threshold voltage of the biosTr to constantly apply a gate voltage several vth higher than the source voltage, and operates in the saturation region.
The hTr is used as a constant current source, and several stages of the constant current sources are connected in series to alleviate fluctuations in saturation current with respect to source-drain voltage, create a more stable constant current, and generate a reference voltage.
この発明における基準電圧発生回路は、ＨＯＳ Ｔｒの
しきい値電圧を利用して、常にソース電圧より数ｖｔｈ
高いゲート電圧を印加させ、飽和領域で動作させるｎ−
ｃｈＴｒを数段直列に接続し、これを定電流源とするこ
とにより、電源電圧の変動に対する定電流源の変動を緩
和させ、より安定な定電流源を作り、基準電圧を発生す
る。The reference voltage generation circuit in this invention utilizes the threshold voltage of the HOS Tr and is always several vth higher than the source voltage.
Apply a high gate voltage and operate in the saturation region n-
By connecting several stages of chTr in series and using this as a constant current source, fluctuations in the constant current source due to fluctuations in the power supply voltage are alleviated, a more stable constant current source is created, and a reference voltage is generated.
以下、この発明の一実施列を図について説明する。第１
図は基準電圧発生回路の回路図である。Hereinafter, one embodiment of the present invention will be explained with reference to the drawings. 1st
The figure is a circuit diagram of a reference voltage generation circuit.
図において（２）はＰ−ｃｈＴｒ（５１は出力端子、（
６）は定電流源発生ｎ−ｃｈＴｒ（７１は負荷抵抗、（
８）は定電圧回路である。この基準電圧発生回路は、電
源線とＧＮＤ線の間に定電流源発生ｎ−ｃｈ Ｔｒ （
６１２段と負荷抵抗（７）を図のように直列に接続する
。各定電流源発生ｎ−ｃｈ Ｔｒ（６１のゲート・ソー
ス間にはゲート・ソース間の電圧を一定に保つ定電圧回
路（８）が接続されている。定電圧回路（８）の構成は
ｍｏｓ ｔｒのしきい値電圧を利用するものであり、電
源線とＧＮＤ線間に負荷抵抗（７）、数段のＰ−ｃｈＴ
ｒ（２１を直列に接続する。In the figure, (2) is a P-chTr (51 is an output terminal, (
6) is a constant current source generating n-chTr (71 is a load resistance, (
8) is a constant voltage circuit. This reference voltage generation circuit generates a constant current source between the power supply line and the GND line.
Connect the 612 stage and the load resistor (7) in series as shown. A constant voltage circuit (8) that keeps the voltage between the gate and source constant is connected between the gate and source of each constant current source generating n-ch Tr (61).The configuration of the constant voltage circuit (8) is MOS. It utilizes the threshold voltage of tr, and requires a load resistor (7) between the power supply line and the GND line, and several stages of P-chT.
r(21 are connected in series.
ドレインがＧＮＤ線に接続されている最下段のＰ ｃｈ
−ｔｒ （２１のゲートは、定電流源発生ｎ−ｃｈＴ
ｒ（６）のソースと接続されている。それ以外のＰ−ｃ
ｈＴｒ（２）はゲート・ドレインを短絡し、最丘段のｐ
−ｃｈＴ ｒ （２１のソースは定電流源発生ｎ−ｃｈ
ｔｒ（６）のゲートとも接続されている。ここで負荷抵
抗（７）は、定電圧回路（８）の消費電流をおさえるた
めに接続されている。The bottom Pch whose drain is connected to the GND line
-tr (The gate of 21 is a constant current source generating n-chT
Connected to the source of r(6). Other P-c
hTr(2) short-circuits the gate and drain, and connects the highest p
-chT r (The source of 21 is a constant current source generated n-ch
It is also connected to the gate of tr(6). Here, the load resistor (7) is connected to suppress the current consumption of the constant voltage circuit (8).
次に動作について説明する。Next, the operation will be explained.
負荷抵抗（７）は、定電流源発生ｎ−ｃｈＴｒ（６１２
段で発生した定電流が流れ、所定の基準電圧が出力端子
（５）に発生するように設定する。The load resistance (7) is a constant current source generating n-chTr (612
Settings are made so that a constant current generated in the stage flows and a predetermined reference voltage is generated at the output terminal (5).
直列に接続された定電流源発生ｎ−ｃｈＴｒ（６）のゲ
ート・ソース間には各々定電圧源で使用されたｐ−ｃｈ
ｔｒ（２１のしきい値電圧ｖｔｈ の段数分の電圧が常
に段加される。これにより定電流源発生ｎ −ｃｈ Ｔ
ｒ （６１は飽和領域で動作し、ソース・ドレイン間電
圧にほとんど依存しない定電流源となるが２つの定電流
源発生ｎ−ｃｈ ｔｒ（６１を直列に接続することによ
り、ソース・ドレイン電圧に対する変動に対する。定電
流の変動をより緩和することができる。これより上記定
電流源に接続された負荷抵抗（７）に発生する電圧、す
なわち出力端子（５）に出力される基準電圧は電源電圧
Ｖｃｃの変動による電圧変動を緩和することができ、よ
り安定な基準電圧を発生することが可能となる。第２図
は基準電圧発生回路の外部電源電圧Ｖｃｃに対する基準
電圧の変動をシミュレーションにより求めた結果を示し
たグラフであって、第１図の回路の特性を実線で示し、
比較のため第４図の回路の特性を破線で示す。ここでこ
の回路は外部電源電圧Ｖｃｃ ５Ｖに対して基準電圧３
．３ｖを供給するものである。Between the gate and source of the constant current source generating n-chTr (6) connected in series are the p-ch transistors used in the constant voltage source, respectively.
The voltage corresponding to the number of stages of the threshold voltage vth of tr(21) is always added in stages.As a result, a constant current source is generated n -ch T
r (61 operates in the saturation region and becomes a constant current source that is almost independent of the source-drain voltage, but by connecting two constant current sources n-ch tr (61) in series, the source-drain voltage With respect to fluctuations, it is possible to further alleviate fluctuations in the constant current.From this, the voltage generated across the load resistor (7) connected to the constant current source, that is, the reference voltage output to the output terminal (5), is equal to the power supply voltage. Voltage fluctuations caused by fluctuations in Vcc can be alleviated, making it possible to generate a more stable reference voltage. Figure 2 shows the fluctuations in the reference voltage with respect to the external power supply voltage Vcc of the reference voltage generation circuit obtained by simulation. A graph showing the results, in which the characteristics of the circuit in FIG. 1 are shown as a solid line,
For comparison, the characteristics of the circuit in FIG. 4 are shown by broken lines. Here, this circuit has a reference voltage of 3 with respect to the external power supply voltage Vcc of 5V.
．． It supplies 3v.
第２図に示すごとくこの発明による発生基準電圧はＶＣ
Ｃの変化に対してより安定な基準電圧となっていること
がわかる。As shown in FIG. 2, the generated reference voltage according to the present invention is VC
It can be seen that the reference voltage is more stable against changes in C.
またＬ記実施例では直列に接続された定電流源発生ｎ−
ｃｈｔｒ（６１の段数が２段であったが、それ以上の段
数を接続すれば、より効果的に、電源電圧の変動に対す
る基準電圧の変動を緩和することができる。第３図はこ
の発明の他の実施例による基準電圧発生回路の回路図で
定電流源発生ｎ−ｃｈＴｒ（６）を多段にしたと記の場
合を示す。図において（２１、（５１、（６１〜（８）
は第１図に示したものと同等である。なお、Ｊ：記実施
例では負荷は抵抗を使用したが負荷ｔｒを使用しても、
上記実施例と同様の効果を奏する。In addition, in the embodiment described in L, the constant current source generating n-
chtr (61) has two stages, but if more stages are connected, fluctuations in the reference voltage with respect to fluctuations in the power supply voltage can be more effectively alleviated. A circuit diagram of a reference voltage generation circuit according to another embodiment shows a case where the constant current source generation n-chTr (6) is multi-staged. In the figure, (21, (51, (61 to (8))
is equivalent to that shown in FIG. Note that in the example described above, a resistor was used as the load, but even if a load tr is used,
The same effects as in the above embodiment are achieved.
〔発明の効果〕
以とのようにこの発明によれば飽和領域を利用して定電
流源となるｎｃｈｔｒを直列に接続するこトニより、ソ
ース・ドレイン間の電圧変動（電源電圧の変動）による
飽和領域でのソース・ドレイン電流の変動で生ずる基準
電圧の変動を緩和し、より安定な基準電圧が得られる効
果がある。[Effects of the Invention] As described below, according to the present invention, by connecting nchtrs that serve as constant current sources in series by utilizing the saturation region, voltage fluctuations between the source and drain (power supply voltage fluctuations) can be reduced. This has the effect of alleviating fluctuations in the reference voltage caused by fluctuations in the source-drain current in the saturation region and providing a more stable reference voltage.
第１図はこの発明の一実施例による基準電圧発生回路の
回路図、第２図は第１図及び第４図の基準電圧発生回路
の基準電圧の外部電源電圧依存性を示すシミュレーショ
ンによる特性のグラフ、第３図はこの発明の他の実施例
を示す基準電圧発生回路の回路図、第４図は従来の基準
電圧発生回路を示す回路図、第５図は第４図の回路をこ
お４する定電流源発生ｐ−ｃｈＴｒのドレイン電圧多こ
対する電流の変化を示すグラフである。図艮おいて（２
１＆ｉ ｐ −ｃｈＴｒ 、 （５）は出力端子、（６
）は定電流源発生ｎ−ｃｈｔｒ（７）は負荷抵抗、（８
）は定電圧回路を示す。
なお１図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a circuit diagram of a reference voltage generation circuit according to an embodiment of the present invention, and FIG. 2 is a simulation showing the dependence of the reference voltage on the external power supply voltage of the reference voltage generation circuit of FIGS. 1 and 4. 3 is a circuit diagram of a reference voltage generation circuit showing another embodiment of the present invention, FIG. 4 is a circuit diagram showing a conventional reference voltage generation circuit, and FIG. 5 is a circuit diagram of a conventional reference voltage generation circuit. 4 is a graph showing changes in current with respect to drain voltage of a p-chTr generated by a constant current source. Illustration (2)
1&ip-chTr, (5) is the output terminal, (6
) is the constant current source generated n-chtr (7) is the load resistance, (8
) indicates a constant voltage circuit. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts.
Claims (1)
を直列に接続し、Ｐチャネルトランジスタの最終段のゲ
ートをソースに、Ｐチャネルトランジスタの初段のドレ
インをゲートに接続したｎチャネルトランジスタを数段
直列に接続し、初段のｎチャネルトランジスタのドレイ
ンを電源に、最終段のｎチャネルトランジスタのソース
を出力端子に接続し、出力端子とＧＮＤの間に負荷を接
続し、この数段を直列に接続したｎチャネルトランジス
タで発生する電流を負荷に流すことによって生ずる電圧
を出力端子に出力し、基準電圧を発生させることを特徴
とする基準電圧発生回路。Current, resistance, several stages of P-channel transistors, GND
are connected in series, the gate of the last stage of the P-channel transistor is connected to the source, and the drain of the first stage of the P-channel transistor is connected to the gate. Several stages of n-channel transistors are connected in series, and the drain of the first stage n-channel transistor is connected to the power supply. By connecting the source of the n-channel transistor in the final stage to the output terminal, connecting the load between the output terminal and GND, and allowing the current generated by the n-channel transistors connected in series in these several stages to flow through the load. A reference voltage generation circuit characterized in that it outputs a generated voltage to an output terminal to generate a reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215228A JPH0378012A (en) | 1989-08-21 | 1989-08-21 | Reference voltage generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215228A JPH0378012A (en) | 1989-08-21 | 1989-08-21 | Reference voltage generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0378012A true JPH0378012A (en) | 1991-04-03 |
Family
ID=16668832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1215228A Pending JPH0378012A (en) | 1989-08-21 | 1989-08-21 | Reference voltage generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0378012A (en) |
-
1989
- 1989-08-21 JP JP1215228A patent/JPH0378012A/en active Pending
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