JPH0376159A - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPH0376159A JPH0376159A JP1212147A JP21214789A JPH0376159A JP H0376159 A JPH0376159 A JP H0376159A JP 1212147 A JP1212147 A JP 1212147A JP 21214789 A JP21214789 A JP 21214789A JP H0376159 A JPH0376159 A JP H0376159A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline
- electrode
- capacitive element
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 230000015654 memory Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 67
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 238000001039 wet etching Methods 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 15
- 239000003990 capacitor Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004506 ultrasonic cleaning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
- H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
Landscapes
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野°〕
本願の発明は、積層容量型ＤＲＡＭと称されている半導
体メモリに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor memory called a stacked capacitor DRAM.
請求項１の発明は、上記の様な半導体メモリにおいて、
容量素子の一方の電極のトンネル状の空洞部内にも他方
の電極を形成して容量素子の容量を大きくすることによ
って、安定な動作が可能である様にしたものである。The invention according to claim 1 provides a semiconductor memory as described above,
Stable operation is made possible by forming the other electrode within the tunnel-shaped cavity of one electrode of the capacitive element to increase the capacitance of the capacitive element.
請求項２の発明は、上記の様な半導体メモリにおいて、
容量素子の一方の電極のトンネル状の空洞部内及び一方
の電極の下面下にも他方の電極を形成して容量素子の容
量を更に大きくすることによって、更に安定な動作が可
能である様にしたものである。The invention according to claim 2 provides a semiconductor memory as described above,
By forming the other electrode in the tunnel-shaped cavity of one electrode of the capacitive element and under the lower surface of one electrode to further increase the capacitance of the capacitive element, more stable operation is possible. It is something.
請求項３の発明は、上記の様な半導体メモリにおいて、
スイッチングトランジスタのゲート電極上の絶縁膜に突
起部を設け、この突起部を容量素子の一方の電極で覆い
、更にこの一方の電極を他方の電極で覆って容量素子の
容量を大きくすることによって、安定な動作が可能であ
る様にしたものである。The invention according to claim 3 provides a semiconductor memory as described above,
By providing a protrusion on the insulating film on the gate electrode of the switching transistor, covering this protrusion with one electrode of the capacitor, and then covering this one electrode with the other electrode to increase the capacitance of the capacitor, This allows for stable operation.
容量素子とスイッチングトランジスタとでメモリセルが
構成されている半導体メモリであるいわゆるＤＲＡＭが
安定に動作するためには、容量素子が大きな容量を有し
ている必要がある。In order for a so-called DRAM, which is a semiconductor memory in which a memory cell is constituted by a capacitive element and a switching transistor, to operate stably, the capacitive element must have a large capacity.
このため、容量素子のうちのスイッチングトランジスタ
に接続されている一方の電極をスイッチングトランジス
タのゲート電極上へ延ばして一方の電極と他方の電極と
の対向面積を大きくした、いわゆる積層容量型ＤＲＡＭ
が考えられている（例えば「月刊Ｓｅｍｔｃｏｎｄｕｃ
ｔｏｒ Ｗｏｒｌｄ Ｊブレスジャーナル社（１９８８
，２）ｐ、３１〜３６）。For this reason, a so-called multilayer capacitive DRAM in which one electrode of the capacitive element connected to the switching transistor is extended over the gate electrode of the switching transistor to increase the opposing area of one electrode and the other electrode.
(For example, "Monthly Semtconduc
tor World J Breath Journal Co., Ltd. (1988
, 2) p, 31-36).
しかし、上記の様な積層容量型ＤＲＡＭでも、特に、微
細化された場合は、トレンチ容量型ＤＲＡＭに比べて容
量素子の容量が小さく、α線によるソフトエラー等に対
して必ずしも強くない。However, even in the above-mentioned stacked capacitor type DRAM, especially when miniaturized, the capacitance of the capacitor element is smaller than that of the trench capacitor type DRAM, and it is not necessarily resistant to soft errors caused by α rays.
請求項１の半導体メモリでは、容量素子３５．３６の一
方の電極１８．２３がトンネル状の空洞部２５を有する
と共にこの一方の電極１８．２３の上面が略平坦に形成
されており、少なくとも前記空洞部２５内と前記上面上
とに誘電体膜２６を介して前記容量素子３５．３６の他
方の電極２７が形成されている。In the semiconductor memory according to the first aspect, one electrode 18.23 of the capacitive element 35.36 has a tunnel-shaped cavity 25, and the upper surface of this one electrode 18.23 is formed substantially flat. The other electrode 27 of the capacitive element 35, 36 is formed in the cavity 25 and on the upper surface with a dielectric film 26 interposed therebetween.
請求項２の半導体メモリでは、請求項１の半導体メモリ
の構成に加えて、容量素子３５．３６の前記一方の電極
１８．２３の下面下にも前記誘電体膜２６を介して前記
他方の電極２７が形成されている。In addition to the structure of the semiconductor memory of claim 1, in the semiconductor memory of claim 2, the other electrode is also provided under the lower surface of the one electrode 18.23 of the capacitive element 35.36 via the dielectric film 26. 27 is formed.
請求項３の半導体メモリでは、スイッチングトランジス
タ３３．３４のゲート電極１４上の絶縁膜１５．１７が
突起部１７ａを有しており、容量素子３５．３６の一方
の電極１８．４５が少なくとも前記突起部１７ａを覆っ
ており、前記容量素子３５．３６の他方の電極２７が誘
電体膜２６を介して前記一方の電極１８．４５を覆って
いる。In the semiconductor memory according to the third aspect, the insulating film 15.17 on the gate electrode 14 of the switching transistor 33.34 has a protrusion 17a, and one electrode 18.45 of the capacitive element 35.36 has at least the protrusion. The other electrode 27 of the capacitive element 35.36 covers the one electrode 18.45 with the dielectric film 26 in between.
請求項１の半導体メモリでは、容量素子３５．３６の一
方の電極１８．２３の上面上のみならず空洞部２５内に
も他方の電極２７が形成されているので、一方の電極１
８．２３と他方の電極２７との対向面積が大きく、容量
素子３５．３６の容量が大きい。In the semiconductor memory according to the first aspect, since the other electrode 27 is formed not only on the upper surface of one electrode 18.23 of the capacitive element 35.36 but also inside the cavity 25, one electrode 18.
The opposing area between the electrode 8.23 and the other electrode 27 is large, and the capacitance of the capacitive element 35.36 is large.
また、空洞部２５がトンネル状であるので、容量素子３
５．３６の容量が大きいにも拘らず、パラツル状等の構
造に比べて、容量素子３５．３６の一方の電極１８．２
３の力学的強度が大きい。Furthermore, since the cavity 25 is tunnel-shaped, the capacitive element 3
Despite the large capacitance of capacitive element 35.36, one electrode 18.2 of capacitive element 35.36 is
3 has high mechanical strength.
また、一方の電極１８．２３の上面が略平坦であるので
、他方の電極２７等の上層配線の平坦度が高い。Further, since the upper surface of one electrode 18.23 is substantially flat, the flatness of the upper layer wiring such as the other electrode 27 is high.
請求項２の半導体メモリでは、容量素子３５．３６の一
方の電極１８．２３の下面下にも他方の電極２７が形成
されているので、一方の電極１８．２３と他方の電極２
７との対向面積が更に大きく、容量素子３５．３６の容
量が更に大きい。In the semiconductor memory according to the second aspect, since the other electrode 27 is also formed under the lower surface of one electrode 18.23 of the capacitive element 35.36, one electrode 18.23 and the other electrode 2
The opposing area with 7 is even larger, and the capacitance of capacitive elements 35 and 36 is even larger.
請求項３の半導体メモリでは、容量素子３５．３６の一
方の電極上８．４５がゲート電極１４上の絶縁膜１５．
１７の突起部１７ａを覆っている分だけ、この一方の電
極１８．４５の表面積が大きい。そして、この一方の電
極１８．４５を他方の電極２７が覆っている。従って、
一方の電極１８．４５と他方の電極２７との対向面積が
大きく、容量素子３５．３６の容量が大きい。In the semiconductor memory according to the third aspect, the insulating film 15.45 on one electrode of the capacitive element 35.36 is on the gate electrode 14.
The surface area of this one electrode 18.45 is large by the extent that it covers the protrusion 17a of the electrode 17. This one electrode 18.45 is covered by the other electrode 27. Therefore,
The opposing area between one electrode 18.45 and the other electrode 27 is large, and the capacitance of the capacitive element 35.36 is large.
以下、本願の発明の第１〜第５実施例を、第１図〜第７
図を参照しながら説明する。Hereinafter, the first to fifth embodiments of the invention of the present application will be described in Figures 1 to 7.
This will be explained with reference to the figures.
第１図及び第２図が、第１実施例及びその製造工程を示
している。この第１実施例を製造するには、第１Ａ図に
示す様に、まず、ｐ−型のＳｔ基板１１に素子分離用の
Ｓｉｎ、膜１２を形成し、スイッチングトランジスタの
ゲート絶縁膜になる５ｉＯｚ膜１３を酸化によって形成
する。1 and 2 show a first embodiment and its manufacturing process. To manufacture this first embodiment, as shown in FIG. 1A, first, a Si film 12 for element isolation is formed on a p-type St substrate 11, and a 5iOz film 12, which will become the gate insulating film of the switching transistor, is formed on a p-type St substrate 11. Film 13 is formed by oxidation.
そして、スイッチングトランジスタのゲート電極つまり
ワード線になる多結晶Ｓｉ膜１４と眉間絶縁膜になるＳ
ｉＯ□膜１５とを、ＣＶＤによって順次に堆積させる。Then, the polycrystalline Si film 14 becomes the gate electrode of the switching transistor, that is, the word line, and the S film becomes the insulating film between the eyebrows.
The iO□ film 15 is sequentially deposited by CVD.
なお、多結晶Ｓｉ膜１４の代りにポリサイド層等を用い
てもよい。Note that a polycide layer or the like may be used instead of the polycrystalline Si film 14.
その後、ワード線のパターンのレジスト（図示せず）を
用いてＳｉｎｇ膜１５と多結晶Ｓｉ膜１４とを順次にパ
ターニングし、これらのＳｉｎｇ膜１５と多結晶Ｓｉ膜
１４とをマスクにしてＳｉ基板ｌｌ中にｎ−領域１６ａ
〜１６ｃを形成する。Thereafter, the Sing film 15 and the polycrystalline Si film 14 are sequentially patterned using a word line pattern resist (not shown), and the Sing film 15 and the polycrystalline Si film 14 are used as masks to form the Si substrate. n-region 16a in ll
~16c is formed.
そして、ＣＶＤによる５ｉＯｚ膜１７の堆積及びＳｉＯ
２膜１７膜上７のエッチバックを行って多結晶Ｓｉ膜１
４及びＳｉＯ２膜１５にＳｉＯ□膜１７の側壁を形成し
、更にＣＶＤによって多結晶Ｓｉ膜１８を堆積させる。Then, a 5iOz film 17 is deposited by CVD and a SiO
Polycrystalline Si film 1 is etched back on the film 17.
4 and the SiO2 film 15, and a polycrystalline Si film 18 is further deposited by CVD.
そして更に、ＳｉＯ，膜１５．１７と多結晶Ｓｉ膜１４
とをマスクにしてＳｉ基板ｌｌ中にｎ＋領域２１ａ〜２
１ｃを形成する。Furthermore, SiO film 15.17 and polycrystalline Si film 14
N+ regions 21a to 21 are formed in the Si substrate 11 using the mask as a mask.
Form 1c.
その後、ＣＶＤによってＳｉＯ，膜２２を全面に堆積さ
せ、このＳｉＯ□膜２２全２２チバックすることによっ
て、多結晶Ｓｉ膜１８上の低い領域にのみＳｉＯ□膜２
２全２２゜なお、ＳｉＯ！膜２２膜化２にＳＯＧ膜やＰ
ＳＧ膜等を用いてもよい。Thereafter, a SiO film 22 is deposited on the entire surface by CVD, and the entire SiO film 22 is chilled, so that the SiO film 22 is deposited only on the low region on the polycrystalline Si film 18.
2 Total 22°In addition, SiO! SOG film or P for film 22 film formation 2
An SG film or the like may also be used.
次に、第１Ｂ図に示す様に、ＣＶＤによって多結晶Ｓｉ
膜２３を堆積させるが、多結晶Ｓｉ膜１８上の低い領域
にはＳｉＯ□膜２２全２２れているので、多結晶Ｓｉ膜
１４同士の間の領域でも多結晶Ｓｉ膜２３は略平坦であ
る。Next, as shown in FIG. 1B, polycrystalline Si is formed by CVD.
The film 23 is deposited, but since the entire SiO□ film 22 is deposited in the low region on the polycrystalline Si film 18, the polycrystalline Si film 23 is substantially flat even in the region between the polycrystalline Si films 14. .
そして、容量素子のうちでｎゝ領域２１ｂ、２１ｃに接
続される一方の電極のパターン等に、レジスト２４をバ
ターニングする。Then, the resist 24 is patterned into the pattern of one electrode of the capacitive element connected to the n regions 21b and 21c.
次に、第１Ｃ図に示す様に、レジスト２４をマスクにし
て、ＳｉＯ□膜２２全２２するまで、多結晶Ｓｉ膜２３
に対するＲＩＢを行う。そして、レジスト２４を残した
まま、ウェットエツチングによってＳｉＯ□膜２２全２
２する。Next, as shown in FIG. 1C, using the resist 24 as a mask, the polycrystalline Si film 23 is
Perform RIB for. Then, while leaving the resist 24, the entire 2 portions of the SiO□ film 22 are etched by wet etching.
Do 2.
そして更に、レジスト２４をマスクにして多結晶Ｓｉ膜
１８に対するＲＩＥを行い、その後にレジスト２４を除
去する。従って、この時点で、多結晶Ｓｉ膜１８．２３
によってトンネル状の空洞部２５が形成されている。Further, RIE is performed on the polycrystalline Si film 18 using the resist 24 as a mask, and then the resist 24 is removed. Therefore, at this point, the polycrystalline Si film 18.23
A tunnel-shaped cavity 25 is formed by this.
次に、第１Ｄ図に示す様に、容量素子の誘電体ＩＩ！２
６を形成するが、この誘電体膜２６は空洞部２５の内表
面にも形成される。そして、容量素子の他方の電極にな
る多結晶５ｉＷｉ！２７をＣＶＤによって堆積させるが
、この多結晶Ｓｉ膜２７も空洞部２５を埋める様に堆積
する。Next, as shown in FIG. 1D, the dielectric II of the capacitive element! 2
This dielectric film 26 is also formed on the inner surface of the cavity 25. Then, polycrystalline 5iWi! becomes the other electrode of the capacitive element! 27 is deposited by CVD, and this polycrystalline Si film 27 is also deposited so as to fill the cavity 25.
その後、多結晶Ｓｉ膜２７のうちでｎ ４ ’ＩＮ域２
１ａ近傍の部分を除去する様に、ＲＩＨによって多結晶
５ｉＩｌ１２７のパターニングを行う。但し、ＲＩＥで
あるので、空洞部２５内の多結晶Ｓｉ膜２７は除去され
ない。After that, in the polycrystalline Si film 27, the n 4 'IN region 2
Polycrystalline 5iIl 127 is patterned by RIH so as to remove the portion near 1a. However, since this is RIE, the polycrystalline Si film 27 within the cavity 25 is not removed.
次に、第１Ｅ図に示す様に、ＰＳＧ膜等の眉間絶縁膜２
８を堆積させ、第１Ｅ図及び第２図に示す様に、ｎ″領
域２１ａに対応する多結晶Ｓｉ膜２３に達するコンタク
ト窓３１を層間絶縁膜２８及び誘電体１１１２６に形成
する。Next, as shown in FIG. 1E, a glabellar insulation film 2 such as a PSG film is formed.
As shown in FIGS. 1E and 2, a contact window 31 reaching the polycrystalline Si film 23 corresponding to the n'' region 21a is formed in the interlayer insulating film 28 and the dielectric 11126.
そして、Ａｆｆｉ膜３２膜堰２させ、この＾ｌ膜３２を
ピッ）ｌのパターンにバターニングする。以上の様にし
て、スイッチングトランジスタ３３．３４と容量素子３
５．３６とを有する第Ｉ実施例が製造される。Then, the Affi film 32 is formed into a film weir 2, and this ^l film 32 is patterned into a pattern of 1). As described above, the switching transistors 33 and 34 and the capacitive element 3
5.36 is manufactured.
この様な第１実施例では、空洞部２５内にも蓄電可能で
あるので容量素子３５．３６の容量が大きいにも拘らず
、空洞部２５がトンネル状であるので、パラツル状等の
構造に比べて多結晶Ｓｉ膜１８．２３の力学的強度が大
きい。従って、製造工程の途中の超音波洗浄等でも破損
されにくい。In the first embodiment, electricity can also be stored in the cavity 25, so despite the large capacitance of the capacitive elements 35 and 36, the cavity 25 is tunnel-shaped, so it is not possible to have a structure such as a parallel shape. In comparison, the mechanical strength of the polycrystalline Si films 18 and 23 is large. Therefore, it is unlikely to be damaged by ultrasonic cleaning or the like during the manufacturing process.
また、略平坦な多結晶Ｓｉ膜２３がコンタクト窓３１の
位置にも形成されているので、このコンタクト窓３１が
浅く、ＡＪ膜３２の段差被覆性がよい。Further, since the substantially flat polycrystalline Si film 23 is also formed at the position of the contact window 31, the contact window 31 is shallow and the step coverage of the AJ film 32 is good.
なお、この第１実施例の様に空洞部２５を形成しても多
結晶Ｓｉ膜２３の平坦度が低い場合は、第３図に示す様
に、更に多結晶Ｓｉ膜３７を堆積させて空洞部３８を形
成するという工程を多段に繰り返してもよい。Note that if the flatness of the polycrystalline Si film 23 is low even after forming the cavity 25 as in the first embodiment, a polycrystalline Si film 37 is further deposited to fill the cavity as shown in FIG. The process of forming the portion 38 may be repeated in multiple stages.
第４図は、第２実施例の製造工程を示している。FIG. 4 shows the manufacturing process of the second embodiment.
この第２実施例は、多結晶Ｓｉ膜１８の下面下にも誘電
体膜２６と多結晶Ｓｉ膜２７とが形成されていることを
除いて、上述の第１実施例と実質的に同様の構成を有し
ている。従って、この第２実施例も平面的に見ると略第
２図の通りである。This second embodiment is substantially the same as the first embodiment described above, except that a dielectric film 26 and a polycrystalline Si film 27 are also formed under the lower surface of the polycrystalline Si film 18. It has a structure. Therefore, this second embodiment is also approximately as shown in FIG. 2 when viewed from above.
この様な第２実施例を製造するには、第４Ａ図に示す様
に、５ｉｎ２膜１７の側壁を形成した後で多結晶Ｓｉ膜
１８を堆積させる前に、薄いＳｉＯ□膜４１及びＳｉ３
Ｎｍ膜４２と比較的厚いＳｉＯ□膜４３とをＣＶＤで順
次に堆積させ、ｎ＋領域２１ａ、２１ｂ等に達するコン
タクト窓４４ａ、４４ｂ等を膜４１〜４３に形成してお
く。To manufacture such a second embodiment, as shown in FIG. 4A, after forming the sidewalls of the 5in2 film 17 and before depositing the polycrystalline Si film 18, a thin SiO□ film 41 and a Si3
A Nm film 42 and a relatively thick SiO□ film 43 are sequentially deposited by CVD, and contact windows 44a, 44b, etc. reaching the n+ regions 21a, 21b, etc. are formed in the films 41-43.
そして、第１実施例の場合と同様に多結晶Ｓｉ膜１８に
対するＲＩＥまで行った後に、５ｉ（ｈ膜４３に対する
ウェットエツチングを行う。この結果、第４Ｂ図に示す
様に、多結晶Ｓｉ膜１８とＳｉ３Ｎ４膜４２との間に空
隙が形成された状態で、多結晶Ｓｉ膜１８．２３によっ
てトンネル状の空洞部２５が形成される。Then, as in the case of the first embodiment, after performing RIE on the polycrystalline Si film 18, wet etching is performed on the 5i(h film 43. As a result, as shown in FIG. 4B, the polycrystalline Si film 18 With a gap formed between the polycrystalline Si film 18 and the Si3N4 film 42, a tunnel-shaped cavity 25 is formed by the polycrystalline Si film 18.23.
なお、ＳｉＪ、膜４２はＳｉＯ□膜４３のウェットエツ
チングに対するストッパであり、５ｉｎｔ膜４１はＳｉ
、Ｎ、膜４２がＳｉ基板１１に直接に接して大きなスト
レスが生じるのを緩和するためのものである。Note that the SiJ film 42 is a stopper for wet etching of the SiO□ film 43, and the 5-int film 41 is a
, N, is used to alleviate the large stress that occurs when the film 42 comes into direct contact with the Si substrate 11.
次に、第１実施例の場合と同様に誘電体膜２６と多結晶
Ｓｉ膜２７とを形成するが、第４ｃ図に示す様に、これ
らの膜２６．２７は多結晶Ｓｉ膜１８の下面下にも形成
される。Next, a dielectric film 26 and a polycrystalline Si film 27 are formed in the same manner as in the first embodiment, but as shown in FIG. It is also formed below.
その後、第１実施例の場合と同様な工程を経て、この第
２実施例が製造される。Thereafter, the second embodiment is manufactured through the same steps as in the first embodiment.
第５図は、第３実施例の製造工程を示している。FIG. 5 shows the manufacturing process of the third embodiment.
この第３実施例を製造するには、第５Ａ図に示す様に、
ＳｉＯ□膜１５主１５上多結晶Ｓｉ膜４５を堆積させ、
膜１４．１５．４５をワード線のパターンにバターニン
グし、これらの膜１４．１５．４５をマスクにしてｎ−
領域１６ａ〜１６ｃを形成するための不純物をＳｉ基板
１１中へイオン注入する。To manufacture this third embodiment, as shown in FIG. 5A,
A polycrystalline Si film 45 is deposited on the main SiO□ film 15,
The films 14.15.45 were patterned into word line patterns, and these films 14.15.45 were used as masks to form n-
Impurity ions for forming regions 16a to 16c are implanted into Si substrate 11.
なお、ＳｉＯ□膜１５膜材５として、膜質のよい５ｔＯ
２膜を形成することができるＴＥ０１ （、テトラエチ
ルオルソシリケート）を用いれば、Ｓｉｎ、膜１５は薄
くてもよい。従って、Ｓｉｎｇ膜１５上に多結晶Ｓｉ膜
４５を堆積させても、ｎ−，６１域１６ａ〜１６Ｃに対
するコンタクト窓が従来よりも深くなることはない。In addition, as the SiO□ film 15 film material 5, 5tO having good film quality is used.
If TE01 (tetraethyl orthosilicate), which can form two films, is used, the film 15 of Sin may be thin. Therefore, even if the polycrystalline Si film 45 is deposited on the Sing film 15, the contact window for the n-, 61 regions 16a to 16C does not become deeper than before.
その後、多結晶Ｓｉ膜４５．１４及びＳｉＯ□膜１５膜
材５ｎｇ膜１７の側壁を形成する。従って、第５Ａ図か
らも明らかな様に、ＳｉＯ□膜１５膜材５結晶Ｓｉ膜１
４から見れば、多結晶Ｓｉ膜４５の膜厚に相当する分だ
けＳｉｎ、膜１７に突起部１７ａが形成されたことにな
る。Thereafter, the side walls of the polycrystalline Si film 45.14, the SiO□ film 15 and the film 17 each having a film material of 5 ng are formed. Therefore, as is clear from FIG. 5A, the SiO□ film 15 film material 5 crystalline Si film 1
4, the protrusion 17a is formed on the Si film 17 by an amount corresponding to the thickness of the polycrystalline Si film 45.
次に、第５Ｂ図に示す様に、多結晶Ｓｉ膜１８の堆積と
ｎ″領域２１ａ〜２１ｃを形成するための不純物のイオ
ン注入とイオン注入した不純物に対するアニールとを順
次に行う。Next, as shown in FIG. 5B, the deposition of the polycrystalline Si film 18, the ion implantation of impurities for forming the n'' regions 21a to 21c, and the annealing of the implanted impurities are sequentially performed.
次に、第５Ｃ図に示す様に、ＳｉＯ□膜１５膜材５する
までＲＩＨによって多結晶Ｓｉ膜１８．４５のバターニ
ングを行う。この時、多結晶Ｓｉ膜１８．４５とＳｉＯ
□膜１５膜材５ツチング選択比が大きいので、多結晶Ｓ
ｉ膜１８．４５に対するオーバエツチング時の安定性が
高い。Next, as shown in FIG. 5C, the polycrystalline Si film 18.45 is patterned by RIH until the SiO□ film 15 is formed. At this time, polycrystalline Si film 18.45 and SiO
□Membrane 15 Membrane material 5 Polycrystalline S
High stability during overetching with respect to i-film 18.45.
その後は、第５Ｄ図に示す様に、第１実施例等の場合と
同様に、誘電体膜２６の形成や多結晶Ｓｉ膜２７のバタ
ーニング等を行う。Thereafter, as shown in FIG. 5D, formation of the dielectric film 26 and patterning of the polycrystalline Si film 27 are performed in the same manner as in the first embodiment.
以上の様にして製造した第３実施例では、多結晶Ｓｉ膜
１８と多結晶Ｓｉ膜４５とがＳｉｎ、膜１７の突起部１
７ａを覆っているので、多結晶Ｓｉ膜１８の膜厚が薄く
ても、突起部１７ａの高さ分つまり多結晶Ｓｉ膜４５の
膜厚分だけ多結晶Ｓｉ膜１８．４５の表面積が大きい。In the third embodiment manufactured as described above, the polycrystalline Si film 18 and the polycrystalline Si film 45 are made of Sin, and the protrusion 1 of the film 17 is
7a, even if the polycrystalline Si film 18 is thin, the surface area of the polycrystalline Si film 18.45 is large by the height of the protrusion 17a, that is, by the thickness of the polycrystalline Si film 45.
従って、多結晶Ｓｉ膜１８．４５と多結晶Ｓｉ膜２７と
の対向面積が大きく、容量素子３５．３６の容量が大き
い。Therefore, the opposing area between the polycrystalline Si film 18.45 and the polycrystalline Si film 27 is large, and the capacitance of the capacitive element 35.36 is large.
第６図は、第４実施例の製造工程を示している。FIG. 6 shows the manufacturing process of the fourth embodiment.
この第４実施例を製造するには、第６Ａ図に示す様に、
５ｉ０２膜１７を堆積させた後、引き続いて多結晶Ｓｉ
膜４６を堆積させる。To manufacture this fourth embodiment, as shown in FIG. 6A,
After depositing the 5i02 film 17, polycrystalline Si is subsequently deposited.
A film 46 is deposited.
次に、第６Ｂ図に示す様に、多結晶Ｓｉ膜４６をＲＩＥ
してＳｉｎｇ膜１７膜条７晶Ｓｉ膜４６の側壁を形成し
、この状態で５ｉＯｚ膜１７．１３をＲＩＥする。この
結果、５ｉｆｔ膜１５上のＳｉｎｇ膜１７膜条７される
が、多結晶Ｓｔ膜４６下のＳｉＯ□膜１７は除去されな
い。Next, as shown in FIG. 6B, the polycrystalline Si film 46 is subjected to RIE.
The sidewalls of the Sing film 17 and the 7-crystalline Si film 46 are then formed, and in this state, the 5iOz film 17.13 is subjected to RIE. As a result, the Sing film 17 on the 5ift film 15 is removed, but the SiO□ film 17 under the polycrystalline St film 46 is not removed.
従って、ＳｉＯ□膜１５及び多結晶Ｓｉ膜１４の両側方
に５ｔ（ｈ膜１７の突起部１７ａが形成され、また側壁
である多結晶Ｓｔ膜４６の厚さ分だけ５ｉＯｚ膜１７の
基底部の幅が広くなる。Therefore, protrusions 17a of the 5T(h film 17) are formed on both sides of the SiO□ film 15 and the polycrystalline Si film 14, and the base of the 5iOz film 17 is formed by the thickness of the polycrystalline St film 46, which is the side wall. The width becomes wider.
次に、多結晶Ｓｉ膜４６をライトエツチングした後、第
６Ｃ図に示す様に、多結晶Ｓｔ膜１８を堆積させる。そ
して、ｎ＋領域２１ａ〜２１Ｃを形成するための不純物
のイオン注入とイオン注入した不純物に対するアニール
とＲＩＥによる多結晶Ｓｔ膜１８のパターニングとを行
う。Next, after light etching the polycrystalline Si film 46, a polycrystalline St film 18 is deposited as shown in FIG. 6C. Then, ion implantation of impurities for forming n+ regions 21a to 21C, annealing of the implanted impurities, and patterning of polycrystalline St film 18 by RIE are performed.
その後は、第６Ｄ図に示す様に、第１実施例等の場合と
同様に、誘電体膜２６の形成や多結晶Ｓｉ膜２７のバタ
ーニング等を行う。Thereafter, as shown in FIG. 6D, the formation of the dielectric film 26 and the patterning of the polycrystalline Si film 27 are performed in the same manner as in the first embodiment.
以上の様にして製造した第４実施例でも、多結晶Ｓｔ膜
１８がＳｉｎｇ膜１７膜条７部１７ａを覆っているので
、多結晶Ｓｔ膜１８の膜厚が薄くても、突起部１７ａの
高さ分だけ多結晶Ｓｉ膜１８の表面積が大きい。従って
、多結晶Ｓｉ膜１８と多結晶Ｓｔ膜２７との対向面積が
大きく、容量素子３５．３６の容量が大きい。In the fourth embodiment manufactured as described above, the polycrystalline St film 18 covers the film strip 7 portion 17a of the Sing film 17, so even if the polycrystalline St film 18 is thin, the protrusion 17a is The surface area of the polycrystalline Si film 18 is large by the height. Therefore, the opposing area between the polycrystalline Si film 18 and the polycrystalline St film 27 is large, and the capacitance of the capacitive elements 35 and 36 is large.
また、側壁である多結晶Ｓｉ膜４６の厚さ分だけ５ｉｎ
２膜１７の基底部の幅が広く、しかもＳｉｎｇ膜１７膜
条７で多結晶Ｓｉ膜４６に覆われている面は堆積時のま
までありＲＩＥを受けていないので、ＳｉＯ□膜１７の
耐圧が高い。Also, the thickness of the polycrystalline Si film 46, which is the side wall, is 5 inches.
The width of the base of the SiO film 17 is wide, and the surface covered with the polycrystalline Si film 46 in the Sing film 17 film strip 7 remains as it was when deposited and has not been subjected to RIE. is high.
第７図は、第５実施例の製造工程を示している。FIG. 7 shows the manufacturing process of the fifth embodiment.
この第５実施例は、第５図に示した第３実施例と第６図
に示した第４実施例とを融合させた構造を有している。This fifth embodiment has a structure that is a combination of the third embodiment shown in FIG. 5 and the fourth embodiment shown in FIG.
即ち、この第５実施例を製造するには、第７Ａ図に示す
様に、多結晶Ｓｔ膜４５とＳｉｎｇ膜１５膜対５晶Ｓｉ
膜１４とをワード線のパターンにパターニングした状態
で、ＳｉＯ□膜１７と多結晶Ｓｉ膜４６とを堆積させる
。That is, in order to manufacture this fifth embodiment, as shown in FIG. 7A, the polycrystalline St film 45 and the Sing film 15 are paired with the
With the film 14 patterned into a word line pattern, the SiO□ film 17 and the polycrystalline Si film 46 are deposited.
その後、第７Ｂ図に示す様に多結晶Ｓｔ膜４６の側壁を
形成し、第７Ｃ図に示す様にＳｉｎｇ膜１７膜条７をＲ
ＩＥＬ、第７Ｄ図に示す様に多結晶Ｓｔ膜１８の堆積及
び多結晶５ｉＮ１８．４５のバターニング等を行う。Thereafter, as shown in FIG. 7B, the side walls of the polycrystalline St film 46 are formed, and as shown in FIG. 7C, the film strips 7 of the Sing film 17 are
IEL, as shown in FIG. 7D, a polycrystalline St film 18 is deposited and polycrystalline 5iN 18.45 is patterned.
以上の様な第５実施例では、ＳｉＯ□膜１７のＲＩＥ時
に、多結晶ｓｔ膜４６ ）ｔ１１壁カ５ｉＯｔｌａ １
７０）側壁に対するストッパとなり、且つ多結晶Ｓｉ膜
４５がＳｉｎｇ膜１５膜対５るストッパとなっているの
で、ＳｉＯ□膜１７のＲＩＥに際してのオーバエツチン
グ時の安定性が高い。In the fifth embodiment as described above, during RIE of the SiO□ film 17, the polycrystalline st film 46)t11 wall
70) Since the polycrystalline Si film 45 acts as a stopper for the side wall and also serves as a stopper for the Sing film 15, stability during overetching during RIE of the SiO□ film 17 is high.
なお、この第５実施例における多結晶Ｓｉ膜４５は、上
述の様にエツチングに対するストッパを主な目的として
いるので、第５図に示した第３実施例における多結晶Ｓ
ｉ膜４５より薄くてもよい。The polycrystalline Si film 45 in this fifth embodiment is mainly intended as a stopper for etching as described above, so the polycrystalline Si film 45 in the third embodiment shown in FIG.
It may be thinner than the i-film 45.
請求項１〜３の何れの半導体メモリでも、容量素子の容
量が大きいので、α線によるソフトエラー等に対して強
く、安定な動作が可能である。In any of the semiconductor memories according to the first to third aspects of the invention, since the capacitance of the capacitive element is large, it is resistant to soft errors caused by alpha rays and stable operation is possible.
また、請求項１の半導体メモリでは、容量素子の一方の
電極の力学的強度が大きいので製造過程での破損が少な
く、しかも容量素子の一方の電極よりも上層の配線の平
坦度も高いので、製造が容易である。Further, in the semiconductor memory according to the first aspect, since the mechanical strength of one electrode of the capacitive element is high, there is less damage during the manufacturing process, and the flatness of the wiring in the upper layer is also higher than that of the one electrode of the capacitive element. Easy to manufacture.
第１図は本願の発明の第１実施例の製造工程を順次に示
しており第２図の７−Ｉ線に沿う側断面図、第２図は第
１実施例の平面図、第３図は第１実施例の変形例の製造
工程の途中を示す側断面図、第４図〜第７図は夫々第２
〜第５実施例の製造工程を順次に示す側断面図である。
なお図面に用いた符号において、
１４・−−−−−・−−−一−−−・・・−・多結晶Ｓ
ｉ膜１５−・−・−−−−−−−−−−−−−５ｉ Ｏ
を膜１７’−−−−−・ ・・ＳｉＯ２膜１７ａ
・突起部
１８−−−−−−−−−一 多結晶Ｓｉ膜２３
−−−−−−・−多結晶Ｓｉ膜２５−−−−−−−−−
・−−−一一−−−−・空洞部２６−・・−・−−−−
一−・−−一−−誘電体膜２７・−−−−−−−・−・
−・−多結晶Ｓｉ膜３３．３４− ・−・−・スイッチ
ングトランジスタ３５．３６ 容量素子
４５−−−−−−−−−−−−・−・・−・多結晶Ｓｉ
膜である。1 is a side sectional view taken along line 7-I in FIG. 2, a plan view of the first embodiment, and FIG. 3 is a side sectional view taken along line 7-I in FIG. is a side sectional view showing the middle of the manufacturing process of a modification of the first embodiment, and FIGS.
- It is a sectional side view which shows the manufacturing process of 5th Example sequentially. In addition, in the symbols used in the drawings, 14.
i film 15−・−・−−−−−−−−−−−5i O
The film 17'-----...SiO2 film 17a
・Protrusion 18-----1 Polycrystalline Si film 23
----------Polycrystalline Si film 25-----
・---11-----Cavity part 26-----
1−・−−1−−Dielectric film 27・−−−−−−・−・
---Polycrystalline Si film 33.34---Switching transistor 35.36 Capacitive element 45----------------Polycrystalline Si
It is a membrane.
Claims (1)
ルが構成されており、前記容量素子の一方の電極が前記
スイッチングトランジスタのゲート電極上へ延びている
半導体メモリにおいて、前記一方の電極がトンネル状の
空洞部を有すると共にこの一方の電極の上面が略平坦に
形成されており、 少なくとも前記空洞部内と前記上面上とに誘電体膜を介
して前記容量素子の他方の電極が形成されている半導体
メモリ。 ２、前記一方の電極の下面下にも前記誘電体膜を介して
前記他方の電極が形成されている請求項１記載の半導体
メモリ。 ３、容量素子とスイッチングトランジスタとでメモリセ
ルが構成されており、前記容量素子の一方の電極が前記
スイッチングトランジスタのゲート電極上へ延びている
半導体メモリにおいて、前記ゲート電極上の絶縁膜が突
起部を有しており、 前記一方の電極が少なくとも前記突起部を覆っており、 前記容量素子の他方の電極が誘電体膜を介して前記一方
の電極を覆っている半導体メモリ。[Claims] 1. In a semiconductor memory in which a memory cell is constituted by a capacitive element and a switching transistor, and one electrode of the capacitive element extends onto a gate electrode of the switching transistor, the one electrode has a tunnel-like cavity, and the upper surface of this one electrode is formed substantially flat, and the other electrode of the capacitive element is formed at least within the cavity and on the upper surface with a dielectric film interposed therebetween. semiconductor memory. 2. The semiconductor memory according to claim 1, wherein the other electrode is also formed under the lower surface of the one electrode with the dielectric film interposed therebetween. 3. In a semiconductor memory in which a memory cell is constituted by a capacitive element and a switching transistor, and one electrode of the capacitive element extends onto the gate electrode of the switching transistor, the insulating film on the gate electrode has a protrusion. A semiconductor memory, wherein the one electrode covers at least the protrusion, and the other electrode of the capacitive element covers the one electrode with a dielectric film interposed therebetween.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1212147A JPH0376159A (en) | 1989-08-18 | 1989-08-18 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1212147A JPH0376159A (en) | 1989-08-18 | 1989-08-18 | Semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0376159A true JPH0376159A (en) | 1991-04-02 |
Family
ID=16617669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1212147A Pending JPH0376159A (en) | 1989-08-18 | 1989-08-18 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0376159A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03178115A (en) * | 1989-12-06 | 1991-08-02 | Matsushita Electric Ind Co Ltd | Manufacture of solid electrolytic capacitor |
| JPH04196481A (en) * | 1990-11-28 | 1992-07-16 | Nec Corp | Semiconductor storage device |
| JPH04225557A (en) * | 1990-04-03 | 1992-08-14 | Electron & Telecommun Res Inst | Dram cell of standard structure |
| JPH04298074A (en) * | 1990-10-25 | 1992-10-21 | Hyundai Electron Ind Co Ltd | Dram provided with stacked capacitor and manufacture thereof |
| JPH06181295A (en) * | 1991-12-18 | 1994-06-28 | Samsung Electron Co Ltd | Semiconductor memory device and its manufacture |
| JPH06232366A (en) * | 1992-12-31 | 1994-08-19 | Hyundai Electron Ind Co Ltd | Manufacture of laminated capacitor for semiconductor element |
| WO1996026544A1 (en) * | 1995-02-22 | 1996-08-29 | Micron Technology, Inc. | Method of forming a dram bit line contact |
| US5686747A (en) * | 1993-02-12 | 1997-11-11 | Micron Technology, Inc. | Integrated circuits comprising interconnecting plugs |
| US5705838A (en) * | 1993-02-12 | 1998-01-06 | Micron Technology, Inc. | Array of bit line over capacitor array of memory cells |
-
1989
- 1989-08-18 JP JP1212147A patent/JPH0376159A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03178115A (en) * | 1989-12-06 | 1991-08-02 | Matsushita Electric Ind Co Ltd | Manufacture of solid electrolytic capacitor |
| JPH04225557A (en) * | 1990-04-03 | 1992-08-14 | Electron & Telecommun Res Inst | Dram cell of standard structure |
| JPH04298074A (en) * | 1990-10-25 | 1992-10-21 | Hyundai Electron Ind Co Ltd | Dram provided with stacked capacitor and manufacture thereof |
| JPH04196481A (en) * | 1990-11-28 | 1992-07-16 | Nec Corp | Semiconductor storage device |
| JPH06181295A (en) * | 1991-12-18 | 1994-06-28 | Samsung Electron Co Ltd | Semiconductor memory device and its manufacture |
| JPH06232366A (en) * | 1992-12-31 | 1994-08-19 | Hyundai Electron Ind Co Ltd | Manufacture of laminated capacitor for semiconductor element |
| US5821140A (en) * | 1993-02-12 | 1998-10-13 | Micron Technology, Inc. | Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells |
| US5686747A (en) * | 1993-02-12 | 1997-11-11 | Micron Technology, Inc. | Integrated circuits comprising interconnecting plugs |
| US5705838A (en) * | 1993-02-12 | 1998-01-06 | Micron Technology, Inc. | Array of bit line over capacitor array of memory cells |
| US5900660A (en) * | 1993-02-12 | 1999-05-04 | Micron Technology, Inc. | Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory calls |
| US6110774A (en) * | 1993-02-12 | 2000-08-29 | Micron Technology, Inc. | Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells |
| WO1996026544A1 (en) * | 1995-02-22 | 1996-08-29 | Micron Technology, Inc. | Method of forming a dram bit line contact |
| KR100388519B1 (en) * | 1995-02-22 | 2003-09-19 | 마이크론 테크놀로지, 인크. | Method for forming a bit line on a capacitor array of a memory cell and an integrated circuit and a semiconductor memory device using the same |
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