JPH0374512B2 - - Google Patents
Info
- Publication number
- JPH0374512B2 JPH0374512B2 JP60014425A JP1442585A JPH0374512B2 JP H0374512 B2 JPH0374512 B2 JP H0374512B2 JP 60014425 A JP60014425 A JP 60014425A JP 1442585 A JP1442585 A JP 1442585A JP H0374512 B2 JPH0374512 B2 JP H0374512B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- superconducting
- layer
- wiring layer
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 67
- 239000011229 interlayer Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 229910052758 niobium Inorganic materials 0.000 description 5
- 239000010955 niobium Substances 0.000 description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910000484 niobium oxide Inorganic materials 0.000 description 2
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
- H10N60/0912—Manufacture or treatment of Josephson-effect devices
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は少なくとも超伝導体、絶縁体及びトン
ネル障壁で構成される超伝導回路装置の製造方法
に関する。更に特定すれば下部超伝導層の周囲が
絶縁層に埋め込まれた後に層間絶縁膜の形成工程
を有する超伝導回路装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a superconducting circuit device comprising at least a superconductor, an insulator, and a tunnel barrier. More specifically, the present invention relates to a method for manufacturing a superconducting circuit device that includes a step of forming an interlayer insulating film after the periphery of the lower superconducting layer is embedded in an insulating layer.
（従来技術とその問題点）
基板上に複数層の互に電気的に絶縁された超伝
導層を重ねた構造がジヨセフソン接合素子あるい
はジヨセフソン接合集積回路等に代表される超伝
導回路装置に用いられる。例えば幸坂らにより第
45回応用物理学会学術講演会12P−Ｙ−７に平坦
化構造が示されている。第３図に互に電気的に絶
縁された超伝導層の二層構造の従来例の一つを示
す。下部超伝導層１８又は埋め込み絶縁層１９に
接して層間絶縁層２０を堆積した後該層間絶縁層
２０上に接して上部超伝導層２１が形成されてい
た。ところで例えば基板１にアース面を設けた場
合の上部超伝導層２１のインダタンクンス低減や
コンタクトホールの作り易さのために、層間絶縁
層２０の薄型化が必要である。第３図の構造でこ
の要請を満たすためには第４図に示す如く、上部
超伝導層２６と下部超伝導層２３が交差する領域
にのみ層間絶縁層２５を残し、上部超伝導層２６
と下部超伝導層２３が交差しない領域の層間絶縁
層を除去する事が考えられる。しかし、この従来
の製造方法では層間絶縁層２５を下部超伝導層２
３のパターンに対応してパターニングする工程が
必要であつた。(Prior art and its problems) A structure in which multiple superconducting layers electrically insulated from each other are stacked on a substrate is used in superconducting circuit devices such as Josephson junction devices or Josephson junction integrated circuits. . For example, Kosaka et al.
The planarized structure is shown in the 45th Japan Society of Applied Physics Academic Conference 12P-Y-7. FIG. 3 shows a conventional example of a two-layer structure of superconducting layers electrically insulated from each other. After depositing an interlayer insulating layer 20 in contact with the lower superconducting layer 18 or the buried insulating layer 19, an upper superconducting layer 21 was formed in contact with the interlayer insulating layer 20. By the way, it is necessary to make the interlayer insulating layer 20 thinner, for example, in order to reduce the inductance of the upper superconducting layer 21 when a ground plane is provided on the substrate 1 and to facilitate the formation of contact holes. In order to satisfy this requirement with the structure shown in FIG. 3, as shown in FIG.
It is conceivable to remove the interlayer insulating layer in the region where the lower superconducting layer 23 and the lower superconducting layer 23 do not intersect. However, in this conventional manufacturing method, the interlayer insulating layer 25 is
A patterning process corresponding to the pattern No. 3 was required.
この事は製造工程の複雑さを招き更に目合せ余
裕度が必要であり装置の小型化を妨げるものであ
つた。 This complicates the manufacturing process and requires a margin for alignment, which hinders miniaturization of the device.
（発明の目的）
本発明は上述の従来の欠点を除去せしめて、層
間絶縁層のパターニングをセルフアラインで実現
できる超伝導回路装置の製造方法を提供する事に
ある。(Object of the Invention) An object of the present invention is to provide a method for manufacturing a superconducting circuit device that eliminates the above-mentioned conventional drawbacks and allows patterning of an interlayer insulating layer to be realized in a self-aligned manner.
（発明の構成）
本発明によれば第１の超伝導配線層と、第１の
超伝導配線層上に絶縁層を介して位置する第２の
超伝導配線層を有する超伝導回路装置の製造にお
いて、パターン化された第１の超伝導配線層の周
囲を絶縁層で埋め込んだ後、第１の超伝導配線層
の表面を第１と第２の超伝導配線層間に流れるト
ンネル電流を阻止するに充分な厚さにまで絶縁層
化する事を特徴とする超伝導回路装置の製造方法
が得られる。(Structure of the Invention) According to the present invention, a superconducting circuit device having a first superconducting wiring layer and a second superconducting wiring layer located on the first superconducting wiring layer with an insulating layer interposed therebetween is manufactured. After filling the periphery of the patterned first superconducting wiring layer with an insulating layer, a tunnel current flowing between the first and second superconducting wiring layers on the surface of the first superconducting wiring layer is blocked. A method for manufacturing a superconducting circuit device is obtained, which is characterized in that the insulating layer is formed to a thickness sufficient for .
（構成の詳細な説明）
本発明は上述の構成をとることにより、従来技
術の問題点を解決した。(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-described configuration.
第１図は本発明による超伝導回路装置の製造工
程を示す断面図である。パターニングされ、周囲
が埋め込み絶縁層３で囲まれた下部超伝導層２が
基板１上に接して設けられている第１図ａ、次に
下部超伝導層２の表面を絶縁層化し層間絶縁層４
を形成する第１図ｂ、その後、埋め込み絶縁層３
と層間絶縁層４上に上部超伝導層５が設けられる
第１図ｃ。この結果、埋め込まれた下部超伝導層
にセルフアラインで形成された層間絶縁層を介し
て下部超伝導層上に上部超伝導層が形成された多
層構造が実現できる。 FIG. 1 is a sectional view showing the manufacturing process of a superconducting circuit device according to the present invention. A patterned lower superconducting layer 2 surrounded by a buried insulating layer 3 is provided in contact with the substrate 1 (a) in FIG. 4
FIG. 1b to form a buried insulating layer 3.
In FIG. 1c, an upper superconducting layer 5 is provided on the interlayer insulating layer 4. As a result, a multilayer structure can be realized in which the upper superconducting layer is formed on the lower superconducting layer via the interlayer insulating layer formed by self-alignment in the buried lower superconducting layer.
以下本発明の実施例について図面を参照して詳
細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図は本発明の実施例を示すジヨセフソン接
合素子の製造工程図である。ジヨセフソン接合素
子の製造工程はすでに良く知られており、例えば
第２図ａに示す対向電極平坦化までは容易に実現
できる。例えば表面を酸化したシリコンウエハを
基板６に用い、基板６上に例えばニオブの300n
ｍ厚のグランドプレーン７を設けた後、該グラン
ドプレーン７の表面をニオブの酸化膜か又は例え
ばSiO膜あるいは両方を重ねた二層膜でおおい、
絶縁層８とする。 FIG. 2 is a manufacturing process diagram of a Josephson junction device showing an embodiment of the present invention. The manufacturing process of Josephson junction elements is already well known, and for example, the process up to the flattening of the counter electrode shown in FIG. 2a can be easily realized. For example, a silicon wafer with an oxidized surface is used as the substrate 6, and 300n of niobium is coated on the substrate 6.
After providing a ground plane 7 with a thickness of m, the surface of the ground plane 7 is covered with a niobium oxide film, an SiO film, or a two-layer film of both.
This is an insulating layer 8.
次に、例えばニオブスパツタ膜を用いた基部電
極９と該基部電極表面を酸化して得られるトンネ
ル障壁１０と更にニオブスパツタ膜で対向電極１
１を同一装置内で一括して形成した後、必要な領
域の基部電極９、トンネル障壁１０と対向電極１
１を残すように例えばドライエツチング法を用い
てパターニングを行う。一般にジヨセフソン電極
密度を104〜103A／cm2と設計すればトンネル障壁
１０の厚さはおよそ10〓〜20〓の範囲である。そ
の後基板６からの距離が対向電極１１の上表面と
同じ位置まで例えばSiOを蒸着し、絶縁層８上の
基部電極９のない領域を埋め込み絶縁層(1)１２で
埋め込み、この工程までの装置表面を平坦する。
（第２図ａ）次に該装置表面に接して対向電極配
線層１３を例えばニオブスパツタ膜で形成し必要
な領域を残すように例えばドライエツチング法で
パターニングした後、対向電極配線層１３をエツ
チングで除去した領域に例えばSiO蒸着膜で埋め
込み絶縁層(2)１４を形成し、対向電極配線層１３
と埋め込み絶縁層(2)１４の上表面が同一平面内に
あるように平坦化する。（第２図ｂ）その後例え
ばRFプラズマ酸化をRF電圧140V、Ar＋4.8Vol
％O2ガス圧３ｍTorrの条件下で行うと約５時間
で40〓程度のニオブ酸化膜が対向電極配線層１３
表面上に形成され、絶縁層１５を得る。（第２図
ｃ）この場合、絶縁層１５を流れるジヨセフソン
電流密度は10-5A／cm2以下と考えられ、トンネル
障壁１０を流れるジヨセフソン電流密度をおよそ
104A〜103A／cm2と設計した場合、絶縁層１５に
よる漏れ電流は無視できる。尚この酸化条件は一
例にすぎずRF電圧、ガス種、ガス圧酸化時間を
それぞれ最適化する事により更に高品質な絶縁層
１５を得る事ができる。 Next, a base electrode 9 made of a niobium sputtered film, a tunnel barrier 10 obtained by oxidizing the surface of the base electrode, and a counter electrode 1 made of a niobium sputtered film.
1 in the same device, the base electrode 9, tunnel barrier 10 and counter electrode 1 are formed in the necessary areas.
Patterning is performed using, for example, a dry etching method so that 1 remains. In general, if the Josephson electrode density is designed to be 10 4 to 10 3 A/cm 2 , the thickness of the tunnel barrier 10 will be in the range of about 10 to 20 A/cm 2 . After that, for example, SiO is vapor-deposited to the same distance from the substrate 6 as the upper surface of the counter electrode 11, and the area on the insulating layer 8 where the base electrode 9 is not filled is filled with the buried insulating layer (1) 12, and the apparatus up to this step is Flatten the surface.
(FIG. 2a) Next, a counter electrode wiring layer 13 is formed of, for example, a niobium sputtered film in contact with the surface of the device, and patterned by, for example, a dry etching method so as to leave a necessary area, and then the counter electrode wiring layer 13 is etched. A buried insulating layer (2) 14 is formed in the removed region using, for example, a SiO vapor deposition film, and a counter electrode wiring layer 13 is formed.
and the upper surface of the buried insulating layer (2) 14 are flattened so that they are in the same plane. (Fig. 2b) Then, for example, RF plasma oxidation is performed at RF voltage 140V, Ar + 4.8Vol.
% O2 gas pressure of 3 mTorr, approximately 40% of niobium oxide film is formed on the counter electrode wiring layer 13 in about 5 hours.
An insulating layer 15 is formed on the surface. (Fig. 2c) In this case, the Josephson current density flowing through the insulating layer 15 is considered to be 10 -5 A/cm 2 or less, and the Josephson current density flowing through the tunnel barrier 10 is approximately
When designed to be 10 4 A to 10 3 A/cm 2 , leakage current due to the insulating layer 15 can be ignored. Note that these oxidation conditions are merely an example, and an even higher quality insulating layer 15 can be obtained by optimizing the RF voltage, gas type, and gas pressure oxidation time.
次に例えばニオブスパツタ膜を堆積し、パター
ニングして制御線１６を形成する。（第２図ｄ）
更に必要ならば制御線１６形成後に図には示され
ていないが、例えばSiOで保護膜を設けてもよ
い。 Next, for example, a niobium sputtered film is deposited and patterned to form the control line 16. (Figure 2d)
Furthermore, if necessary, a protective film of SiO, for example, may be provided after the control line 16 is formed, although it is not shown in the figure.
以上の結果、周囲が埋め込まれた対向電極配線
層上に絶縁層を介して制御線を形成する構造にお
いて、該絶縁層をセルフアラインによつて形成し
ている。以上実施例で述べた製造工程の内装置構
造、超伝導材料、絶縁層材料、あるいはそれ等の
製造方法パターニング方法等には多くのバリエー
シヨンが考えられるが、本発明はいずれの場合も
有効に用いる事ができる。 As a result of the above, in a structure in which a control line is formed via an insulating layer on a counter electrode wiring layer whose periphery is buried, the insulating layer is formed by self-alignment. Although there are many variations in the device structure, superconducting material, insulating layer material, manufacturing method, patterning method, etc. of the manufacturing process described in the above embodiments, the present invention is effective in any case. It can be used.
（発明の効果）
本発明によれば、周囲が埋め込まれた下部超伝
導層上に形成された絶縁層を介して上部超伝導層
を設ける場合、該絶縁層が下部超伝導層にセルフ
アラインで形成されるので、該絶縁層のパターニ
ング工程が不要になり、工程の簡略化でき、更に
目合せ余裕度が不要になり装置の小型化を可能に
する。(Effects of the Invention) According to the present invention, when an upper superconducting layer is provided via an insulating layer formed on a lower superconducting layer in which the periphery is embedded, the insulating layer is self-aligned with the lower superconducting layer. Since the patterning process of the insulating layer is not necessary, the process can be simplified, and alignment margin is not required, making it possible to downsize the device.
第１図ａからｃは本発明による超伝導回路装置
の製造工程を示す断面図、第２図ａからｄは本発
明による実施例を示すためのジヨセフソン接合素
子の製造工程図、第３図は従来の超伝導回路装置
の一つを示すための構造断面図、第４図は別の従
来の超伝導回路装置を示すための構造断面図であ
る。
図において、１，６，１７，２２は基板、２，
１８，２３は下部超伝導層、３，１９，２４は埋
め込み絶縁層、４，２０，２５は層間絶縁層、
５，２１，２６は上部超伝導層、７はグランドプ
レーン、８，１５は絶縁層、９は基部電極、１０
はトンネル障壁、１１は対向電極、１２は埋め込
み絶縁層(1)、１３は対向電極配線層、１４は埋め
込み絶縁層(2)、１６は制御線である。
1A to 1C are cross-sectional views showing the manufacturing process of a superconducting circuit device according to the present invention, FIGS. A structural cross-sectional view showing one conventional superconducting circuit device, and FIG. 4 is a structural cross-sectional view showing another conventional superconducting circuit device. In the figure, 1, 6, 17, 22 are substrates, 2,
18, 23 are lower superconducting layers, 3, 19, 24 are buried insulating layers, 4, 20, 25 are interlayer insulating layers,
5, 21, 26 are upper superconducting layers, 7 is a ground plane, 8, 15 are insulating layers, 9 is a base electrode, 10
11 is a tunnel barrier, 11 is a counter electrode, 12 is a buried insulating layer (1), 13 is a counter electrode wiring layer, 14 is a buried insulating layer (2), and 16 is a control line.
Claims (1)
上に絶縁層を介して位置する第２の超伝導配線層
を有する起伝導回路装置の製造において、パター
ン化された第１の超伝導配線層の周囲を絶縁層で
埋め込んだ後、第１の超伝導配線層の表面を第１
と第２の超伝導配線層間に流れるトンネル電流を
阻止するに充分な厚さにまで絶縁層化する事を特
徴とする超伝導回路装置の製造方法。1. In manufacturing a conductive circuit device having a first superconducting wiring layer and a second superconducting wiring layer located on the first superconducting wiring layer with an insulating layer interposed therebetween, a patterned first After filling the periphery of the superconducting wiring layer with an insulating layer, the surface of the first superconducting wiring layer is covered with a first
A method for manufacturing a superconducting circuit device, comprising forming an insulating layer to a thickness sufficient to block tunnel current flowing between the first and second superconducting wiring layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60014425A JPS61174783A (en) | 1985-01-30 | 1985-01-30 | Manufacture of superconducting circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60014425A JPS61174783A (en) | 1985-01-30 | 1985-01-30 | Manufacture of superconducting circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61174783A JPS61174783A (en) | 1986-08-06 |
| JPH0374512B2 true JPH0374512B2 (en) | 1991-11-27 |
Family
ID=11860662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60014425A Granted JPS61174783A (en) | 1985-01-30 | 1985-01-30 | Manufacture of superconducting circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174783A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209183A (en) * | 1982-05-31 | 1983-12-06 | Nec Corp | Manufacture of josephson junction element |
-
1985
- 1985-01-30 JP JP60014425A patent/JPS61174783A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209183A (en) * | 1982-05-31 | 1983-12-06 | Nec Corp | Manufacture of josephson junction element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61174783A (en) | 1986-08-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |