JPH0370382B2 - - Google Patents
Info
- Publication number
- JPH0370382B2 JPH0370382B2 JP57220582A JP22058282A JPH0370382B2 JP H0370382 B2 JPH0370382 B2 JP H0370382B2 JP 57220582 A JP57220582 A JP 57220582A JP 22058282 A JP22058282 A JP 22058282A JP H0370382 B2 JPH0370382 B2 JP H0370382B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- region
- substrate
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 10
- 230000005669 field effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 23
- 235000012239 silicon dioxide Nutrition 0.000 description 22
- 239000000377 silicon dioxide Substances 0.000 description 22
- 238000003860 storage Methods 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000002955 isolation Methods 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 230000010354 integration Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- LBDSXVIYZYSRII-IGMARMGPSA-N alpha-particle Chemical compound [4He+2] LBDSXVIYZYSRII-IGMARMGPSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-RNFDNDRNSA-N silicon-32 atom Chemical compound [32Si] XUIMIQQOPSSXEZ-RNFDNDRNSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- OFHCOWSQAMBJIW-AVJTYSNKSA-N alfacalcidol Chemical compound C1(/[C@@H]2CC[C@@H]([C@]2(CCC1)C)[C@H](C)CCCC(C)C)=C\C=C1\C[C@@H](O)C[C@H](O)C1=C OFHCOWSQAMBJIW-AVJTYSNKSA-N 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は半導体メモリセルの構造に関し、さら
に詳しくはより大きな記憶容量を実現する半導体
メモリセルの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor memory cell, and more particularly to a structure of a semiconductor memory cell that achieves a larger storage capacity.
電荷の形で２進情報を貯蔵する半導体メモリセ
ルはセル面積が小さいため、高集積、大容量メモ
リセルとして優れている。特にメモリセルとして
１つのトランジスタと１つのコンデンサからなる
メモリセル（以下1T1Cセルと略す）は構成要素
も少なく、セル面積も小さいため高集積メモリ用
メモリセルとして重要である。 Semiconductor memory cells that store binary information in the form of charges have a small cell area and are therefore excellent as highly integrated and large capacity memory cells. In particular, a memory cell consisting of one transistor and one capacitor (hereinafter abbreviated as 1T1C cell) has few constituent elements and has a small cell area, so it is important as a memory cell for highly integrated memory.
第１図に従来よく用いられている1T1Cセルの
１例を示す。第１図に於いて、３がキヤパシタ電
極で６の反転層との間に記憶容量を形成する。２
はスイツチングトランジスタのゲート電極で、ワ
ード線に接続されており、ビツト線に接続されて
いる拡散層４と反転層６の間の電荷の移動を制御
する。又、７は隣接メモリセルとの分離領域であ
る。従来例において、記憶容量は３のキヤパシタ
電極の面積と５の絶縁膜の誘電率及び膜厚によつ
て決定される。すなわち、大きな記憶容量を確保
する手段として以下の３つの方法がある。 Figure 1 shows an example of a 1T1C cell that has been commonly used in the past. In FIG. 1, a capacitor electrode 3 forms a storage capacitor between it and an inversion layer 6. 2
is the gate electrode of the switching transistor, which is connected to the word line and controls the movement of charges between the diffusion layer 4 and the inversion layer 6, which are connected to the bit line. Further, 7 is an isolation region from an adjacent memory cell. In the conventional example, the storage capacity is determined by the area of the capacitor electrode (3) and the dielectric constant and film thickness of the insulating film (5). That is, there are the following three methods for securing a large storage capacity.
(1) キヤパシタ電極の面積の面積を大きくする。(1) Increase the area of the capacitor electrode.
(2) 絶縁膜の膜厚を薄くする。(2) Reduce the thickness of the insulating film.
(3) 高誘電率の絶縁膜を用いる。(3) Use an insulating film with a high dielectric constant.
ところで、一般にメモリの高集積化は微細加工
技術の進展に伴うメモリセルサイズの縮小によつ
て達成されており、従来例で示した1T1Cセル構
造ではキヤパシタ電極の面積は減少する。それ
故、従来例の1T1Cセルでは絶縁膜の膜厚を薄く
することにより記憶容量の大幅な減少を防いでい
た。しかし絶縁膜の膜厚はもはや限界に近づいて
おり、一方セルの微細化は進展するばかりで従来
の構造の1T1Cセルでは高誘電率の絶縁膜を採用
しない限り記憶容量は減少する一方である。 Incidentally, high integration of memory is generally achieved by reducing memory cell size with advances in microfabrication technology, and in the 1T1C cell structure shown in the conventional example, the area of the capacitor electrode is reduced. Therefore, in conventional 1T1C cells, a significant decrease in storage capacity was prevented by reducing the thickness of the insulating film. However, the thickness of the insulating film is approaching its limit, and on the other hand, the miniaturization of cells continues to progress, and the storage capacity of 1T1C cells with the conventional structure will continue to decrease unless an insulating film with a high dielectric constant is used.
高誘電率の絶縁膜は模索段階で近いうちに実用
化される目途はたつていない。 Insulating films with high dielectric constants are still in the exploratory stage and there is no prospect that they will be put to practical use in the near future.
以上述べたように、従来型の1T1Cセルは、今
後ますます記憶容量が減少するという問題点を有
している。しかも耐α粒子問題、センスアンプの
感度等から大きな記憶容量が望まれており（例え
ば耐α粒子問題からは50fF以上の記憶容量）従
来型の1T1Cではもはや対処出来ない。 As described above, conventional 1T1C cells have the problem that their storage capacity will continue to decrease in the future. Moreover, a large storage capacity is desired due to the α-particle resistance problem, the sensitivity of the sense amplifier, etc. (for example, a storage capacity of 50 fF or more due to the α-particle resistance problem), and the conventional 1T1C can no longer cope with this problem.
本発明の目的は、上記従来型1T1Cセルの欠点
を改善し、微小な面積のセルに於いても従来型セ
ル以上に大きな記憶容量を得ることが可能な構造
の半導体メモリセルを提供することにある。 An object of the present invention is to provide a semiconductor memory cell having a structure that improves the drawbacks of the conventional 1T1C cell and can obtain a larger storage capacity than the conventional cell even in a cell with a small area. be.
本発明によれば、半導体基板上に半導体の壁で
仕切られた領域を複数形成し、それら各領域内の
壁の側面または側面と底面の一部を薄い絶縁膜を
介して導電性薄膜で被い、しかもこの導電性薄膜
は一つの領域内で複数に分離され、前記複数の導
電性薄膜と前記薄い絶縁膜と壁または壁と基板の
半導体とでメモリセル用キヤパシタを一つの領域
内に複数構成し、前記導電性薄膜の表面を絶縁膜
で被い、基板と電気的に接続したエピタキシヤル
半導体膜を前記各領域を埋めるように形成し、一
つの領域内のエピタキシヤル半導体膜にMIS電界
効果トランジスタを前記キヤパシタと同数形成
し、それぞれのトランジスタの拡散層の一方を前
記複数形成したキヤパシタのそれぞれの導電性薄
膜と電気的に接続することを特徴とする半導体メ
モリセルが得られる。 According to the present invention, a plurality of regions partitioned by semiconductor walls are formed on a semiconductor substrate, and the side surfaces of the walls or part of the side surfaces and bottom surfaces in each region are covered with a conductive thin film via a thin insulating film. Moreover, this conductive thin film is separated into a plurality of parts within one region, and a plurality of memory cell capacitors are formed within one region by the plurality of conductive thin films, the thin insulating film, and the wall or the wall and the semiconductor of the substrate. The surface of the conductive thin film is covered with an insulating film, and an epitaxial semiconductor film electrically connected to the substrate is formed to fill each region, and an MIS electric field is applied to the epitaxial semiconductor film in one region. A semiconductor memory cell is obtained, characterized in that effect transistors are formed in the same number as the capacitors, and one of the diffusion layers of each transistor is electrically connected to the conductive thin film of each of the plurality of capacitors formed.
以下本発明の典型的な一実施例としてキヤパシ
タンス部を二分割した場合について第２図、第３
図を用いて詳述する。 Below, as a typical embodiment of the present invention, the case where the capacitance section is divided into two parts is shown in Figs. 2 and 3.
This will be explained in detail using figures.
第２図は本発明におけるメモリセルの平面図を
示したものであり、第３図は第２図の平面図を
AA′の一点鎖線に沿つて切り開いた部分を製造プ
ロセスの順を追つて示した模式的断面図である。 FIG. 2 shows a plan view of the memory cell according to the present invention, and FIG. 3 shows the plan view of FIG. 2.
FIG. 3 is a schematic cross-sectional view showing a part cut out along the dashed line of AA' in order of the manufacturing process.
まず、Ｐ型シリコン単結晶基板２１の表面上に
熱酸化法又はCVD法により二酸化珪素膜２２を
形成した後、素子分離領域の形状を有するフオト
レジスト２３を形成した（ａ図）。 First, a silicon dioxide film 22 was formed on the surface of a P-type silicon single crystal substrate 21 by a thermal oxidation method or a CVD method, and then a photoresist 23 having the shape of an element isolation region was formed (FIG. 1A).
次に、前記フオトレジスト２３を耐エツチング
マスクとして前記二酸化珪素膜２２をエツチング
除去し、さらにシリコン基板をも深くエツチング
してシリコン基板表面に凹部を設けた後、熱酸化
法によりシリコン基板２１を二酸化珪素膜２４で
被い、さらに多結晶シリコン２５、二酸化珪素膜
２６、窒化珪素膜２７を順次形成してから凹部に
おけるキヤパシタンス分離領域を除く全面をフオ
トレジスト２８で被い、さらにこのフオトレジス
ト２８を耐エツチングマスクとしてキヤパシタン
ス分離領域の前記窒化珪素膜２７、前記二酸化珪
素膜２６および前記多結晶シリコン２５の一部を
エツチング除去した（ｂ図）。 Next, the silicon dioxide film 22 is removed by etching using the photoresist 23 as an etching-resistant mask, and the silicon substrate is also deeply etched to form a recess on the surface of the silicon substrate. After covering with a silicon film 24, polycrystalline silicon 25, silicon dioxide film 26, and silicon nitride film 27 are sequentially formed, the entire surface except for the capacitance isolation region in the recess is covered with photoresist 28, and this photoresist 28 is then covered. Parts of the silicon nitride film 27, the silicon dioxide film 26, and the polycrystalline silicon 25 in the capacitance isolation region were removed by etching as an etching-resistant mask (Figure b).
次に、前記窒化珪素膜２７を耐酸化マスクとし
て前記多結晶シリコン２５を酸化しキヤパシタン
ス分離領域に二酸化珪素膜２９を形成した（ｃ
図）。 Next, the polycrystalline silicon 25 was oxidized using the silicon nitride film 27 as an oxidation-resistant mask to form a silicon dioxide film 29 in the capacitance isolation region (c
figure).
このようにして凹部に形成した多結晶シリコン
２５は二酸化珪素膜２９により二分割されるた
め、キヤパシタンスも二分割されることになる。 Since the polycrystalline silicon 25 thus formed in the recess is divided into two by the silicon dioxide film 29, the capacitance is also divided into two.
次に、凹部の底の一部分を除く全面をフオトレ
ジスト３０で被つた後、このフオトレジスト３０
を耐エツチングマスクとして前記窒化珪素膜２
７、前記二酸化珪素膜２６、前記多結晶シリコン
２５、前記二酸化珪素膜２４を各々エツチング除
去した（ｄ図）。 Next, after covering the entire surface of the recess except for a part of the bottom with a photoresist 30, the photoresist 30
The silicon nitride film 2 is used as an etching-resistant mask.
7. The silicon dioxide film 26, the polycrystalline silicon 25, and the silicon dioxide film 24 were each removed by etching (Figure d).
次に、前記窒化珪素膜２７を耐酸化マスクとし
て熱酸化法により前記多結晶シリコン２５の一部
を酸化した（ｅ図）。 Next, a portion of the polycrystalline silicon 25 was oxidized by a thermal oxidation method using the silicon nitride film 27 as an oxidation-resistant mask (Fig. e).
次に、前記窒化珪素膜２７を耐エツチングマス
クとして凹部の底の一部に形成された二酸化珪素
膜３１′を除去し、次に前記窒化珪素膜２７を除
去した後凹部の底に形成された窓よりシリコンの
エピタキシヤル成長法を用いて基板シリコン２１
と同じ導電型の単結晶シリコン３２を成長させて
凹部を完全に埋めてしまつた状態を示す。（ｆ図）
次に、表面に出ている前記二酸化珪素膜２６を
除去した後、前記多結晶シリコン２５およびエピ
タキシヤル成長により形成した単結晶シリコン３
２を前記二酸化珪素膜２３′の表面が出るまでエ
ツチング除去した（ｇ図）。 Next, using the silicon nitride film 27 as an etching-resistant mask, the silicon dioxide film 31' formed on a part of the bottom of the recess is removed, and after removing the silicon nitride film 27, the silicon dioxide film 31' formed on the bottom of the recess is removed. The substrate silicon 21 is grown using the silicon epitaxial growth method from the window.
This shows a state in which single crystal silicon 32 of the same conductivity type is grown to completely fill the recess. (Figure f) Next, after removing the silicon dioxide film 26 exposed on the surface, the polycrystalline silicon 25 and the single crystal silicon 3 formed by epitaxial growth are removed.
2 was removed by etching until the surface of the silicon dioxide film 23' was exposed (Figure g).
次に、前記単結晶シリコン３２上にゲート酸化
膜３３を形成、多結晶シリコンによりスイツチン
グトランジスタのゲート電極１１′，１１′Ａを形
成、さらに砒素又は燐のイオン注入によりビツト
線に接続するＮ型拡散層領域１２および多結晶シ
リコン１３，１３Ａを通して前記シリコン基板内
に形成した前記多結晶シリコン２５と導通してい
るＮ型拡散層３４を形成することにより凹部内に
1T1Cを２個形成した（ｈ図）。 Next, a gate oxide film 33 is formed on the single crystal silicon 32, gate electrodes 11' and 11'A of the switching transistors are formed using polycrystalline silicon, and the N electrodes connected to the bit lines are formed by ion implantation of arsenic or phosphorus. By forming an N-type diffusion layer 34 that is electrically connected to the polycrystalline silicon 25 formed in the silicon substrate through the type diffusion layer region 12 and the polycrystalline silicon 13, 13A,
Two 1T1C were formed (Figure h).
第２図の平面図、第３図ｈの断面図と従来の
1T1Cセルの第１図を比較してみると、第１図の
ワード線に接続されているスイツチングトランジ
スタのゲート電極２は、第２図、第３図ｈでは、
多結晶シリコン１１′，１１′Ａに相当し、第１図
のビツト線に接続されている拡散層４は第２図、
第３図ｈでは拡散層１２に相当している。電荷を
記憶する場合、ワード線に接続されたスイツチン
グトランジスタをONにすることにより、ビツト
線に接続された拡散層１２より基板内に形成され
た多結晶シリコン２５に電荷が蓄積されて記憶状
態となる。そしてこの蓄積容量は、多結晶シリコ
ンとシリコン基板間に形成された二酸化珪素膜の
容量により形成される。このため蓄積容量は、多
結晶シリコンを基板内に深く形成することによ
り、表面積を増加させることなく、蓄積容量のみ
を増加できる。 The plan view in Fig. 2, the sectional view in Fig. 3 h, and the conventional
Comparing Figure 1 of the 1T1C cell, the gate electrode 2 of the switching transistor connected to the word line in Figure 1 is as follows in Figures 2 and 3.
The diffusion layer 4 corresponding to the polycrystalline silicon 11', 11'A and connected to the bit line in FIG. 1 is shown in FIG.
In FIG. 3h, this corresponds to the diffusion layer 12. When storing electric charge, by turning on the switching transistor connected to the word line, the electric charge is accumulated in the polycrystalline silicon 25 formed in the substrate from the diffusion layer 12 connected to the bit line, and the stored state is changed. becomes. This storage capacitance is formed by the capacitance of a silicon dioxide film formed between the polycrystalline silicon and the silicon substrate. Therefore, by forming polycrystalline silicon deep within the substrate, only the storage capacitance can be increased without increasing the surface area.
記憶した電荷を読み出す場合、ワード線に接続
されたスイツチングトランジスタをONにして、
ビツト線に接続された拡散層１２に基板内に形成
された多結晶シリコンに蓄積された電荷を移動さ
せて読み出しを行う。 To read the stored charge, turn on the switching transistor connected to the word line,
Reading is performed by moving the charges accumulated in polycrystalline silicon formed in the substrate to the diffusion layer 12 connected to the bit line.
本発明によるメモリセルは、凹部内に形成した
キヤパシタとしての多結晶シリコンを多分割する
ことにより一つの凹部内に複数個のメモリセルを
形成して集積度の大幅な向上を可能にしているば
かりか、前記実施例ではその記憶容量自体はシリ
コン基板内に形成する多結晶シリコンの両側に形
成されるため極めて大きくなる。またさらに、大
きな容量が必要ならばこの多結晶シリコンの深さ
を深くとることによつて集積度を落とさずに必要
な記憶容量を容易に確保できる。 The memory cell according to the present invention not only makes it possible to significantly improve the degree of integration by forming a plurality of memory cells in one recess by dividing polycrystalline silicon as a capacitor formed in the recess into multiple parts. Furthermore, in the embodiment described above, the storage capacity itself is extremely large because it is formed on both sides of the polycrystalline silicon formed within the silicon substrate. Furthermore, if a large capacity is required, by increasing the depth of this polycrystalline silicon, the required storage capacity can be easily secured without reducing the degree of integration.
現在までのところダイナミツクメモリセルの記
憶容量はα線が１個入射してもソフトエラーを発
生しないだけの大きさを有することが必要とされ
ている。記憶容量部を平面的に形成している従来
の1T1Cメモリセルを用いる場合、1Mbitクラス
の高集積大容量メモリセルでは、セル面積におけ
る記憶容量部の占める割合は50％程度にも及ぶ
が、本発明によれば、記憶容量部は基板内に形成
されるため、この部分の表面積は非常に小さくて
済み、高集積化に適している。 Up to now, the storage capacity of a dynamic memory cell is required to be large enough not to cause a soft error even if one alpha ray is incident on it. When using a conventional 1T1C memory cell in which the storage capacity section is formed in a planar manner, in a 1Mbit class highly integrated large capacity memory cell, the storage capacity section accounts for approximately 50% of the cell area. According to the invention, since the storage capacitor section is formed within the substrate, the surface area of this section can be extremely small, making it suitable for high integration.
前記の実施例においては、シリコン基板内に形
成した多結晶シリコンによるキヤパシタンス領域
の形を素子領域下まで広げて、断面図３ｆでもわ
かるようにＬ字型にしているが、このキヤパシタ
ンス部の形状自体は必ずしもこのように素子領域
下まで広がつたＬ字型でなくてもよく、基板の深
さ方向のみに形成された構造でも十分である。た
だしこの場合はＬ字型に比べて深さ方向に深くキ
ヤパシタンス領域を形成して容量を大きくとる必
要がある。 In the above embodiment, the shape of the capacitance region made of polycrystalline silicon formed in the silicon substrate is extended to below the element region, and is L-shaped as can be seen in the cross-sectional view 3f. However, the shape of this capacitance region itself is It does not necessarily have to be an L-shape extending below the element region, and a structure formed only in the depth direction of the substrate is sufficient. However, in this case, it is necessary to form a capacitance region deeper in the depth direction than in the L-shape to increase the capacitance.
また素子分離については、前記実施例では２ビ
ツト分のセルとセルの間にシリコン基板２１を細
く残して素子分離領域としているが、これに限る
必要はなく、絶縁体例えばSiO2を用いて分離し
てもよい。 Regarding element isolation, in the embodiment described above, a thin silicon substrate 21 is left between cells for 2 bits to serve as an element isolation region, but it is not limited to this, and an insulator such as SiO 2 can be used for isolation. You may.
さらに、前記実施例では２ビツト分のセルを形
成する場合を示したが、複数ビツト分のセルを形
成することができることは自明である。 Further, in the above embodiment, a case was shown in which a cell for two bits was formed, but it is obvious that a cell for a plurality of bits could be formed.
以上述べたように本発明によれば、微細なメモ
リセル面積においても記憶容量を大きくとること
ができるため、高集積化に適したメモリセルが容
易に得られる。 As described above, according to the present invention, a large storage capacity can be obtained even in a small memory cell area, so that a memory cell suitable for high integration can be easily obtained.
第１図は、従来の1T1Cメモリセルの断面図、
第２図は本発明によるメモリセルの平面図、第３
図は本発明によるメモリセルを製造するプロセス
を示す断面図である。
１…シリコン基板、２…ワード線に接続された
ゲート電極、３…キヤパシタ電極、４…ビツト線
に接続された拡散層、５…二酸化珪素膜、６…反
転層、７…分離領域に形成された二酸化珪素膜、
１１，１１Ａ…ワード線、１１′，１１′Ａ…スイ
ツチングトランジスタのゲート電極、１２…ビツ
ト線に接続する拡散層、１３，１３Ａ…多結晶シ
リコン、１４…凹部に形成した多結晶シリコンを
分割する分離領域、２１…シリコン基板、２２，
２２′…二酸化珪素膜、２３…フオトレジスト、
２４…二酸化珪素膜、２５…多結晶シリコン、２
６…二酸化珪素膜、２７…窒化珪素膜、２８…フ
オトレジスト、２９…多結晶シリコンを分離して
いる二酸化珪素膜、３０…フオトレジスト、３
１，３１′…二酸化珪素膜、３２…エピタキシヤ
ル成長により形成した単結晶シリコン、３３…二
酸化珪素膜、３４…拡散層、３５…二酸化珪素
膜。
Figure 1 is a cross-sectional view of a conventional 1T1C memory cell.
FIG. 2 is a plan view of a memory cell according to the present invention;
The figure is a cross-sectional view showing a process for manufacturing a memory cell according to the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Gate electrode connected to word line, 3... Capacitor electrode, 4... Diffusion layer connected to bit line, 5... Silicon dioxide film, 6... Inversion layer, 7... Formed in isolation region. silicon dioxide film,
11, 11A... Word line, 11', 11'A... Gate electrode of switching transistor, 12... Diffusion layer connected to bit line, 13, 13A... Polycrystalline silicon, 14... Dividing polycrystalline silicon formed in the recessed part. isolation region, 21...silicon substrate, 22,
22'...Silicon dioxide film, 23...Photoresist,
24...Silicon dioxide film, 25...Polycrystalline silicon, 2
6...Silicon dioxide film, 27...Silicon nitride film, 28...Photoresist, 29...Silicon dioxide film separating polycrystalline silicon, 30...Photoresist, 3
1, 31'...Silicon dioxide film, 32...Single crystal silicon formed by epitaxial growth, 33...Silicon dioxide film, 34...Diffusion layer, 35...Silicon dioxide film.
Claims (1)
を複数形成し、それら各領域内の壁の側面または
側面と底面の一部を薄い絶縁膜を介して導電性薄
膜で被い、しかもこの導電性薄膜は一つの領域内
で複数に分離され、前記複数の導電性薄膜と前記
薄い絶縁膜と壁または壁と基板の半導体とでメモ
リセル用キヤパシタを一つの領域内に複数構成
し、前記導電性薄膜の表面を絶縁膜で被い、基板
と電気的に接続したエピタキシヤル半導体膜を前
記各領域を埋めるように形成し、一つの領域内の
エピタキシヤル半導体膜にMIS電界効果トランジ
スタを前記キヤパシタと同数形成し、それぞれの
トランジスタの拡散層の一方を前記複数形成した
キヤパシタのそれぞれの導電性薄膜と電気的に接
続することを特徴とする半導体メモリセル。1 A plurality of regions partitioned by semiconductor walls are formed on a semiconductor substrate, and the sides of the walls or part of the sides and bottom of each region are covered with a conductive thin film via a thin insulating film, and this conductive film is The conductive thin film is separated into a plurality of parts in one region, and a plurality of memory cell capacitors are configured in one region by the plurality of conductive thin films, the thin insulating film, and the wall or the wall and the semiconductor of the substrate. The surface of the magnetic thin film is covered with an insulating film, an epitaxial semiconductor film electrically connected to the substrate is formed to fill each of the regions, and a MIS field effect transistor is connected to the capacitor in the epitaxial semiconductor film in one region. A semiconductor memory cell characterized in that the same number of capacitors are formed, and one of the diffusion layers of each transistor is electrically connected to the conductive thin film of each of the plurality of capacitors formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57220582A JPS59110155A (en) | 1982-12-16 | 1982-12-16 | Semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57220582A JPS59110155A (en) | 1982-12-16 | 1982-12-16 | Semiconductor memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59110155A JPS59110155A (en) | 1984-06-26 |
| JPH0370382B2 true JPH0370382B2 (en) | 1991-11-07 |
Family
ID=16753226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57220582A Granted JPS59110155A (en) | 1982-12-16 | 1982-12-16 | Semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59110155A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6115362A (en) * | 1984-06-29 | 1986-01-23 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Dynamic ram cell |
| JPH0296368A (en) * | 1988-09-30 | 1990-04-09 | Ricoh Co Ltd | Semiconductor memory device |
| JPH02135776A (en) * | 1988-11-17 | 1990-05-24 | Hitachi Ltd | Semiconductor storage device |
-
1982
- 1982-12-16 JP JP57220582A patent/JPS59110155A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59110155A (en) | 1984-06-26 |
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