JPH0370275A - Video display device - Google Patents
Video display deviceInfo
- Publication number
- JPH0370275A JPH0370275A JP20468489A JP20468489A JPH0370275A JP H0370275 A JPH0370275 A JP H0370275A JP 20468489 A JP20468489 A JP 20468489A JP 20468489 A JP20468489 A JP 20468489A JP H0370275 A JPH0370275 A JP H0370275A
- Authority
- JP
- Japan
- Prior art keywords
- video
- video signal
- circuit
- reference clock
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 abstract description 9
- 238000003786 synthesis reaction Methods 0.000 abstract description 9
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Radar Systems Or Details Thereof (AREA)
- Studio Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は映像表示装置に係り、特に複数の映像を重畳し
て表示する映像表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video display device, and particularly to a video display device that displays a plurality of videos in a superimposed manner.
従来、複数の映像信号源から出力される映像信号を、Ｃ
ＲＴ等のモニタ受像機の同一画面上に重畳して表示する
ことが、例えば特開昭５４−４００９１号公報に示され
る如く行われていた。Conventionally, video signals output from multiple video signal sources are
For example, as shown in Japanese Patent Application Laid-Open No. 54-40091, images have been displayed in a superimposed manner on the same screen of a monitor receiver such as an RT.
この場合、夫々の映像信号源よりの出力映像信号のタイ
ミングがずれていると、モニタ受像機で扱う複数の映像
信号の同期が乱れ、映像の重畳が良好には行われず、最
悪の場合には重畳された映像信号の垂直同期信号や水平
同期信号が乱れたものとなり、映像の表示ができなくな
る欠点があった。In this case, if the timing of the output video signals from each video signal source is out of sync, the synchronization of the multiple video signals handled by the monitor receiver will be disrupted, the video will not be superimposed properly, and in the worst case, This has the disadvantage that the vertical synchronization signal and horizontal synchronization signal of the superimposed video signal become distorted, making it impossible to display the video.
本発明は斯る点に鑑み、簡単な構成で複数の映像の重畳
が良好に行える映像表示装置を提供することを目的とす
る。In view of the above, an object of the present invention is to provide a video display device that has a simple configuration and can satisfactorily superimpose a plurality of videos.
上記目的は、第１の映像信号源の出力映像信号と第２の
映像信号源の出力映像信号との位相差を検出する同期検
出回路を設け、この同期検出回路の検出信号に基づいて
第１又は第２の映像信号源の映像信号出力タイミングを
制御することで、達成される。The above object is to provide a synchronization detection circuit that detects the phase difference between the output video signal of the first video signal source and the output video signal of the second video signal source, and to Alternatively, this can be achieved by controlling the video signal output timing of the second video signal source.
斯る構成によると、一方の映像信号源の映像信号出力タ
イミングに合わせて、他方の映像信号源の映像信号出力
タイミングが制御され、双方の映像信号出力タイミング
が一致するようになり、両出力映像信号を重畳しても同
期孔れが発生しない。According to this configuration, the video signal output timing of the other video signal source is controlled in accordance with the video signal output timing of one video signal source, so that the video signal output timings of both sides match, and both output video Even when signals are superimposed, synchronization errors do not occur.
以下、本発明の一実施例を添付図面を参照して説明する
。Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings.
第１図は、本発明の一実施例に係る映像表示装置を示す
構成図である。この第１図において、１は第１の映像信
号発生器を示し、この第１の映像信号発生器１は基準ク
ロック信号発生回路２とＣＲＴ制御回路３と映像信号出
力回路４とを備える。FIG. 1 is a configuration diagram showing a video display device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 indicates a first video signal generator, and the first video signal generator 1 includes a reference clock signal generation circuit 2, a CRT control circuit 3, and a video signal output circuit 4.
そして、基準クロック信号発生回路２が出力する基準ク
ロック信号に基づいて、ＣＲＴ制御回路３が映像信号作
成用の同期信号を作威し、この同期信号を映像信号出力
回路４に供給し、この同期信号に同期した映像信号を映
像信号出力回路４が出力する。また、ＣＲＴ制御回路３
が出力する同期信号を、後述する同期検出回路９のブリ
ップフロップ回路１０及びＣＲＴモニタ１３に供給する
。Then, based on the reference clock signal outputted from the reference clock signal generation circuit 2, the CRT control circuit 3 generates a synchronization signal for creating a video signal, supplies this synchronization signal to the video signal output circuit 4, and outputs the synchronization signal. A video signal output circuit 4 outputs a video signal synchronized with the signal. In addition, the CRT control circuit 3
A synchronization signal outputted by the synchronization detection circuit 1 is supplied to a flip-flop circuit 10 of a synchronization detection circuit 9 and a CRT monitor 13, which will be described later.
また、図中５は第２の映像信号発生器を示し、この第２
の映像信号発生器５は基準クロック信号発生回路６とＣ
ＲＴ制御回路７と映像信号出力回路８とを備える。そし
て、基準クロック信号発生回路６が出力する基準クロッ
ク信号を、同期検出回路９の論理積回路１１の一方の入
力端子に供給し、この論理積回路１１の論理積出力をＣ
ＲＴ制御回路７に供給する。Further, 5 in the figure indicates a second video signal generator, and this second
The video signal generator 5 includes a reference clock signal generation circuit 6 and C
It includes an RT control circuit 7 and a video signal output circuit 8. Then, the reference clock signal output from the reference clock signal generation circuit 6 is supplied to one input terminal of the AND circuit 11 of the synchronization detection circuit 9, and the AND output of this AND circuit 11 is
It is supplied to the RT control circuit 7.
ＣＲＴ制御回路７は、この論理積出力に基づいて映像信
１号作成用の同期信号を作成し、この同期信号に同期し
た映像信号を映像信号出力回路８が出力する。また、Ｃ
ＲＴ制御回路７が出力する同期信号を、同期検出回路９
のフリップフロップ回路１０に供給する。The CRT control circuit 7 creates a synchronization signal for creating video signal No. 1 based on this AND output, and the video signal output circuit 8 outputs a video signal synchronized with this synchronization signal. Also, C
The synchronization signal output from the RT control circuit 7 is sent to the synchronization detection circuit 9.
is supplied to the flip-flop circuit 10 of.
そして、同期検出回路９のフリップフロップ回路１０に
供給される第１及び第２の映像信号発生器１及び５内の
ＣＲＴ制御回路３及び７の出力同期信号の位相差を、こ
のブリップフロップ回路１０で検出し、位相差検出信号
をこのフリップフロップ回路１０から論理積回路１１の
他方の入力端子に供給する。Then, the phase difference between the output synchronization signals of the CRT control circuits 3 and 7 in the first and second video signal generators 1 and 5, which are supplied to the flip-flop circuit 10 of the synchronization detection circuit 9, is determined by the flip-flop circuit 10 of the synchronization detection circuit 9. The phase difference detection signal is supplied from this flip-flop circuit 10 to the other input terminal of the AND circuit 11.
そして、この論理積回路１１の論理積出力を、第２の映
像信号発生器５のＣＲＴ制御回路７にクロック信号とし
て供給する。The AND output of this AND circuit 11 is then supplied to the CRT control circuit 7 of the second video signal generator 5 as a clock signal.
そして、第１及び第２の映像信号発生器１及び５の映像
信号出力回路４及び８が出力する夫々の映像信号を、映
像合成回路１２に供給する。そして、この映像合成回路
１２で夫々の映像信号を合成し、合成した映像信号をＣ
ＲＴモニタ１３に供給する。このＣＲＴモニタ１３は、
映像合成回路１２から供給される映像信号の表示を、第
１の映像信号発生器１のＣＲＴ制御回路３が出力する同
期信号に基づいて行う。The video signals output from the video signal output circuits 4 and 8 of the first and second video signal generators 1 and 5 are then supplied to the video synthesis circuit 12. Then, the video synthesis circuit 12 synthesizes the respective video signals and converts the synthesized video signal into C.
The signal is supplied to the RT monitor 13. This CRT monitor 13 is
The video signal supplied from the video synthesis circuit 12 is displayed based on the synchronization signal output from the CRT control circuit 3 of the first video signal generator 1.
斯る構成により映像をＣＲＴモニタ１３に表示する際の
動作を説明すると、まず第Ｉ及び第２の映像信号発生器
１及び５の基準クロック信号発生回路２及び６は、最初
の状態では非同期の基準クロック信号を出力する。ここ
で、第１の映像信号発生器１の基準クロック信号と第２
の映像信号発生器５の出力同期信号との位相差が同期検
出回路９のフリップフロップ回路１０で検出される。To explain the operation when displaying an image on the CRT monitor 13 with such a configuration, first, the reference clock signal generation circuits 2 and 6 of the first and second video signal generators 1 and 5 are asynchronous in the initial state. Outputs a reference clock signal. Here, the reference clock signal of the first video signal generator 1 and the second
The phase difference between the output synchronization signal of the video signal generator 5 and the output synchronization signal of the video signal generator 5 is detected by the flip-flop circuit 10 of the synchronization detection circuit 9.
一方、第２の映像信号発生器５の基準クロック信号発生
回路６が出力する基準クロック信号は、論理積回路１１
を経由してＣＲＴ制御回路７に供給される如くしである
。このため、フリッププロップ回路１０が出力する位相
差検出信号と基準クロック信号との論理積出力により、
ＣＲＴ制御回路７が制御される。即ち、第１の映像信号
発生器１側の基準クロック信号と、第２の映像信号発生
器５側の基準クロック信号との位相が合っていないとき
には、論理積回路１１から論理積出力としてのクロック
信号が良好に出力されない、そして、第２の映像信号発
生器５側の基準クロック信号発生回路６からの基準クロ
ック信号の位相が、第１の映像信号発生器１側の基準ク
ロック信号と一致するようになると、フリップフロップ
回路１０で双方の同期信号の一致を検出するようになり
、論理積回路１１から基準クロック信号がそのまま出力
されるようになり、第１の映像信号発生器１側と同一位
相の基準クロック信号に基づいて、映像信号出力回路８
から映像信号が出力される。On the other hand, the reference clock signal outputted from the reference clock signal generation circuit 6 of the second video signal generator 5 is transmitted to the AND circuit 11.
The signal is supplied to the CRT control circuit 7 via the CRT control circuit 7. Therefore, due to the AND output of the phase difference detection signal outputted by the flip-flop circuit 10 and the reference clock signal,
CRT control circuit 7 is controlled. That is, when the reference clock signal on the first video signal generator 1 side and the reference clock signal on the second video signal generator 5 side are not in phase, the clock signal is output from the AND circuit 11 as an AND output. The signal is not output properly, and the phase of the reference clock signal from the reference clock signal generation circuit 6 on the second video signal generator 5 side matches the reference clock signal on the first video signal generator 1 side. Then, the flip-flop circuit 10 detects the coincidence of both synchronization signals, and the AND circuit 11 outputs the reference clock signal as it is, which is the same as that on the first video signal generator 1 side. Based on the phase reference clock signal, the video signal output circuit 8
A video signal is output from.
このようにして第１及び第２の映像信号発生器ｌ及び５
から、同一位相の基準クロック信号に基づいた映像信号
が出力されることで、映像合成回路１２に供給される双
方の映像信号の位相が一致し、両映像信号の合成が良好
に行われ、ＣＲＴモニタ１３に合成映像が良好に表示さ
れる。In this way, the first and second video signal generators l and 5
By outputting a video signal based on a reference clock signal of the same phase, the phases of both video signals supplied to the video synthesis circuit 12 match, and the synthesis of both video signals is performed satisfactorily. The composite video is displayed well on the monitor 13.
このように夫々異なる基準クロック信号発生回路２及び
６からの基準クロック信号に基づいた映像信号の合成が
良好に行えることで、例えば温度。In this way, video signals based on the reference clock signals from the different reference clock signal generation circuits 2 and 6 can be synthesized satisfactorily, so that, for example, the temperature can be adjusted.
振動等の外部要因による基準クロック信号の周波数変動
等が生じても、映像の合成が安定して行えると共に、夫
々の基準クロック信号発生回路２及び６の発振精度の相
異により映像の合成状態が乱れることが防止される。Even if the frequency of the reference clock signal fluctuates due to external factors such as vibration, video synthesis can be performed stably, and the video synthesis state can be changed due to the difference in the oscillation accuracy of the respective reference clock signal generation circuits 2 and 6. Disturbances are prevented.
本発明の映像表示装置によると、複数の映像信号源から
の映像信号が同期状態になり、映像の合成が良好に行え
る。According to the video display device of the present invention, video signals from a plurality of video signal sources are synchronized, and video can be synthesized satisfactorily.
第１図は本発明の一実施例に係る映像表示装置の構成図
である。
１・・・第１の映像信号発生器、２・・・基準クロック
信号発生器、４・・・映像信号出力回路、５・・・第２
の映像信号発生器、６・・・基準クロック信号発生器。
８・・・映像信号出力回路、９・・・同期検出回路、１
０・・・フリップフロップ回路、１２・・・映像合成回
路、１３・・・ＣＲＴモニタ。FIG. 1 is a configuration diagram of a video display device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... First video signal generator, 2... Reference clock signal generator, 4... Video signal output circuit, 5... Second
6... Reference clock signal generator. 8... Video signal output circuit, 9... Synchronization detection circuit, 1
0...Flip-flop circuit, 12...Video synthesis circuit, 13...CRT monitor.
Claims (1)
号源の出力映像信号とを、モニタ受像機に重畳して表示
させる映像表示装置において、前記第１及び第２の映像
信号源の出力映像信号の位相差を検出する同期検出回路
を設け、該同期検出回路の検出信号に基づいて前記第１
又は第２の映像信号源の映像信号出力タイミングを制御
することを特徴とする映像表示装置。1. In a video display device that displays an output video signal of a first video signal source and an output video signal of a second video signal source in a superimposed manner on a monitor receiver, the first and second video signals A synchronization detection circuit is provided for detecting a phase difference between the output video signals of the source, and based on the detection signal of the synchronization detection circuit, the first
Alternatively, a video display device characterized in that the video signal output timing of the second video signal source is controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20468489A JPH0370275A (en) | 1989-08-09 | 1989-08-09 | Video display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20468489A JPH0370275A (en) | 1989-08-09 | 1989-08-09 | Video display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0370275A true JPH0370275A (en) | 1991-03-26 |
Family
ID=16494595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20468489A Pending JPH0370275A (en) | 1989-08-09 | 1989-08-09 | Video display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0370275A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229573B1 (en) | 1998-03-13 | 2001-05-08 | Kabushiki Kaisha Toshiba | Synchronization control circuit |
-
1989
- 1989-08-09 JP JP20468489A patent/JPH0370275A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6229573B1 (en) | 1998-03-13 | 2001-05-08 | Kabushiki Kaisha Toshiba | Synchronization control circuit |
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