JPH0362926A - Manufacture of bump - Google Patents
Manufacture of bumpInfo
- Publication number
- JPH0362926A JPH0362926A JP19969789A JP19969789A JPH0362926A JP H0362926 A JPH0362926 A JP H0362926A JP 19969789 A JP19969789 A JP 19969789A JP 19969789 A JP19969789 A JP 19969789A JP H0362926 A JPH0362926 A JP H0362926A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- bump
- layer
- composition
- plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 238000007747 plating Methods 0.000 claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- 239000000203 mixture Substances 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 10
- 238000002844 melting Methods 0.000 claims abstract description 10
- 229910052745 lead Inorganic materials 0.000 abstract description 3
- 229910052718 tin Inorganic materials 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract 6
- 229910045601 alloy Inorganic materials 0.000 abstract 2
- 239000000956 alloy Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910020220 Pb—Sn Inorganic materials 0.000 description 1
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000010587 phase diagram Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半田を材料としたパップの製法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a pad using solder as a material.
(従来の技術)
テープキャリア方式又はフリップチップ方式等に分いて
はチップの表面の電極にバンプと称する突出した電極が
用いられている。第3図はその一例の断面図である。半
導体の基板1の表面に形成された集積回路は保護膜3に
よって覆われ、を極2の上部は保護膜3が開口され、こ
の開口部及びその周縁はバリアメタル4によって覆われ
ている。(Prior Art) In the tape carrier method, the flip chip method, and the like, protruding electrodes called bumps are used as electrodes on the surface of the chip. FIG. 3 is a sectional view of one example. An integrated circuit formed on the surface of a semiconductor substrate 1 is covered with a protective film 3. The protective film 3 has an opening above the pole 2, and this opening and its periphery are covered with a barrier metal 4.
このバリアメタルはバンプが第3図の場合、CuとTi
+CuとCr等で構成されている。T + rCr等が
!極側になる。このバリアメタルの表面にさらにCU層
5をメッキにより形成し、その上にマツシュルーム状の
半田層6が設けられている。In the case of the bump shown in Figure 3, this barrier metal is Cu and Ti.
+It is composed of Cu, Cr, etc. T + rCr etc! Be on the extreme side. A CU layer 5 is further formed by plating on the surface of this barrier metal, and a pine mushroom-shaped solder layer 6 is provided thereon.
このような構造のバンプは下記のようにして製造される
。A bump having such a structure is manufactured as follows.
電極2の部分の保護膜3を開口したウェーハの全面にバ
リアメタル層4を蒸着し、蒸着膜上にフォトレジストを
塗布し、フォトリノグラフィ工程により、電極2上邪の
バンプ形成の必要な個所に穴を開ける。次にこの穴にC
0層5金メッキにより形成し、さらにその上に半田層6
を同様にメッキにより形成してバンプを作る。その後に
フォトレジストを除去し、バンプ部以外の不要なバリア
メタル層4を除去する。A barrier metal layer 4 is deposited on the entire surface of the wafer with the protective film 3 open at the electrode 2 portion, a photoresist is applied on the deposited film, and a portion where bumps are required to be formed on the electrode 2 is formed by a photolinography process. make a hole in Next, C in this hole.
0 layer 5 is formed by gold plating, and a solder layer 6 is further formed on top of it.
Similarly, a bump is formed by plating. After that, the photoresist is removed, and unnecessary barrier metal layer 4 other than the bump portion is removed.
バンプ金属としてはP b/S n以外に、A u r
Cu等も使用されるが、本発明はバンプ金属が半田(
Pb/Sn)の場合に有用なものである。In addition to Pb/Sn, other bump metals include Aur
Cu, etc. can also be used, but in the present invention, the bump metal is solder (
Pb/Sn).
前述の半田層6の下方に設けられるCu層5ば、半田に
よるバンプの形成されたチップを、プリント基板等へ加
熱により接続する場合、加熱により半田層6が溶けて流
れバンプが潰れないように、Cu層5によって半田層6
を支える役目をしている。The Cu layer 5 provided below the solder layer 6 described above is designed to prevent the solder layer 6 from melting due to heating and crushing the bumps when the chip on which solder bumps are formed is connected to a printed circuit board or the like by heating. , solder layer 6 by Cu layer 5
It plays a supporting role.
(発明が解決しようとする課題)
前述のようにバンプ金属として半田を用いるときは、半
田層6とバリアメタル4との間にCu層5を設ける必要
があった。(Problems to be Solved by the Invention) When using solder as the bump metal as described above, it was necessary to provide the Cu layer 5 between the solder layer 6 and the barrier metal 4.
(課題を解決するための手段)
バリアメタルの上部に設けた半田層の組成が、半田層の
上層部付近にかいて融点が低くなるように変更してメッ
キを行うようにした。(Means for Solving the Problems) The composition of the solder layer provided on the upper part of the barrier metal is changed so that the melting point is lower near the upper layer of the solder layer, and plating is performed.
(作用)
バンプの表面の半田が融けても、内部の半田は融けない
ので、バンプが潰れることがない。(Function) Even if the solder on the surface of the bump melts, the solder inside does not melt, so the bump will not be crushed.
(実施例)
前述の従来例にかいて、フォトリングラフィにより′を
極2の上部に穴を開けたウェーハに半田メッキを行うの
であるが、最初は半田の組成のPbが多くなるようにし
、必要な高さlでメッキを形成し、その後配線基板との
接続に必要な厚さ(約5μ爪)のみをP b : S
n =38 : 62 (%)の最低の融点となる共晶
点の組成とする。具体的には、例えば、アルカノールス
ルホン酸系のメッキ液ヲ使用する。水液はメッキ液組成
・電流密度・メッキ液循環速度を変更することによって
、析出物の組成を変更できることが実験によって確認さ
れている。(Example) As in the conventional example described above, solder plating is performed on a wafer with a hole made at the top of pole 2 by photolithography, but initially the solder composition is made to have a large amount of Pb, Plating is formed to the required height l, and then only the thickness required for connection with the wiring board (approximately 5μ nails) is P b : S
The composition has a eutectic point, which is the lowest melting point of n = 38: 62 (%). Specifically, for example, an alkanolsulfonic acid-based plating solution is used. It has been experimentally confirmed that the composition of the precipitate can be changed by changing the plating solution composition, current density, and plating solution circulation speed.
第1図はこのようにして形成されたバンプの断面図であ
って、第3図の従来例と異々る所は、バリアメタル4の
上に融点の高い半田層7、例えばPb:5n=60:4
0(%)、を形成し、その表面に融点の低い半田層6、
例えばP b: S n =38 : 62(%)、を
形成したことである。第3図と同一の部分には同一の符
号を付しである。FIG. 1 is a sectional view of a bump formed in this manner, and is different from the conventional example shown in FIG. 60:4
0 (%), and a low melting point solder layer 6 on its surface.
For example, Pb:Sn=38:62(%). The same parts as in FIG. 3 are given the same reference numerals.
第2図はPbとSnとより逢る半田の状態図である。FIG. 2 is a state diagram of solder in which Pb and Sn meet more closely.
(発明の効果)
本発明によれば、200℃程度の低温でバンプを配線基
板に接続することができる。しかも、半田が流れてバン
プが潰れることがない。半田メッキ工程中のメッキ液組
成、電流密度、メッキ液循環速度等を変更するだけでよ
いから、工程が簡単になる。(Effects of the Invention) According to the present invention, bumps can be connected to a wiring board at a low temperature of about 200°C. Moreover, the solder will not flow and the bumps will not be crushed. The process is simplified because it is only necessary to change the plating solution composition, current density, plating solution circulation speed, etc. during the solder plating process.
第1図は本発明により製造したバンプの断面図、第2図
はP b −S nの金属状態図、第3図は従来の方法
によるバンプの断面図である。
1・・基板、2 ・電極、3・・・保護膜、4・・・バ
リアメタル、5・・Cu層、6・・半田層、7・・・融
点の高い半田層
萬
!
図
第
図
21陸
第 3 図FIG. 1 is a sectional view of a bump manufactured according to the present invention, FIG. 2 is a metal phase diagram of Pb-Sn, and FIG. 3 is a sectional view of a bump manufactured by a conventional method. 1: Substrate, 2: Electrode, 3: Protective film, 4: Barrier metal, 5: Cu layer, 6: Solder layer, 7: High melting point solder layer! Figure Figure 21 Land Figure 3
Claims (1)
、バンプ上層部の半田層の融点より高くなるように半田
層の組成を変更してメッキを行うことを特徴とするバン
プの製造方法。1. A method for producing a bump, which comprises performing plating by changing the composition of the solder layer so that the melting point of the solder layer in the lower layer of the bump near the barrier metal is higher than the melting point of the solder layer in the upper layer of the bump.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19969789A JPH0362926A (en) | 1989-07-31 | 1989-07-31 | Manufacture of bump |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19969789A JPH0362926A (en) | 1989-07-31 | 1989-07-31 | Manufacture of bump |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0362926A true JPH0362926A (en) | 1991-03-19 |
Family
ID=16412110
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19969789A Pending JPH0362926A (en) | 1989-07-31 | 1989-07-31 | Manufacture of bump |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0362926A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6455785B1 (en) * | 1998-10-28 | 2002-09-24 | International Business Machines Corporation | Bump connection with stacked metal balls |
-
1989
- 1989-07-31 JP JP19969789A patent/JPH0362926A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6455785B1 (en) * | 1998-10-28 | 2002-09-24 | International Business Machines Corporation | Bump connection with stacked metal balls |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0354114B1 (en) | Method of building solder bumps and resulting structure | |
US5186383A (en) | Method for forming solder bump interconnections to a solder-plated circuit trace | |
US3921285A (en) | Method for joining microminiature components to a carrying structure | |
US5075965A (en) | Low temperature controlled collapse chip attach process | |
US5311404A (en) | Electrical interconnection substrate with both wire bond and solder contacts | |
US4875617A (en) | Gold-tin eutectic lead bonding method and structure | |
CN100501982C (en) | Wiring board with semiconductor component | |
JP2001308129A (en) | Method of forming lead-free bumps | |
KR100733556B1 (en) | Bump forming method | |
US6258703B1 (en) | Reflow of low melt solder tip C4's | |
US6179200B1 (en) | Method for forming solder bumps of improved height and devices formed | |
US5877560A (en) | Flip chip microwave module and fabrication method | |
US4332343A (en) | Process for in-situ modification of solder comopsition | |
JP3232872B2 (en) | Solder bump formation method | |
JPH0362926A (en) | Manufacture of bump | |
JP2002217226A (en) | Solder bump forming method | |
JPS5958843A (en) | Manufacture of bump for flip chip | |
JP2893634B2 (en) | Connection structure of electronic components | |
JPH11233561A (en) | Mounting structure of semiconductor chip part | |
JPS5953708B2 (en) | Flip chip face bonding method | |
JPH05206221A (en) | Connection structure of ic chip and its method | |
JP2771616B2 (en) | Conductive paste for bump formation and bump formation method | |
JPS595639A (en) | Hybrid integrated circuit | |
JPH0613382A (en) | Bump structure of ic semiconductor device and its forming method | |
JPS5950094B2 (en) | Flip chip reflow bonding method |