JPH0358421A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0358421A JPH0358421A JP19344289A JP19344289A JPH0358421A JP H0358421 A JPH0358421 A JP H0358421A JP 19344289 A JP19344289 A JP 19344289A JP 19344289 A JP19344289 A JP 19344289A JP H0358421 A JPH0358421 A JP H0358421A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- film
- semiconductor substrate
- metal film
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000009713 electroplating Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000007747 plating Methods 0.000 claims description 19
- 230000005611 electricity Effects 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は半導体装置の製造方法に関し、特に、パイアホ
ールやスルーホールを金属膜で埋設する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of burying a via hole or a through hole with a metal film.
従来、パイアホールやスルーホール内に金属膜を埋設す
る方法として、例えば第３図（ａ）及び（ｂ）に示す方
法が用いられている。Conventionally, the method shown in FIGS. 3(a) and 3(b), for example, has been used as a method for embedding a metal film in a via hole or a through hole.
例えば、第３図（ａ）のように、ゲート電極２，ソース
電極３，ドレイン電極４及び絶縁膜５を形成した半導体
基板ｌの裏面に、ソース電極３に達する直径３０μｍφ
，深さ５０μｍのパイアホール６を開設する．そして、
半導体基板ｌの裏面にスバッタ法によりＴｉ（約１００
〜２００人）とＡｕ（約２０００人）を被著させ、金属
１ｆｌ７を形成する。For example, as shown in FIG. 3(a), on the back surface of the semiconductor substrate l on which the gate electrode 2, source electrode 3, drain electrode 4, and insulating film 5 are formed, a diameter of 30 μmφ reaching the source electrode 3 is placed.
, a pier hole 6 with a depth of 50 μm is opened. and,
Ti (approximately 100
~200 people) and Au (about 2000 people) to form metal 1fl7.
次に、第３図（ｂ）のように、前記金属膜７を利用した
電解めっき法により、金属膜７上にＡｕめっきＪＩＩ８
（約３０ａｍ）を戒長させ、このＡｕめっき膜８でパイ
アホール６を埋設する。Next, as shown in FIG. 3(b), Au plating JII8 is applied on the metal film 7 by electrolytic plating using the metal film 7.
(approximately 30 am), and the via hole 6 is filled with this Au plating film 8.
上述した従来の製造方法では、パイアホール６を含む半
導体基板１の裏面全体に金属膜７が存在し、この金属Ｉ
ｌｌ！１７の全面にＡｕめっき膜８が或長されるため、
パイアホール６が深い場合（例えば５０μｍ以上）、あ
るいは穴の径が小ざい場合（例えば２０μｍ以下）には
、パイアホーＪ１６の入り口でＡｕめっき膜８が戒長し
、パイアホール内部にＡｕめっき膜８が完全に成長しな
いうちに入り口付近を塞いでしまう。そのため、その後
に電解めっきを続けても、パイアホール６の内部に“す
“（空間）が発生し、パイアホール６内に金属を埋設す
ることができなくなる。In the conventional manufacturing method described above, the metal film 7 is present on the entire back surface of the semiconductor substrate 1 including the via hole 6, and this metal film 7 is
ll! Since the Au plating film 8 has a certain length on the entire surface of the plate 17,
When the pipe hole 6 is deep (for example, 50 μm or more) or the diameter of the hole is small (for example, 20 μm or less), the Au plating film 8 is stretched at the entrance of the pipe hole J16, and the Au plating film 8 is formed inside the pipe hole. It blocks the entrance area before it fully grows. Therefore, even if electrolytic plating is continued thereafter, a "space" (space) is generated inside the pire hole 6, making it impossible to embed metal in the pire hole 6.
このように、不完全な埋め込み状態で作られたＧａＡｓ
ＦＥＴ （主にパワー系トランジスタ）では、ソースイ
ンダクタンスが十分に低減できないため効率が上がらな
い、パイアホール内部の“″す゛が熱処理によって膨れ
てしまうことによる信頼度の低下等の問題が生じている
。In this way, GaAs made in an incompletely embedded state
FETs (mainly power transistors) have problems such as the efficiency not increasing because the source inductance cannot be reduced sufficiently, and the reliability decreasing due to the swell inside the pire hole due to heat treatment.
本発明はパイアホール内に確実に金属を埋設することが
できる製造方法を提｛』（することを目的とする。An object of the present invention is to provide a manufacturing method that can reliably embed metal in a pipe hole.
本発明の製造方法は、半導体基板に形成した電極に達す
る深い穴を該半導体基板又は絶縁膜に形成する工程と、
この穴を含む半導体基板又は絶縁膜の全面に前記電極に
接触した金属膜を被着する工程と、これを異方性エッチ
ングして前記六内の側面にのみ該金属膜を残す工程と、
前記電極を通して穴内の金属膜に通電を行う電解めっき
法により該穴内にめっき膜を成長させる工程とを含んで
いる。The manufacturing method of the present invention includes a step of forming a deep hole in the semiconductor substrate or an insulating film that reaches an electrode formed on the semiconductor substrate;
A step of depositing a metal film in contact with the electrode on the entire surface of the semiconductor substrate or insulating film including the hole, and a step of anisotropically etching this to leave the metal film only on the side surface of the inner part.
The method includes the step of growing a plating film in the hole by electrolytic plating in which electricity is applied to the metal film in the hole through the electrode.
この製造方法では、金属膜は穴の側面にのみ存在するた
め、電解めっき法によりめっき膜を戒長させる際に、め
っき膜が穴の入口部で成長し゛ζ穴を塞ぐことがなく、
穴内における空隙の発生が防止される。In this manufacturing method, the metal film exists only on the sides of the hole, so when the plating film is lengthened by electrolytic plating, the plating film grows at the entrance of the hole and does not block the hole.
Generation of voids within the hole is prevented.
次に、本発明を図面を参照して説明する．第１図（ａ）
乃至（Ｃ）は本発明の第１実施例を工程順に示す断面図
である。Next, the present invention will be explained with reference to the drawings. Figure 1(a)
1 to 3(C) are cross-sectional views showing the first embodiment of the present invention in the order of steps.
先ず、第１図（ａ）のように、半導体基板ｌの表面には
ゲート電極２．ソース電極３，ドレイン電極４を形成し
、絶縁膜５で覆ってＧａＡｓ ＦＥＴを形成している。First, as shown in FIG. 1(a), a gate electrode 2. is formed on the surface of a semiconductor substrate l. A source electrode 3 and a drain electrode 4 are formed and covered with an insulating film 5 to form a GaAs FET.
前記ソース電極３．ドレイン電極４はそれぞれＴ ｉ
／ Ａ ｕ構造に形成されている。そして、このソース
電極３の裏面側から半導体基板１にパイアホール６を開
設する．その上で、このパイアホール６を含む半導体基
板ｌの裏面に、スバッタ法によりＴ ｉ ／ Ａ ｕ構
造の金属膜７を被着する。この場合、金属膜７の膜厚は
通常、ＴｉがｌＯＯ〜２００人で、Ａｕが１５００ 〜
２５００人である。The source electrode 3. The drain electrodes 4 are each T i
/A u structure. A via hole 6 is then opened in the semiconductor substrate 1 from the back side of the source electrode 3. Thereafter, a metal film 7 having a Ti/Au structure is deposited on the back surface of the semiconductor substrate l including the via hole 6 by a sputtering method. In this case, the thickness of the metal film 7 is usually 100~200 for Ti and 1500~200 for Au.
There are 2,500 people.
次に、第１図（ｂ）のように、半導体基板ｌの裏面側か
らＣｌ系ガスによる異方性ドライエッチングを行ない、
前記金属ＩＩ！７をエッチングする。Next, as shown in FIG. 1(b), anisotropic dry etching is performed using a Cl-based gas from the back side of the semiconductor substrate l.
Said metal II! Etch 7.
このとき、エッチング或分は垂直方向のみであるので、
金属膜７はパイアホール６内の側面にのみ残される。At this time, since the etching is only in the vertical direction,
The metal film 7 is left only on the side surface inside the via hole 6.
その後、第１図（Ｃ）のように、ソース電極３及び金属
膜７を通して通電し、電解めっき法によりパイアホール
６内にＡｕめっき膜８をｒａ長させる。この時、パイア
ホール６の入り口部には金属膜７が存在していないので
、めっき処理中に入り口が塞がることがなく、パイアホ
ール６の内部に完全にＡｕめっき膜８を成長させること
ができる。Thereafter, as shown in FIG. 1C, electricity is applied through the source electrode 3 and the metal film 7, and the Au plating film 8 is formed in the via hole 6 to a length of ra by electrolytic plating. At this time, since the metal film 7 is not present at the entrance of the pire hole 6, the entrance is not blocked during the plating process, and the Au plating film 8 can be completely grown inside the pire hole 6. .
第２図（ａ）乃至（ｄ）は本発明の第２実施例を工程順
に示す断面図である。FIGS. 2(a) to 2(d) are sectional views showing a second embodiment of the present invention in the order of steps.
先ず、第２図（ａ）のように、半導体基板ｌ１の表面に
第１層目の電極ｌ２を形成し、かっこの上にＴｉ／Ａｕ
構造の金属膜ｌ３を形成した後、フォトレジスト１４を
マスクとしてイオンミリングにより所要パターンに形成
する。First, as shown in FIG. 2(a), a first layer electrode l2 is formed on the surface of the semiconductor substrate l1, and a Ti/Au layer is formed on the parentheses.
After forming the structural metal film l3, a desired pattern is formed by ion milling using the photoresist 14 as a mask.
その後、第２図（ｂ）に示すように、全面に絶縁膜ｌ５
を形或した後、図外のフォトレジストをマスクにしてス
ルーホール１６をあける．次に、第２図（Ｃ）に示すよ
うに、スバッタ法により全面にＴｉ／Ａｕ構造の金属膜
ｌ７を被着させた後、Ｃｉ！．系ガスにより異方性エッ
チングを行い、スルーホール１６内の側壁のみに前記金
属膜ｌ７を残す。After that, as shown in FIG. 2(b), an insulating film l5 is formed on the entire surface.
After shaping, a through hole 16 is made using a photoresist (not shown) as a mask. Next, as shown in FIG. 2(C), a metal film 17 having a Ti/Au structure is deposited on the entire surface by a sputtering method, and then Ci! ．． Anisotropic etching is performed using a system gas, leaving the metal film 17 only on the side wall of the through hole 16.
その後、第２図（ｄ）のように、電解めっき法によりＡ
ｕめっきを行い、Ａｕめっき膜１８をスルーホールｌ６
の内部のみ成長させる。このとき、スルーホール１６の
入り口付近には金属１１１１７が存在していないので、
めっき成長中にスルーホールｌ６の入口が塞がってしま
うことはない。Then, as shown in Figure 2(d), A
U plating is performed, and the Au plating film 18 is formed into the through hole l6.
grow only inside. At this time, since there is no metal 11117 near the entrance of the through hole 16,
The entrance of the through hole l6 will not be blocked during the plating growth.
以上説明したように本発明は、半導体基板や絶縁膜に形
成した深い穴の内部側面にのみ金属膜を形成し、この金
属膜を利用した電解めっき法により穴内にめっき膜を成
長させているので、めっき膜が穴の入口部で成長して穴
を塞ぐことがなく、六内に空隙を発生させることなく金
属を六内に理設することができる効果がある。As explained above, in the present invention, a metal film is formed only on the inner side surface of a deep hole formed in a semiconductor substrate or an insulating film, and a plating film is grown inside the hole by electroplating using this metal film. This has the effect that the plating film does not grow at the entrance of the hole and block the hole, and metal can be placed inside the six without creating a void inside the six.
第１図（ａ）乃至（Ｃ）は本発明の第１実施例の製造方
法を工程順に示す断面図、第２図（ａ）乃至（ｄ）は本
発明の第２実施例の製造方法を工程順に示す断面図、第
３図（ａ）及び（ｂ）は従来の製造方法及びその不具合
を工程順に示す断面図である。
１・・・半導体基板、２・・・ゲート電極、３・・・ソ
ース電極、４・・・ドレイン電極、５・・・絶縁膜、６
・・・パイアホール、７・・・金属膜、８・・・Ａｕめ
っき膜、１ｌ・・・半導体基板、１２・・・第１層目配
線、１３・・・金属膜、１４・・・フォトレジスト、１
５・・・絶縁膜、１６・・・スルーホール、
ｌ
７・・・金属膜、
１８・・・Ａｕめっき膜。
第
ｌ
図
第２
図FIGS. 1(a) to (C) are cross-sectional views showing the manufacturing method of the first embodiment of the present invention in order of steps, and FIGS. 2(a) to (d) are sectional views showing the manufacturing method of the second embodiment of the present invention. 3(a) and 3(b) are cross-sectional views showing the conventional manufacturing method and its defects in the order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Gate electrode, 3... Source electrode, 4... Drain electrode, 5... Insulating film, 6
... Pier hole, 7 ... Metal film, 8 ... Au plating film, 1l ... Semiconductor substrate, 12 ... First layer wiring, 13 ... Metal film, 14 ... Photo resist, 1
5... Insulating film, 16... Through hole, l 7... Metal film, 18... Au plating film. Figure l Figure 2
Claims (1)
体基板又は電極を覆う絶縁膜に形成する工程と、この穴
を含む半導体基板又は絶縁膜の全面に前記電極に接触し
た金属膜を被着する工程と、これを異方性エッチングし
て前記穴内の側面にのみ該金属膜を残す工程と、前記電
極を通して穴内の金属膜に通電を行う電解めっき法によ
り該穴内にめっき膜を成長させる工程とを含むことを特
徴とする半導体装置の製造方法。1. Forming a deep hole in an insulating film that covers the semiconductor substrate or electrode, reaching the electrode formed on the semiconductor substrate, and depositing a metal film in contact with the electrode on the entire surface of the semiconductor substrate or insulating film, including this hole. a step of anisotropically etching this to leave the metal film only on the side surfaces inside the hole; and a step of growing a plating film inside the hole by electrolytic plating in which electricity is applied to the metal film inside the hole through the electrode. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19344289A JPH0358421A (en) | 1989-07-26 | 1989-07-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19344289A JPH0358421A (en) | 1989-07-26 | 1989-07-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0358421A true JPH0358421A (en) | 1991-03-13 |
Family
ID=16308059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19344289A Pending JPH0358421A (en) | 1989-07-26 | 1989-07-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0358421A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07144158A (en) * | 1993-11-26 | 1995-06-06 | Nobumi Takayama | Spraying machine |
| JP2005277173A (en) * | 2004-03-25 | 2005-10-06 | Sanyo Electric Co Ltd | Semiconductor device, and its manufacturing method |
| US7144761B2 (en) | 2000-10-26 | 2006-12-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2007005402A (en) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | Method of forming through interconnection line in semiconductor substrate |
| JP2012235134A (en) * | 2003-09-23 | 2012-11-29 | Micron Technology Inc | Process and integration scheme for manufacturing semiconductor components including conductive components, through vias and conductive through wafer vias |
-
1989
- 1989-07-26 JP JP19344289A patent/JPH0358421A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07144158A (en) * | 1993-11-26 | 1995-06-06 | Nobumi Takayama | Spraying machine |
| US7144761B2 (en) | 2000-10-26 | 2006-12-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2012235134A (en) * | 2003-09-23 | 2012-11-29 | Micron Technology Inc | Process and integration scheme for manufacturing semiconductor components including conductive components, through vias and conductive through wafer vias |
| US9287207B2 (en) | 2003-09-23 | 2016-03-15 | Micron Technology, Inc. | Methods for forming conductive vias in semiconductor device components |
| JP2005277173A (en) * | 2004-03-25 | 2005-10-06 | Sanyo Electric Co Ltd | Semiconductor device, and its manufacturing method |
| JP2007005402A (en) * | 2005-06-21 | 2007-01-11 | Matsushita Electric Works Ltd | Method of forming through interconnection line in semiconductor substrate |
| JP4552770B2 (en) * | 2005-06-21 | 2010-09-29 | パナソニック電工株式会社 | Method for forming through wiring on semiconductor substrate |
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