JPH03248534A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH03248534A JPH03248534A JP2044628A JP4462890A JPH03248534A JP H03248534 A JPH03248534 A JP H03248534A JP 2044628 A JP2044628 A JP 2044628A JP 4462890 A JP4462890 A JP 4462890A JP H03248534 A JPH03248534 A JP H03248534A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- insulating film
- layer
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000010410 layer Substances 0.000 claims abstract description 34
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 7
- 238000002844 melting Methods 0.000 abstract description 4
- 230000008018 melting Effects 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 20
- 229910045601 alloy Inorganic materials 0.000 description 10
- 239000000956 alloy Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、半導体素子におけるコンタクト孔埋込み配
線形成に際し、深いコンタクト孔も浅いコンタクト孔の
両方ともに断線することなく、良好に形成できるように
した半導体素子の製造方法に関するものである。[Detailed Description of the Invention] (Industrial Field of Application) The present invention enables the formation of buried wiring in contact holes in semiconductor devices, in which both deep contact holes and shallow contact holes can be formed satisfactorily without disconnection. The present invention relates to a method for manufacturing a semiconductor element.
（従来の技術）
半導体素子において、配線構造は従来第３図に示すよう
に形成されている。この第３図において、まず、ＩＣ基
板１に素子分離のための絶縁膜２（例えば５ｉＪ） 、
拡散層３を形成した後、絶縁膜４（例えばＢＰＳＧ）を
ＣＶＤ法にて形成する。(Prior Art) In a semiconductor device, a wiring structure is conventionally formed as shown in FIG. In FIG. 3, first, an insulating film 2 (for example, 5iJ) for element isolation is placed on an IC substrate 1.
After forming the diffusion layer 3, an insulating film 4 (for example, BPSG) is formed by CVD.
その後、コンタクトとなる開孔部５を形成し、その後配
線となるＡｌ−５ｉ系合金膜６をスパッタ法で形成し、
配線パターンをホトリソ・エツチングで得る。これによ
って半導体素子が完成する。After that, an opening 5 that will become a contact is formed, and then an Al-5i alloy film 6 that will become a wiring is formed by sputtering.
Obtain the wiring pattern by photolithography and etching. This completes the semiconductor device.
しかしながら、集積度が増加するにつれて、コンタクト
の開孔部５の径は小さくなり、アスペクト比（径と深さ
の比）が大きくなるにつれて、第３図の従来の製造方法
では、Ａｌ−５ｉ合金膜６のステップカバレージが悪く
なり、断線となる。そのため、コンタクト孔内部を金属
で埋め込む技術が開発されてきている。However, as the degree of integration increases, the diameter of the aperture 5 of the contact becomes smaller, and as the aspect ratio (ratio of diameter to depth) becomes larger, the conventional manufacturing method shown in FIG. The step coverage of the film 6 deteriorates, resulting in disconnection. Therefore, techniques have been developed to fill the inside of the contact hole with metal.
その一つとして、選択ＷＣＶＤ法を例に用いて第４図に
より説明する。この第４図において、ＩＣ基板１１に先
程と同様に素子分離絶縁膜１２゜拡散層１３を形成した
後絶縁膜１４を形成し、コンタクトとなる開孔部１５を
形成する。そして、選択ＷＣＶＤ法により、Ｗｌ１１１
６を開孔部１５と絶縁膜１４の段差が生じない程度に形
成する。その後、Ａｌ−５ｉ系合金膜１７をスパッタ法
で形成し、ホトリソ・エツチングによりパターニングす
る。As one of them, the selective WCVD method will be explained with reference to FIG. 4 as an example. In FIG. 4, an element isolation insulating film 12 and a diffusion layer 13 are formed on an IC substrate 11 in the same manner as before, and then an insulating film 14 is formed, and an opening 15 that becomes a contact is formed. Then, by selective WCVD method, Wl111
6 is formed to such an extent that no difference in level between the opening 15 and the insulating film 14 occurs. Thereafter, an Al-5i alloy film 17 is formed by sputtering and patterned by photolithography and etching.
このような方法によれば、コンタクト孔内を金属で埋め
込めるため、ステップカバレージの悪化による断線を防
ぐことができ、信鯨性の高い配線構造を得ることができ
る。According to such a method, since the inside of the contact hole can be filled with metal, disconnection due to deterioration of step coverage can be prevented, and a wiring structure with high reliability can be obtained.
しかしながら、実際に用いられる半導体素子のコンタク
ト孔は第５図のように、拡散層２３上だけではなく、電
極層２５上も存在する。However, as shown in FIG. 5, the contact holes of the semiconductor element actually used exist not only on the diffusion layer 23 but also on the electrode layer 25.
すなわち、第５図において、第４図の場合と同様にＩＣ
基板２１上に素子分離絶縁膜２２．拡散層２３を形成し
た後、絶縁膜２４を形成し、この絶縁膜２４内に電極層
２５を埋め込み、拡散層２３上と電極層２５上のコンタ
クト孔２６．２７を形成した後、コンタクト孔２６．２
７にそれぞれＷ膜２Ｂ、２９を形成し、しかる後に、Ａ
ｌ−３ｉ系台金膜３０を形成してパターニングする。That is, in FIG. 5, as in the case of FIG.
An element isolation insulating film 22 is formed on the substrate 21. After forming the diffusion layer 23, an insulating film 24 is formed, an electrode layer 25 is embedded in the insulating film 24, contact holes 26 and 27 are formed on the diffusion layer 23 and the electrode layer 25, and then the contact hole 26 is formed. .2
W films 2B and 29 are formed on A and A, respectively.
An l-3i base metal film 30 is formed and patterned.
（発明が解決しようとする課題）
このように、第５図の例では、拡散層２７上および電極
層２５上のコンタクト孔２６．コンタクト孔２７を同時
に選択ＷＣＶＤ法でＷ膜２８．Ｗ膜２９を形成すること
になる。(Problem to be Solved by the Invention) As described above, in the example of FIG. 5, the contact hole 26 on the diffusion layer 27 and the electrode layer 25. Contact hole 27 is simultaneously selected by WCVD method to form W film 28. A W film 29 will be formed.
この２種類のコンタクト孔２６．コンタクト孔２７のう
ち、コンタクト孔２７の方が浅いため、埋め込まれるＷ
膜２９の厚さはコンタクト孔２７における絶縁膜２４と
段差が生じない程度に抑えなければならない。These two types of contact holes 26. Among the contact holes 27, since the contact hole 27 is shallower, the buried W
The thickness of the film 29 must be suppressed to such an extent that no difference in level from the insulating film 24 in the contact hole 27 occurs.
したがって、深い方のコンタクト孔２６内のＷ膜２８の
厚さはＷ膜２９と同じであるため、コンタクト孔２６は
完全に埋め込まれておらず、配線層となるＡｌ−５ｉ系
合金膜３０をスパッタ法で形成する際、ステップカバレ
ージの悪化により、コンタクト孔２６内では、Ａｌ−５
ｉ系合金膜３０が断線する可能性がある。Therefore, since the thickness of the W film 28 in the deeper contact hole 26 is the same as that of the W film 29, the contact hole 26 is not completely filled, and the Al-5i alloy film 30 serving as the wiring layer is When forming the contact hole 26 by sputtering, due to deterioration of step coverage, Al-5
There is a possibility that the i-based alloy film 30 will be disconnected.
また、前記ステップカバレージを良くするために、コン
タクト孔２６のＷ膜２８の膜厚を厚くすると、コンタク
ト孔２７でのＷ膜２９が絶縁膜２４よりあふれ、上方お
よび左右へＷ膜が成長するため、平坦性の悪化および、
層内ショートという問題が発生する。Furthermore, if the thickness of the W film 28 in the contact hole 26 is increased in order to improve the step coverage, the W film 29 in the contact hole 27 overflows from the insulating film 24, causing the W film to grow upward and to the left and right. , worsening of flatness and
A problem of intralayer short circuit occurs.
これらのために、深さの異なるコンタクト孔への選択Ｗ
ＣＶＤ法は技術的に満足できるものは得られなかった。For these reasons, selection of contact holes with different depths W
The CVD method did not yield a technically satisfactory result.
この発明は前記従来技術が持っている問題点のうち、深
さの異なるコンタクト孔に選択ＷＣＶＤ法を用いる際、
浅いコンタクト孔を埋め込んでも、深いコンタクト孔は
完全に埋め込むことができないために、配線層となるＡ
ｌ−３ｉ系合金膜をスパッタする際、ステップカバレー
ジ悪化による断線が生じるという問題点について解決し
た半導体素子の製造方法を提供するものである。This invention addresses the problems of the prior art when using selective WCVD for contact holes with different depths.
Even if shallow contact holes are filled, deep contact holes cannot be completely filled, so A
The present invention provides a method for manufacturing a semiconductor device that solves the problem of wire breakage occurring due to poor step coverage when sputtering an l-3i alloy film.
この発明は前記問題点を解決するために半導体素子の製
造方法において、半導体基板上に素子分離用の絶縁膜を
形成して拡散層形成後に第１の層間絶縁膜を形成する工
程と、Ａｓを含む高融点のＷポリサイド膜を第１の層間
絶縁膜上に形成した後筒２の層間絶縁膜を形成して拡散
層上には深いコンタクト孔を形成し、かつＷポリサイド
膜上には浅いコンタクト孔を形成する工程と、深いコン
タクト孔のみにＷ膜を埋め込み、かつ浅いコンタクト孔
にはＷ膜を埋め込まない工程とを導入したものである。In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device, including a step of forming an insulating film for device isolation on a semiconductor substrate and forming a first interlayer insulating film after forming a diffusion layer; A high melting point W polycide film including a high melting point W polycide film is formed on the first interlayer insulating film, and a deep contact hole is formed on the diffusion layer, and a shallow contact is formed on the W polycide film. This method introduces a step of forming a hole and a step of filling only the deep contact hole with the W film and not filling the shallow contact hole with the W film.
（作 用）
この発明によれば、半導体素子の製造方法において、以
上のような工程を導入したので、浅いコンタクト孔と深
いコンタクト孔の形成後、選択ＷＣＶＤ法によりＷ膜を
形成させると、深いコンタクト孔のみに第２の層間絶縁
膜と段差の生じない程度にＷ膜を埋め込まれ、浅いコン
タクト孔はその下地となるＷポリサイド膜にはＡｓが含
まれているから、Ｗ膜が成長しなくなり、後工程で、配
線層を形成しても、浅いコンタクト孔での配線層のステ
ップカバレージを悪化するレベルまで浅いコンタクト孔
が盛り上がらなくなり、したがって前記問題点を除去で
きる。(Function) According to the present invention, since the above-described steps are introduced in the method for manufacturing a semiconductor element, when a W film is formed by selective WCVD after forming a shallow contact hole and a deep contact hole, a deep contact hole is formed. Only the contact hole is filled with the W film to such an extent that there is no difference in level from the second interlayer insulating film, and the W film that forms the base of the shallow contact hole contains As, so the W film does not grow. Even if a wiring layer is formed in a post-process, the shallow contact hole does not swell to a level that deteriorates the step coverage of the wiring layer in the shallow contact hole, and thus the above-mentioned problem can be eliminated.
（実施例）
以下、この発明の半導体素子の製造方法の実施例につい
て図面に基づき説明する。第１図（ａ）ないし第１図（
ｃ）はその一実施例の工程断面図であり、まず第１図（
ａ）に示すように、半導体基板としてＳｔ基板３１に素
子分離のための絶縁膜３２（例えば５ｉｆｔ ）を形成
し、拡散層３３を形成した後、第１の層間絶縁膜３４（
例えばＢＰＳＧ）をＣＶＤ法にて５０００人形成する。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
c) is a process cross-sectional view of one example, and first of all, Fig. 1 (
As shown in a), after forming an insulating film 32 (for example, 5ift) for element isolation on an St substrate 31 as a semiconductor substrate and forming a diffusion layer 33, a first interlayer insulating film 34 (
For example, 5,000 people (BPSG) are formed using the CVD method.
次いで、この第１の層間絶縁膜３４の表面を平坦にさせ
るフロー熱処理を行う。この熱処理はＮｔ雰囲気で９５
０°Ｃ２１５分行う。Next, flow heat treatment is performed to flatten the surface of this first interlayer insulating film 34. This heat treatment was carried out at 95°C in an Nt atmosphere.
Perform at 0°C for 215 minutes.
次に、第１の層間絶縁膜３４が平坦になった後、電極と
なるＷポリサイド（ＷＳｉｘ）膜３５を形成する。この
作成方法は、まずポリシリコン膜をＣＶＤ法にて１００
０〜１５００人形成スル、ソの後、ドーパントとなる不
純物をポリシリコンに含ませる０通常リン（Ｐ）が−船
釣であるが、ここでは、選択Ｗの成長を行わせないこと
が目的であるので、Ａｓをイオンインプランテーション
法によって打ち込む。Next, after the first interlayer insulating film 34 is flattened, a W polycide (WSix) film 35 that will become an electrode is formed. In this production method, first, a polysilicon film with a thickness of 100% is formed using the CVD method.
After the formation of 0 to 1500 people, an impurity that will become a dopant is added to the polysilicon. Normally, phosphorus (P) is used for boat fishing, but here the purpose is to prevent the growth of selection W. Therefore, As is implanted by the ion implantation method.
このイオンインプランテーションの条件は、４０ＫｅＶ
Ｉ ＸＩＱＩ６ｔｏｎｓ／ｃｄで行う、そして、Ｗ
Ｓ ｉ膜をスパッタ法にて１５００人形成し、前述の
ポリシリコン層／ＷＳｉ層をホトリソ・エツチングでパ
ターニングする。そして、第２の層間絶縁膜３６（例え
ばＢＰＳＧ）をＣＶＤ法にて５０００人形成し、平坦に
させるフロー熱処理を行う。The conditions for this ion implantation are 40KeV
Performed with I XIQI6tons/cd, and W
A 1,500 Si film is formed by sputtering, and the aforementioned polysilicon layer/WSi layer is patterned by photolithography and etching. Then, a second interlayer insulating film 36 (for example, BPSG) is formed using the CVD method, and a flow heat treatment is performed to flatten the film.
この熱処理条件はＮ！雰囲気で９５０°Ｃ１１５分行う
。この熱処理によって、前述のポリシリコン層／ＷＳｉ
層はＡｓを含む高融点金属のＷポリサイド膜３５となる
。This heat treatment condition is N! It is carried out in an atmosphere at 950°C for 115 minutes. By this heat treatment, the aforementioned polysilicon layer/WSi
The layer is a W polycide film 35 of a high melting point metal containing As.
その後、第１図（ｂ）に示すように、ホトリソ・エツチ
ングにより拡散層３３上およびＷポリサイド膜３５上に
コンタクト孔３７．３８をそれぞれ形成する。Thereafter, as shown in FIG. 1(b), contact holes 37 and 38 are respectively formed on the diffusion layer 33 and the W polycide film 35 by photolithography and etching.
コンタクト孔３７．３８のエツチングはＲＩＥ（リアク
ティブ・イオン・エツチング）を用い、ＲＩＥはＣｌＦ
３１５ ｓｃｃｍ＋、 ＣＨＦ３２０５ｅｃ（圧力８０
ｐａ、 ＲＦパワー４００Ｗで行う。The contact holes 37 and 38 are etched using RIE (reactive ion etching), and RIE is performed using ClF.
315 sccm+, CHF3205ec (pressure 80
pa, RF power of 400W.
コンタクト孔３７．３８開孔後、選択ＷＣＶＤ（化学気
相反応）法にてＷ膜３９を深いコンタクト孔３７内には
、この層間絶縁膜３６と段差が生じない程度に形成する
。この時、Ｗポリサイド膜３５上の浅いコンタクト孔３
８には、ＡｓをＷポリサイド内に含有させているために
、Ｗ膜の成長はなく、コンタクト孔３８があいたままの
状態となっている。After the contact holes 37 and 38 are opened, a W film 39 is formed in the deep contact hole 37 by selective WCVD (chemical vapor phase reaction) to such an extent that no difference in level from the interlayer insulating film 36 occurs. At this time, the shallow contact hole 3 on the W polycide film 35
In No. 8, since As is contained in the W polycide, there is no growth of the W film, and the contact hole 38 remains open.
その後、第１図（ｃ）に示すように、配線層となるＡｌ
−５ｉ系合金膜４０をスパッタ法にて６０００人形成し
た後、ホトリソ・エツチングを行い、配線パターンを得
る。After that, as shown in FIG. 1(c), Al
After forming 6,000 -5i alloy films 40 by sputtering, photolithography and etching are performed to obtain wiring patterns.
また、Ａｓはポリシリコン層形成後だけとは限らず、コ
ンタクト孔３７．３８を形成した後に浅いコンタクト孔
３８に選択的にイオンインプランテーションにより打ち
込んでもよい。Ｐの濃度よりもＡｓの濃度の方が高い時
にＷ膜の成長は起こらなくなる。Furthermore, As is not limited to being implanted only after forming the polysilicon layer, but may also be implanted selectively into the shallow contact hole 38 by ion implantation after the contact holes 37 and 38 are formed. When the As concentration is higher than the P concentration, the W film does not grow.
第２図はこのＷ膜の成長が起こらない様子を顕微鏡写真
から転写して示した図であり、図中のＷポリサイドＡの
領域でＷがついていないことが示されている（図中空白
で示す部分）。Figure 2 is a diagram transcribing from a microscopic photograph showing how this W film does not grow, and it is shown that there is no W attached in the region of W polycide A in the figure (blank in the figure). (part shown).
Ｐを用いてＷポリサイド膜３５を形成した場合には、選
択ＷＣＶＤ法でコンタクト孔３７内にＷ膜３９を形成す
る時、浅いコンタクト孔３８内には選択Ｗの成長が正常
に起こるのに対して、Ａｓを用いて、Ｗポリサイド膜３
５を形成後に選択ＷＣＶＤ法でコンタクト孔３７にＷ膜
３９を形成すると、浅いコンタクト孔３８内Ｗ膜の成長
が起こらないのは、Ｗポリサイド膜３５の表面の状態に
違いがあると考えられるが、詳しいことはよくわかって
いない。When the W polycide film 35 is formed using P, selective W growth normally occurs in the shallow contact hole 38 when the W film 39 is formed in the contact hole 37 by the selective WCVD method. Then, using As, a W polycide film 3 is formed.
When the W film 39 is formed in the contact hole 37 by the selective WCVD method after the formation of the W polycide film 35, the reason why the W film does not grow in the shallow contact hole 38 is thought to be that there is a difference in the surface condition of the W polycide film 35. , the details are not well known.
（発明の効果）
以上詳細に説明したように、この発明によれば、浅いコ
ンタクト孔の下地をＡｓを含むＷポリサイド膜としたの
で、Ｓｉが下地である深いコンタクト孔が同時に存在す
るウェハに選択ＷＣＶＤを行っても、Ｗポリサイドが下
地である浅いコンタクト孔にはＷは成長されなくなり、
深いコンタクト孔に選択Ｗ膜を埋込むことができ、深い
コンタクト孔でのスパッタＡｌ−５ｉ系合金膜のステッ
プカバレージの悪化はなくなる。(Effects of the Invention) As explained in detail above, according to the present invention, since the base of the shallow contact hole is a W polycide film containing As, it is selected for use in a wafer in which there is also a deep contact hole with Si as the base. Even if WCVD is performed, W will no longer grow in shallow contact holes with W polycide as the base.
The selective W film can be buried in the deep contact hole, and step coverage of the sputtered Al-5i alloy film in the deep contact hole does not deteriorate.
また、選択Ｗ膜が成長しない浅いコンタクト孔はスパッ
タＡｌ−５ｉ系合金のステップカバレージが悪化するレ
ベルではなく、断線のない良好な半導体素子の実現が可
能となる。Further, the shallow contact hole in which the selective W film does not grow is not at a level where the step coverage of the sputtered Al-5i alloy is deteriorated, and it is possible to realize a good semiconductor device without disconnection.
第１図（ａ）ないし第１図（ｃ）はこの発明の半導体素
子の製造方法の工程断面図、第２図は選択Ｗ膜の非成長
性の説明図、第３図ないし第５図はそれぞれ従来の異な
る半導体素子の製造方法の説明図である。
３１・・・Ｓｉ基板、３２・・・絶縁膜、３３・・・拡
散層、３４・・・第１の層間絶縁膜、３５・・・Ｗポリ
サイド膜、３６・・・第２の層間絶縁膜、３７．３８・
・・コンタクト孔、３９・・・Ｗ膜、４０・・・Ａｌ−
５ｉ系合金膜。
（ｂ）
本発明の工程断面図
第１図
（ｃ）
本発明の工程断面図
第
図
本発明のコンタクト孔の説明図
第
図
１
：ＩＣ基板
３：拡散層
５：開孔部
６：Ａ４−５
系合金膜
従来の製造方法の説明図
第
３
１：ＩＣ基板
２：素子分離絶縁膜
３：拡散層
４：絶縁膜
５：開孔部
６：Ｗ膜
７：ヘノ−Ｓｉ系合金膜
従来の製造方法の説明図
第
図1(a) to 1(c) are process cross-sectional views of the method for manufacturing a semiconductor element of the present invention, FIG. 2 is an explanatory diagram of the non-growth property of the selective W film, and FIGS. 3 to 5 are FIGS. 3A and 3B are explanatory diagrams of different conventional methods of manufacturing semiconductor elements; FIGS. 31... Si substrate, 32... Insulating film, 33... Diffusion layer, 34... First interlayer insulating film, 35... W polycide film, 36... Second interlayer insulating film , 37.38・
...Contact hole, 39...W film, 40...Al-
5i alloy film. (b) Process cross-sectional diagram of the present invention Figure 1 (c) Process cross-sectional diagram of the present invention Figure Explanatory diagram of the contact hole of the present invention Figure 1: IC substrate 3: Diffusion layer 5: Opening portion 6: A4- 5-based alloy film Explanatory diagram of conventional manufacturing method Part 3 1: IC substrate 2: Element isolation insulating film 3: Diffusion layer 4: Insulating film 5: Opening portion 6: W film 7: Heno-Si alloy film Conventional Explanatory diagram of manufacturing method
Claims (1)
層を形成し、かつ第１の層間絶縁膜を形成する工程と、 （ｂ）上記第１の層間絶縁膜上にＡｓを含むＷポリサイ
ド膜および第２の層間絶縁膜を形成した後このＡｓを含
むＷポリサイド膜上に浅いコンタクト孔を形成するとと
もに上記拡散層上に深いコンタクト孔を形成する工程と
、 （ｃ）上記深いコンタクト孔内にのみＷ膜を上記第２の
層間絶縁膜と段差を生じない程度にＷ膜を埋め込んだ後
に配線層を形成する工程と、 よりなる半導体素子の製造方法。[Scope of Claims] (a) forming a diffusion layer after forming an insulating film for element isolation on a semiconductor substrate, and forming a first interlayer insulating film; (b) the step of forming the first interlayer insulating film; After forming a W polycide film containing As and a second interlayer insulating film on the film, forming a shallow contact hole on the W polycide film containing As and forming a deep contact hole on the diffusion layer; (c) forming a wiring layer after burying a W film only in the deep contact hole to such an extent that no difference in level from the second interlayer insulating film is formed;
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2044628A JP2892421B2 (en) | 1990-02-27 | 1990-02-27 | Method for manufacturing semiconductor device |
| US07/658,239 US5192713A (en) | 1990-02-27 | 1991-02-20 | Method of manufacturing semiconductor devices having multi-layered structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2044628A JP2892421B2 (en) | 1990-02-27 | 1990-02-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03248534A true JPH03248534A (en) | 1991-11-06 |
| JP2892421B2 JP2892421B2 (en) | 1999-05-17 |
Family
ID=12696691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2044628A Expired - Lifetime JP2892421B2 (en) | 1990-02-27 | 1990-02-27 | Method for manufacturing semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5192713A (en) |
| JP (1) | JP2892421B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940010197A (en) * | 1992-10-13 | 1994-05-24 | 김광호 | Manufacturing Method of Semiconductor Device |
| JP3219909B2 (en) * | 1993-07-09 | 2001-10-15 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH07297194A (en) * | 1994-04-25 | 1995-11-10 | Sony Corp | Multichamber apparatus and manufacture of semiconductor device |
| US5512514A (en) * | 1994-11-08 | 1996-04-30 | Spider Systems, Inc. | Self-aligned via and contact interconnect manufacturing method |
| JP2710221B2 (en) * | 1995-01-25 | 1998-02-10 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| JP3397505B2 (en) * | 1995-04-19 | 2003-04-14 | 株式会社東芝 | Method for manufacturing semiconductor device |
| US5950099A (en) * | 1996-04-09 | 1999-09-07 | Kabushiki Kaisha Toshiba | Method of forming an interconnect |
| TW402809B (en) * | 1997-10-18 | 2000-08-21 | United Microelectronics Corp | The manufacture method of electrical charge storage structure |
| KR19990072936A (en) * | 1998-02-27 | 1999-09-27 | 가나이 쓰도무 | Isolator and modem unit using the same |
| KR100589490B1 (en) * | 2003-12-30 | 2006-06-14 | 동부일렉트로닉스 주식회사 | Method For manufacturing Semiconductor Devices |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
| US5108941A (en) * | 1986-12-05 | 1992-04-28 | Texas Instrument Incorporated | Method of making metal-to-polysilicon capacitor |
| JPH069200B2 (en) * | 1987-03-31 | 1994-02-02 | 株式会社東芝 | Method of forming metal wiring |
| US4764484A (en) * | 1987-10-08 | 1988-08-16 | Standard Microsystems Corporation | Method for fabricating self-aligned, conformal metallization of semiconductor wafer |
| JP2695861B2 (en) * | 1988-09-21 | 1998-01-14 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JPH0724261B2 (en) * | 1989-01-20 | 1995-03-15 | 株式会社東芝 | Method for manufacturing semiconductor device |
| JP2578193B2 (en) * | 1989-02-01 | 1997-02-05 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
| US4933297A (en) * | 1989-10-12 | 1990-06-12 | At&T Bell Laboratories | Method for etching windows having different depths |
| US4987099A (en) * | 1989-12-29 | 1991-01-22 | North American Philips Corp. | Method for selectively filling contacts or vias or various depths with CVD tungsten |
-
1990
- 1990-02-27 JP JP2044628A patent/JP2892421B2/en not_active Expired - Lifetime
-
1991
- 1991-02-20 US US07/658,239 patent/US5192713A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2892421B2 (en) | 1999-05-17 |
| US5192713A (en) | 1993-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5640041A (en) | Stress relaxation in dielectric before metallization | |
| US5476814A (en) | Method of manufacturing semiconductor device utilizing selective CVD method | |
| US5308786A (en) | Trench isolation for both large and small areas by means of silicon nodules after metal etching | |
| US5861671A (en) | Process for removing seams in tungsten plugs | |
| JPH03248534A (en) | Manufacture of semiconductor element | |
| US5700726A (en) | Multi-layered tungsten depositions for contact hole filling | |
| JPH02257640A (en) | Manufacture of semiconductor element | |
| JPH08288390A (en) | Semiconductor device and manufacture thereof | |
| JP3214445B2 (en) | Method for manufacturing semiconductor device | |
| JP3065395B2 (en) | Method for manufacturing semiconductor device | |
| JPH02162722A (en) | Manufacture of semiconductor device | |
| JP2702007B2 (en) | Method for manufacturing semiconductor device | |
| US20010016416A1 (en) | Method for fabricating contact plug | |
| US6887767B2 (en) | Method for manufacturing semiconductor device | |
| JPH01243526A (en) | Manufacture of semiconductor device | |
| JPH0234957A (en) | Manufacture of semiconductor device | |
| KR0175518B1 (en) | Structure of Metallization in Semiconductor Device and Manufacturing Method Thereof | |
| JPH04127425A (en) | Manufacture of semiconductor integrated circuit | |
| JP2840675B2 (en) | Method for manufacturing semiconductor device | |
| JPH0590207A (en) | Manufacture of semiconductor device | |
| JP2940986B2 (en) | Method for manufacturing semiconductor device | |
| JP2720567B2 (en) | Method for manufacturing semiconductor device | |
| JPH08293552A (en) | Forming method of plug | |
| JPH0521377A (en) | Manufacture of semiconductor device | |
| JPH04315425A (en) | Manufacture of semiconductor device |